CN115395768B - GaN device gate-source voltage oscillation suppression circuit with clamping function and method - Google Patents

GaN device gate-source voltage oscillation suppression circuit with clamping function and method Download PDF

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CN115395768B
CN115395768B CN202211200446.XA CN202211200446A CN115395768B CN 115395768 B CN115395768 B CN 115395768B CN 202211200446 A CN202211200446 A CN 202211200446A CN 115395768 B CN115395768 B CN 115395768B
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gate
diode
resistor
source voltage
gan device
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CN115395768A (en
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陈健
许建平
宋文胜
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Southwest Jiaotong University
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0038—Circuits or arrangements for suppressing, e.g. by masking incorrect turn-on or turn-off signals, e.g. due to current spikes in current mode control
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0048—Circuits or arrangements for reducing losses
    • H02M1/0054—Transistor switching losses
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Power Conversion In General (AREA)

Abstract

The invention provides a GaN device gate-source voltage oscillation suppression circuit with a clamping function and a method thereof, wherein the circuit comprises a diode D 1, a diode D 2, a clamping capacitor C 1, a decoupling capacitor C 2, a resistor R 1 and a resistor R 2, the anode end of the diode D 1 is connected to the gate of the GaN device, and the cathode end of the diode D 1 is connected to the source of the GaN device through the clamping capacitor C 1; the resistor R 1 is connected with the clamping capacitor C 1 in parallel, the anode end of the diode D 2 is connected to the driving power supply, the cathode end of the diode D 2 is grounded through the decoupling capacitor C 2, and the cathode end of the diode D 2 is also connected with the charging end of the clamping capacitor C 1 through the resistor R 2. The effect is that: the circuit design is simple, can effectively clamp gate source voltage to the protection device does not receive the damage, does not have the influence to device switching speed, and can not cause extra switching loss, does not receive the influence of grid resistance simultaneously, can increase switching speed and reduce switching loss, can reduce the risk of crosstalk moreover.

Description

GaN device gate-source voltage oscillation suppression circuit with clamping function and method
Technical Field
The invention relates to a switching element driving control technology, in particular to a GaN device gate-source voltage oscillation suppression circuit with a clamping function and a method thereof.
Background
Wide bandgap devices, such as GaN devices, are considered a promising device for power electronic conversion due to their excellent performance. Such applications include electric vehicles, aerospace systems, 5G communications. The small parasitic capacitance of GaN devices provides faster switching speeds allowing them to operate at high switching frequencies, thus increasing power density.
However, despite the many advantages of GaN devices, considerable challenges remain in terms of technology readiness, which hamper their further development. For example, switching oscillations of GaN devices are more severe due to fast switching speeds, and these overshoots make the devices easier to approach the breakdown limit in combination with the structural and material characteristics of GaN devices. Taking the gate-source voltage of a GaN device as an example, the maximum rated gate voltage of a commercial low-voltage normally-off device is relatively low. The maximum gate-source voltage of GaN devices from EPC company is typically 6V. However, the gate driving voltage is usually 5V, and the driving voltage is very close to the gate breakdown voltage, and the gate driving circuit needs to be carefully designed. One of the most conventional methods of suppressing gate-source voltage oscillations is to increase the gate resistance, but this method generally slows down the switching speed of the device and increases the switching losses. Optimizing the PCB layout may also suppress gate-source voltage oscillations. However, in practical applications, it is very difficult to further reduce these spurious parameters due to device packaging and PCB layout constraints. And as circuit parameters such as input parameters and switching frequency etc. change, it is difficult to ensure that the gate-source voltage does not exceed the maximum rated value. In the prior art, a learner can finally obtain a model of the gate-source opening voltage by modal division of the device opening process, and can predict the peak value of the gate-source voltage through the model. However, a method that can effectively suppress the gate-source voltage oscillation is not proposed. In addition, there have been studies to suppress switching oscillations by active gate driving or clamping circuits, but these designs are mainly used to suppress gate-source voltage false turn-on and parasitic oscillations of drain-source voltage. Therefore, the existing research lacks an effective protection method for device damage caused by gate-source voltage overshoot of the GaN device. Since the margin between the gate driving voltage and the maximum rated voltage of the GaN device is relatively small, careful optimization and design of the gate driving circuit are required.
Disclosure of Invention
In view of the above-mentioned needs, a primary object of the present invention is to provide a GaN device gate-source voltage oscillation suppression circuit with clamping function for effectively suppressing gate-source voltage overshoot of a GaN device.
In order to achieve the above purpose, the specific technical scheme adopted by the invention is as follows:
The GaN device gate-source voltage oscillation suppression circuit with the clamping function is characterized by comprising a diode D 1, a diode D 2, a clamping capacitor C 1, a decoupling capacitor C 2, a resistor R 1 and a resistor R 2, wherein the anode end of the diode D 1 is connected to the gate of the GaN device, and the cathode end of the diode D 1 is connected to the source of the GaN device through the clamping capacitor C 1; the resistor R 1 is connected with the clamping capacitor C 1 in parallel, the anode end of the diode D 2 is connected to the driving power supply, the cathode end of the diode D 2 is grounded through the decoupling capacitor C 2, and the cathode end of the diode D 2 is also connected with the clamping capacitor C 1 through the resistor R 2, so that the driving power supply charges the clamping capacitor C 1 after passing through the diode D 2 and the resistor R 2.
Optionally, the resistance of the resistor R 1 is greater than the resistance of the resistor R 2.
Optionally, the driving power supply is connected with a driving chip, and a driving signal output by the driving chip is loaded onto the gate of the GaN device after passing through the gate resistor R G and the gate inductor L G.
Optionally, let the difference between the maximum voltage of the clamp capacitor C 1 and V G-VD2 be Δv C1, the magnitude of Δv C1 is set according to the relationship between Δv C1 and the capacitance of the clamp capacitor C 1, where V G is the driving voltage output by the driving power supply, and V D2 is the step-down value of the diode D 2.
Optionally, the driving chip adopts LM5114, and the driving voltage of the driving power is 5V.
Optionally, the capacitance of the clamping capacitor C 1 is >20nF.
Optionally, the capacitance of the clamping capacitor C 1 is 47nF, the resistance of the resistor R 1 is 2kΩ, the resistance of the resistor R 2 is 2 Ω, and the capacitance of the decoupling capacitor C 2 is 1 μf.
Optionally, the voltage drop of diode D 2 is greater than or equal to the voltage drop of diode D 1.
Optionally, the resistance of the gate resistor R G is 1Ω.
Based on the circuit, the invention provides a method for suppressing the grid source voltage oscillation of a GaN device with a clamping function, which is characterized in that the grid source voltage oscillation suppression circuit of the GaN device with the clamping function is adopted in a driving circuit of the GaN device to suppress the grid source voltage oscillation.
The invention has the following effects:
(1) The suppression circuit provided by the invention mainly adopts passive elements, so that the design of the driving circuit is very simple.
(2) The oscillation suppression circuit always keeps the gate-source voltage overshoot of the GaN device at a position close to the driving voltage when circuit parameters such as input parameters are changed, which can effectively clamp the gate-source voltage and protect the device from damage.
(3) The circuit and the method provided by the invention have no influence on the switching speed of the device, and can not cause extra switching loss.
(4) The overshoot of the gate-source voltage can be effectively clamped without being affected by the gate resistance, which will allow the gate resistance to be properly reduced in practical applications. Reducing the gate resistance not only increases the switching speed and reduces the switching losses, but also reduces the risk of crosstalk.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below.
FIG. 1 is a schematic circuit diagram of a double pulse circuit;
FIG. 2 is a schematic circuit diagram of a suppression circuit in accordance with an embodiment of the present invention;
FIG. 3 is a schematic diagram illustrating the operation of the suppression circuit at various stages in accordance with an embodiment of the present invention;
FIG. 4 is a schematic diagram of an exemplary waveform of a suppression circuit and a relationship between DeltaV C1 and clamp capacitance C 1 according to an embodiment of the present invention;
FIG. 5 is a waveform comparison chart of the present invention and the conventional method under different input voltages with fixed gate resistance; wherein V in = 10V for fig. 5 (a), V in = 20V for fig. 5 (b), and V in = 30V for fig. 5 (c);
Fig. 6 is a waveform comparison chart of the present invention and a conventional method under the condition of fixed input voltage and different gate resistances, wherein R G = 1 Ω corresponding to fig. 6 (a), R G = 2 Ω corresponding to fig. 6 (b), and R G = 3 Ω corresponding to fig. 6 (c).
Detailed Description
Embodiments of the technical scheme of the present invention will be described in detail below with reference to the accompanying drawings. The following examples are only for more clearly illustrating the technical aspects of the present invention, and thus are merely examples, and are not intended to limit the scope of the present invention.
It is noted that unless otherwise indicated, technical or scientific terms used herein should be given the ordinary meaning as understood by one of ordinary skill in the art to which this application belongs.
As shown in fig. 1, a double pulse circuit is generally used in the prior art to analyze the overshoot of the gate-source voltage, Q 1 is a passive device, and Q 2 is an active device and also a device to be tested. As described above, the maximum gate-source voltage of the GaN device is relatively close to the driving voltage, and the fast switching speed of the GaN device makes the serious overshoot phenomenon more likely to occur. Therefore, the present embodiment provides a GaN device gate-source voltage oscillation suppression circuit with a clamping function, as shown in fig. 2, including a diode D 1, a diode D 2, a clamping capacitor C 1, a decoupling capacitor C 2, a resistor R 1, and a resistor R 2, wherein an anode terminal of the diode D 1 is connected to a gate of the GaN device, and a cathode terminal of the diode D 1 is connected to a source of the GaN device through the clamping capacitor C 1; the resistor R 1 is connected with the clamping capacitor C 1 in parallel, the anode end of the diode D 2 is connected to the driving power supply, the cathode end of the diode D 2 is grounded through the decoupling capacitor C 2, and the cathode end of the diode D 2 is also connected with the clamping capacitor C 1 through the resistor R 2, so that the driving power supply charges the clamping capacitor C 1 after passing through the diode D 2 and the resistor R 2.
In specific implementation, the driving power supply is connected with a driving chip, and a driving signal output by the driving chip is loaded onto the grid electrode of the GaN device after passing through the grid electrode resistor R G and the grid electrode inductor L G.
It can be seen that the circuit provided by the present embodiment is a gate driver with high efficiency and compact structure, mainly using passive components and not requiring additional control, which makes the design of the driver very simple and can be used in other bridge circuits.
The working principle of the circuit is analyzed as follows:
Before the drive signal comes, the drive voltage V G charges the clamp capacitor C 1 through the diode D 2 and the resistor R 2. Since the driving voltage V G of the GaN device is 5V, the diode drop is not negligible.
As can be seen in connection with fig. 3, the circuit operating state mainly comprises four phases, and a typical waveform is shown in fig. 4,
(1) Opening process
Stage 1[t 0-t1 ], as shown in fig. 3 (a): the driving voltage V G charges the clamp capacitor C 1 through the diode D 2 and the resistor R 2. To prevent clamp capacitance C 1 from affecting the turn-on process of the device, the cathode of diode D 1 is connected in series with clamp capacitance C 1. The resistor R 1 connected in parallel with the clamp capacitor C 1 is larger and much larger than R 2, so the voltage of C 1 is approximately equal to the difference between the driving voltage V G and the step-down value V D2 of the diode D 2, which is:
During this period, there is no driving signal, and the gate-source voltage v gs of the device Q 2 is 0, so the cathode voltage of the diode D 1 is higher than the anode voltage, and the diode is reverse-blocked. When the resistor R 1 is not added, the voltage V C1 of the clamp capacitor is equal to the driving voltage V G. At this time, the gate-source voltage V gs of device Q 2 is clamped approximately at the sum of V C1 and the voltage drop V D1 of diode D 1. If the voltage drop V D1 of the diode is large at this time, there is still a risk that V gs exceeds 6V, and the clamp circuit does not have a good protection effect. Therefore, R1 needs to be added and its size is much larger than R2.
Stage 2[t 1-t2 ], as shown in fig. 3 (b): when the drive signal comes, the gate-source voltage v gs of the device Q 2 starts rising. At this point, the voltage of C 1 has reached V G-VD2, and the cathode voltage of diode D 1 is still higher than the anode voltage. Thus, diode D 1 is still reverse blocking until the gate-source voltage V gs reaches the sum of V C1 and the voltage drop V D1 of diode D 1, i.e., V gs is approximately equal to V G-VD2+VD1. Since D 1 and D 2 are generally chosen to be of the same type, meaning that V D1 is equal to V D2, where V gs is approximately equal to V G, it is also possible to choose a pressure drop of D 2 that is slightly greater than that of D 1.
Stage 3[t 2-t3 ], as shown in fig. 3 (c): when the gate-source voltage V gs of device Q 2 reaches the drive voltage V G, V gs will oscillate and exceed V G due to resonance between the gate inductance and gate-source capacitance of Q 2. At this time, the diode D 1 is turned on in the forward direction. C 1 begins to clamp the voltage difference between V gs,vgs and V G to charge capacitor C 1, which results in significant suppression of the overshoot of V gs. When the overshoot of v gs charges C 1, a clamp current i C1 will be generated, which will reduce the gate current through Q 2. The larger C 1 is, the more gate current flows into C 1, and the better the oscillation suppression effect is.
Stage 4[t 3-t4 ], as shown in fig. 3 (d): after the device is fully turned on, the gate-source voltage V gs of the device drops to V G and diode D 1 is reverse blocked. The overshoot energy stored in C 1 will be fed back through resistor R 2 into decoupling capacitor C 2, which will not affect the switching transient of device Q 2. At this point, V C1 continues to drop from maximum, eventually returning again to V G-VD2.
(2) Shut-down procedure
When the device turns off, the gate-source voltage V gs begins to drop, which will be lower than the drive voltage V G. The sum of the voltage of capacitor C 1 and the voltage of diode D 1 is approximately equal to V G. Thus, diode D 1 is reverse blocked and the clamp circuit does not affect the turn-off process of the device.
In specific implementation, the parameter design process of the circuit is as follows:
(1) Parameter design of capacitors C 1 and C 2
When v gs overshoot occurs, capacitor C 1 will absorb energy, the magnitude of which determines the maximum voltage of v C1 during turn-on. DeltaV C1 represents the difference between the maximum voltage of C 1 and V G-VD2, which determines the voltage value at which V gs is ultimately clamped, as shown in FIG. 4 (a). Fig. 4 (b) shows the relationship between Δv C1 and the capacitance C 1, which is established based on the simulation results. It can be seen that the larger C 1, the smaller DeltaV C1. In order to keep the clamped gate-source voltage V gs close to the drive voltage, the maximum av C1 is chosen not to exceed 0.3V, so according to fig. 4 (b), C 1 should be greater than 20nF. Furthermore, according to fig. 3 (d), the energy stored in C 1 needs to be completely released through R 2 in one switching cycle. The larger the C 1, the longer the RC discharge time. Thus C 1 was finally chosen to be 47nF.
The capacitor C 2 mainly plays a decoupling role and can be approximated as a voltage source V G-VD2. Therefore, the value is relatively large, here 1. Mu.F.
(2) Parameter design of resistors R 1 and R 2
The larger R 2, the larger the RC time constant τ, which will not ensure that the energy stored in C 1 is completely released within one switching cycle. In order to achieve a complete release of the overshoot energy stored in C 1, typically 3-5 times τ is required. Here we choose a time constant of 5 times.
t1＝5×C1×R2 (2)
Setting the release time t 1 <2 μs we can obtain R 2 <8.5 Ω. Accordingly, the value of R 2 is finally set to 2Ω.
As described above, the resistor R 1 is relatively large so as not to affect the clamp function of C 1. When resistor R 1 is small, capacitor C 1 will be shorted. In addition, R 1 should be much larger than R 2. When R 2 is too large or comparable to R 1, the voltage of R 2 cannot be ignored. At this time, the voltage of R 1 cannot be approximately equal to V G-VD2. Here we choose the value of R 1 to be 2kΩ.
(3) Parameter design of diodes D 1 and D 2
Diode D 1 acts to block C 1 during the on and off process of the device, so C 1 will not affect the on and off process of the device. When v gs overshoot occurs, D 1 turns on to clamp the overshoot of v gs. As previously mentioned, the voltage drop of the diode cannot be neglected. Diodes D 1 and D 2 are therefore selected to be of the same element type in order to clamp v gs around the drive voltage, where the voltage drop of D 2 can also be selected to be slightly larger than the voltage drop of D 1.
The remarkable effect of the invention is further verified by constructing a specific experimental platform. The experimentally selected switching device was EPC2015C, the driver was LM5114, and diodes D 1 and D 2 were ultrafast recovery diodes RF202LAM2S manufactured by ROHM company. The input voltage V in V, the inductor current I L 5A, and the driving voltage V G 5V. For accurate measurement of the switching current, a coaxial shunt (SSDN-10) produced by T & M RESEARCH Products inc. With a bandwidth of 2GHz was used.
Fig. 5 shows an experimental waveform comparison of the oscillation suppression circuit with the normal driving method when the load current I L is 5A and the gate resistance R G is 1Ω. It can be seen that the present invention has a good clamping effect on the oscillations of the gate-source voltage V gs, V gs being clamped at a position of about 5.3V. When the input voltage V in is varied, the method still has a good oscillation suppression effect, which proves the effectiveness of the invention. In addition, it can also be seen from fig. 5 that the present invention does not affect the switching speed of the device and thus does not increase the switching loss of the device.
Fig. 6 shows experimental waveforms of the present invention compared with a general driving method when the load current I L is 5A and the input voltage V in is 30V. It can be seen that the smaller the gate resistance, the greater the oscillation overshoot of v gs. As shown in fig. 6 (a), when the gate resistance is 1Ω, the voltage overshoot of V gs is about 6V, the maximum rated gate voltage. After the circuit provided by the invention is adopted, V gs can be effectively clamped at 5.3V. And, when the gate resistance changes, the invention can still clamp the overshoot voltage effectively without slowing down the switching speed. Accordingly, experimental results effectively support our theoretical design.
In addition, the embodiment also provides a method for suppressing the gate-source voltage oscillation of the GaN device with the clamping function, wherein the gate-source voltage oscillation suppression circuit of the GaN device with the clamping function is adopted in the driving circuit of the GaN device to suppress the gate-source voltage oscillation.
In practical applications, in order to suppress the gate-source voltage overshoot, a method of increasing the gate resistance is generally employed. Although this approach can suppress gate-source voltage overshoot to some extent, it will slow down the switching speed and increase the risk of switching losses and crosstalk. The proposed oscillation suppression method effectively clamps the gate-source voltage when the gate resistance changes. Therefore, in practical application, by adopting the method provided by the invention, the grid resistance can be properly reduced, so that the switching speed can be increased, the switching loss can be reduced, and the crosstalk can be restrained to a certain extent. In addition, in this method, R 1 is relatively large and the current of the gate clamp is relatively small. Therefore, the method has negligible effect on the drive loss.
Finally, it should be noted that the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention and are intended to be within the scope of the appended claims and description.

Claims (9)

1. The GaN device gate-source voltage oscillation suppression circuit with the clamping function is characterized by comprising a diode D 1, a diode D 2, a clamping capacitor C 1, a decoupling capacitor C 2, a resistor R 1 and a resistor R 2, wherein the anode end of the diode D 1 is connected to the gate of the GaN device, and the cathode end of the diode D 1 is connected to the source of the GaN device through the clamping capacitor C 1; the resistor R 1 is connected with the clamping capacitor C 1 in parallel, the anode end of the diode D 2 is connected to a driving power supply, the cathode end of the diode D 2 is grounded through the decoupling capacitor C 2, and the cathode end of the diode D 2 is also connected with the clamping capacitor C 1 through the resistor R 2, so that the driving power supply charges the clamping capacitor C 1 after passing through the diode D 2 and the resistor R 2;
The resistance of the resistor R 1 is larger than that of the resistor R 2.
2. The GaN device gate-source voltage oscillation suppression circuit with clamping function according to claim 1, wherein the driving power supply is connected with a driving chip, and the driving signal output by the driving chip is loaded onto the gate of the GaN device through a gate resistor R G and a gate inductor L G.
3. The GaN device gate-source voltage oscillation suppression circuit with clamping function according to claim 2, wherein if a difference between a maximum voltage of the clamping capacitor C 1 and V G-VD2 is Δv C1, a magnitude of Δv C1 is set according to a relationship between Δv C1 and a capacitance of the clamping capacitor C 1, where V G is a driving voltage outputted by the driving power supply, and V D2 is a step-down value of the diode D 2.
4. The GaN device gate-source voltage oscillation suppression circuit with clamping function according to claim 2 or 3, wherein the driving chip adopts LM5114, and the driving voltage of the driving power supply is 5V.
5. The GaN device gate-source voltage oscillation suppression circuit with clamping function according to claim 1 or 3, wherein a capacitance value of said clamping capacitor C 1 is >20nF.
6. The GaN device gate-source voltage oscillation suppression circuit with clamping function according to claim 1 or 3, wherein the capacitance of the clamping capacitor C 1 is 47nF, the resistance of the resistor R 1 is 2kΩ, the resistance of the resistor R 2 is 2 Ω, and the capacitance of the decoupling capacitor C 2 is 1 μf.
7. The GaN device gate-source voltage oscillation suppression circuit with clamping function of claim 1, wherein a voltage drop of diode D 2 is greater than or equal to a voltage drop of diode D 1.
8. The GaN device gate-source voltage oscillation suppression circuit with clamping function according to claim 2, wherein the gate resistor R G has a resistance value of 1Ω.
9. A method for suppressing gate-source voltage oscillation of a GaN device having a clamping function, characterized in that the gate-source voltage oscillation suppression circuit of a GaN device having a clamping function as claimed in any one of claims 1 to 8 is employed in a driving circuit of the GaN device.
CN202211200446.XA 2022-09-29 2022-09-29 GaN device gate-source voltage oscillation suppression circuit with clamping function and method Active CN115395768B (en)

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GB2564482B (en) * 2017-07-14 2021-02-10 Cambridge Entpr Ltd A power semiconductor device with a double gate structure
CN111257719A (en) * 2020-03-05 2020-06-09 香港科技大学深圳研究院 Active MOSFET voltage clamping circuit, clamping method and double-pulse test circuit
CN113315354A (en) * 2021-06-24 2021-08-27 南通大学 Low-impedance clamping drive circuit for inhibiting crosstalk of SiC MOSFET (Metal-oxide-semiconductor field Effect transistor)
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"A Suppression Method for Gate-Source Voltage Oscillation With Clamping Function for GaN Devices";Jian Chen等;《IEEE Transactions on Power Electronics》;20221010;全文 *

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