CN115394855A - PMOS device structure with germanium-silicon source drain region and manufacturing method thereof - Google Patents

PMOS device structure with germanium-silicon source drain region and manufacturing method thereof Download PDF

Info

Publication number
CN115394855A
CN115394855A CN202211042108.8A CN202211042108A CN115394855A CN 115394855 A CN115394855 A CN 115394855A CN 202211042108 A CN202211042108 A CN 202211042108A CN 115394855 A CN115394855 A CN 115394855A
Authority
CN
China
Prior art keywords
germanium
silicon
sige
layer
precursor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202211042108.8A
Other languages
Chinese (zh)
Inventor
张强
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai IC R&D Center Co Ltd
Shanghai IC Equipment Material Industry Innovation Center Co Ltd
Original Assignee
Shanghai IC R&D Center Co Ltd
Shanghai IC Equipment Material Industry Innovation Center Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai IC R&D Center Co Ltd, Shanghai IC Equipment Material Industry Innovation Center Co Ltd filed Critical Shanghai IC R&D Center Co Ltd
Priority to CN202211042108.8A priority Critical patent/CN115394855A/en
Publication of CN115394855A publication Critical patent/CN115394855A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures

Abstract

The invention discloses a PMOS device structure with a germanium-silicon source drain region and a manufacturing method thereof.A germanium-silicon cap layer is additionally arranged between a germanium-silicon main body layer and the silicon cap layer, and the germanium concentration in the germanium-silicon cap layer is in a descending state from bottom to top by adjusting the flow rate of a germanium precursor and the flow rate proportion of each reaction gas in first germanium-silicon epitaxial reaction gas, so that a germanium-silicon buffer layer with gradually reduced concentration is formed between the germanium-silicon main body layer and the silicon cap layer, the probability of lattice mismatch of a germanium-silicon intrinsic layer and the silicon cap layer at an interface can be obviously reduced, and the problem of relaxation defects can be effectively solved; in addition, in the gradient temperature rise stage before the silicon cap layer is formed, the second germanium-silicon epitaxial reaction gas without a germanium precursor is adopted to activate the surface of the silicon-germanium cap layer, so that the surface of the silicon-germanium crystal is always in an active state of heat absorption and heat release, and the risk of relaxation on the surface of the crystal can be greatly reduced.

Description

PMOS device structure with germanium-silicon source drain region and manufacturing method thereof
Technical Field
The invention relates to the technical field of semiconductor integrated circuit processes, in particular to a PMOS device structure with a germanium-silicon source drain region and a manufacturing method thereof.
Background
As the scaling of the ultra-large scale integrated circuit continues to progress, the size of the circuit device is smaller and the operation speed is faster, and how to improve the driving current of the circuit device becomes more and more important.
An embedded silicon germanium (eSiGe) technology is a strained silicon technology for improving the performance of a PMOS transistor device, and a silicon germanium (SiGe) stress layer is formed in a selective epitaxial manner in a source-drain region of the PMOS transistor, so that the mobility of a channel hole can be improved, and the current driving capability of the PMOS transistor is improved.
Referring to fig. 1, a conventional PMOS device structure with sige source and drain regions is shown. The structure of the current PMOS SiGe epitaxial film is roughly divided into a SiGe Seed layer (SiGe Seed) 15, a SiGe Bulk layer (SiGe Bulk) 14, and a Si Cap layer (Si Cap) 13 formed in the source-drain trench 11 from bottom to top. The manufacturing process generally comprises the following steps:
(1) Forming a source-drain trench 11 on the substrate 10 at two sides of the gate 12, and then growing a germanium-silicon seed crystal layer 15 containing low germanium concentration in the source-drain trench 11 to improve relaxation (relax) defects;
(2) Continuing to grow a sige body layer 14 containing a higher concentration of ge on the sige seed layer 15 to provide strain;
(3) Carrying out gradient temperature rise in a hydrogen atmosphere;
(4) The growth of the silicon cap layer 13 (for forming the NiSi metal suicide layer) continues on the silicon germanium body layer 14.
However, due to the high concentration of germanium in the silicon germanium bulk layer 14, the high concentration of silicon germanium bulk layer 14 and silicon cap layer 13 are lattice mismatched at the interface, and thus are prone to relaxation defects. Meanwhile, since the temperature rise process in the gradient temperature rise stage before the growth of the silicon cap layer 13 usually takes 6 to 10 minutes, and the reaction is stopped during the temperature rise process, the longer waiting time is also easy to cause a relaxation risk on the surface of the unreacted silicon germanium crystal.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provides a PMOS device structure with a germanium-silicon source drain region and a manufacturing method thereof.
In order to achieve the purpose, the technical scheme of the invention is as follows:
the invention provides a PMOS device structure with a germanium-silicon source drain region, which comprises:
a substrate;
the gate is arranged on the substrate, and the source drain regions are positioned on two sides of the gate;
the source drain region comprises a germanium-silicon seed crystal layer, a germanium-silicon main body layer, a germanium-silicon cap layer and a silicon cap layer which are formed from bottom to top;
the germanium-silicon capping layer has a surface treated by germanium-silicon epitaxial reaction gas without a germanium precursor in a gradient temperature rise process.
Furthermore, the source-drain region is provided with a source-drain groove, the germanium-silicon seed layer, the germanium-silicon main body layer, the germanium-silicon cap layer and the silicon cap layer are formed in the source-drain groove from bottom to top, and the surface of the germanium-silicon main body layer is exposed from the source-drain groove and is higher than the surface of the substrate.
Further, the germanium concentration in the germanium-silicon capping layer decreases from bottom to top.
Further, the germanium concentration in the germanium-silicon main body layer increases from bottom to top, and the germanium concentration in the germanium-silicon capping layer decreases from bottom to top to 5% -10% consistent with the germanium concentration in the surface of the germanium-silicon main body layer.
The invention also provides a manufacturing method of the PMOS device structure with the germanium-silicon source drain region, which comprises the following steps:
providing a substrate;
forming a grid on the substrate, and forming source-drain grooves on the surface of the substrate on two sides of the grid;
forming a germanium-silicon seed crystal layer, a germanium-silicon main body layer and a germanium-silicon cap layer from bottom to top in the source-drain groove by epitaxial growth by adopting a first germanium-silicon epitaxial reaction gas containing a silicon precursor, a germanium precursor and an etching gas;
executing a gradient temperature rise process, and simultaneously processing the surface of the germanium-silicon cap layer by adopting a second germanium-silicon epitaxial reaction gas without a germanium precursor;
and forming a silicon capping layer on the surface of the processed germanium-silicon capping layer.
Further, when the germanium-silicon cap layer is formed, the concentration of germanium in the formed germanium-silicon cap layer is decreased progressively from bottom to top by adopting a method of gradually reducing the flow of a germanium precursor in the first germanium-silicon epitaxial reaction gas.
Further, the flow rate of the germanium precursor in the first germanium-silicon epitaxial reaction gas is gradually reduced to 1/10 of the initial value.
Further, when the germanium-silicon cap layer is formed, the flow ratio among the silicon precursor, the germanium precursor and the etching gas satisfies:
silicon precursor from the beginning of the process: germanium precursor: etching gas ≡ 1:8:2.5 starting ratio, linearly graded by flow size to silicon precursor at the end of the process: germanium precursor: etching gas ≡ 2:1: 2.
Further, when the surface of the germanium-silicon cap layer is processed, the flow ratio between the silicon precursor and the etching gas satisfies the following conditions:
silicon precursor: etching gas ≡ 1:1.
further, the flow rates of the silicon precursor and the etching gas are gradually reduced to half of the initial values.
Further, the silicon precursor comprises dichlorosilane, the germanium precursor comprises germane, and the etching gas comprises HCl.
According to the technical scheme, the germanium-silicon cap layer is additionally arranged between the germanium-silicon main body layer and the silicon cap layer, the germanium concentration in the germanium-silicon cap layer is in a decreasing state from bottom to top by adjusting the flow rate of the germanium precursor and the flow rate proportion of each reaction gas in the first germanium-silicon epitaxial reaction gas, so that a germanium-silicon buffer layer with gradually decreased concentration is formed between the germanium-silicon main body layer and the silicon cap layer, the probability of lattice mismatch of the germanium-silicon intrinsic layer and the silicon cap layer at an interface can be obviously reduced, and the problem of relaxation defects can be effectively solved. In addition, in the gradient temperature rise stage before the silicon cap layer is formed, the second germanium-silicon epitaxial reaction gas without a germanium precursor is adopted to activate the surface of the silicon-germanium cap layer, so that the surface of the silicon-germanium crystal is always in an active state of heat absorption and heat release, and the risk of relaxation on the surface of the crystal can be greatly reduced.
Drawings
FIG. 1 is a schematic structural diagram of a conventional PMOS device having SiGe source/drain regions;
FIG. 2 is a schematic structural diagram of a PMOS device with SiGe source/drain regions according to a preferred embodiment of the present invention;
fig. 3 is a flowchart of a method for manufacturing a PMOS device structure having sige source and drain regions according to a preferred embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below, and it is obvious that the described embodiments are a part of the embodiments of the present invention, but not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without inventive step based on the embodiments of the present invention, are within the scope of protection of the present invention. Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. As used herein, the word "comprising" and similar words are intended to mean that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items.
The following provides a more detailed description of embodiments of the present invention, with reference to the accompanying drawings.
Referring to fig. 2, fig. 2 is a schematic structural diagram of a PMOS device having sige source/drain regions according to a preferred embodiment of the present invention. As shown in fig. 2, a PMOS device structure with sige source drain regions according to the present invention includes: the semiconductor device comprises a substrate 100, a gate 102 arranged on the substrate 100 and source and drain regions positioned at two sides of the gate 102.
Wherein, a germanium-silicon Seed layer (SiGe Seed) 106, a germanium-silicon body layer (SiGe Bulk) 105, a germanium-silicon Cap layer (SiGe Cap) 104 and a silicon Cap layer (Si Cap) 103 are formed in the source/drain region from bottom to top. Moreover, the germanium concentration in the sige capping layer 104 decreases from bottom to top, and the sige capping layer 104 has an upper surface treated by a sige epitaxial reaction gas (second sige epitaxial reaction gas) containing no ge precursor in the gradient temperature increasing process.
Please refer to fig. 2. In a preferred embodiment, the substrate 100 may be a conventional semiconductor substrate 100, such as a silicon material substrate 100 formed of single crystal silicon, polysilicon, amorphous silicon, or the like, or a silicon-on-insulator (SOI) substrate 100, or the like. The substrate 100 may also be a substrate 100 that uses other semiconductor materials or other structures.
The gate 102 may employ a conventional gate 102 structure, such as a metal gate structure with sidewalls. The invention is not limited.
In a preferred embodiment, the source and drain regions may be provided with source and drain trenches 101; a silicon germanium seed layer 106, a silicon germanium body layer 105, a silicon germanium cap layer 104 and a silicon cap layer 103 are formed in the source drain trench 101 from bottom to top.
In a preferred embodiment, the upper surface of the sige body layer 105 is exposed from the source/drain trench 101 and is higher than the upper surface of the substrate 100.
In a preferred embodiment, the germanium concentration in sige body layer 105 increases from bottom to top; the germanium concentration in the sige capping layer 104 decreases from bottom to top and from a lower surface state consistent with the germanium concentration in the upper surface of the sige body layer 105 to an upper surface state in which the germanium concentration is 5% to 10%.
In a preferred embodiment, the germanium concentration in sige body layer 105 may increase from 30% to 40% from bottom to top; the germanium concentration in the germanium-silicon capping layer 104 can be decreased from 40% to 5% -10% from bottom to top.
In a preferred embodiment, the thickness of the sige capping layer 104 may be about 15 to 35 angstroms.
The following describes in detail a method for fabricating a PMOS device structure having a sige source/drain region according to the present invention with reference to the accompanying drawings.
Please refer to fig. 3 in conjunction with fig. 2. The method for manufacturing the PMOS device structure with the germanium-silicon source drain region can be used for manufacturing the PMOS device structure with the germanium-silicon source drain region shown in figure 2, and can comprise the following steps:
step S1: a substrate 100 is provided.
In a preferred embodiment, the substrate 100 may be, for example, a silicon substrate 100.
Step S2: a gate electrode 102 is formed on a substrate 100, and source-drain trenches 101 are formed on the surface of the substrate 100 on both sides of the gate electrode 102.
In a preferred embodiment, the gate 102 structure may be formed on the silicon substrate 100 by a conventional gate process.
Conventional photolithography and etching processes may then be used to form source and drain trenches 101 in the surface of the silicon substrate 100 on both sides of the gate 102.
And step S3: a first sige epitaxy reaction gas containing a si precursor, a ge precursor and an etching gas is used to form a sige seed layer 106, a sige body layer 105 and a sige capping layer 104 from bottom to top through epitaxial growth in the source/drain trench 101, and the ge concentration in the sige capping layer 104 is decreased from bottom to top.
In a preferred embodiment, the silicon precursor in the first SiGe epitaxy reaction gas may comprise Dichlorosilane (DCS), etc., and the germanium precursor may comprise germane (GeH) 4 ) Etc., the etching gas may include HCl, etc.
In the source-drain trench 101, a first sige epitaxial reaction gas may be introduced first, and a conventional sige seed layer 106 with a low ge concentration is formed on the inner wall of the source-drain trench 101 by epitaxial growth.
Then, the first sige epitaxial reaction gas may be continuously introduced to further grow sige body layer 105 on the formed sige seed layer 106.
In a preferred embodiment, during the formation of sige body layer 105, a method of gradually increasing the germane flow in the first sige epitaxial reaction gas may be employed to form sige body layer 105 with an increasing ge concentration from bottom to top. For example, the germanium concentration in the sige body layer 105 formed may be increased from 30% to 40% from bottom to top by gradually increasing the germane flow in the first sige epitaxial reaction gas.
Then, the first sige epitaxial reaction gas may be continuously introduced to further grow the sige capping layer 104 on the formed sige body layer 105.
In a preferred embodiment, during the formation of the sige capping layer 104, a method of gradually decreasing the germane flow in the first sige epitaxial reaction gas may be adopted to make the ge concentration in the formed sige capping layer 104 decrease from bottom to top.
In a preferred embodiment, during the formation of the sige capping layer 104, a method of gradually reducing the germane flow in the first sige epitaxial reaction gas may be adopted to decrease the ge concentration in the formed sige capping layer 104 from the same level as the ge concentration in the upper surface of the sige body layer 105 to a level of 5% -10% ge concentration from bottom to top.
In a preferred embodiment, the process temperature used in forming the sige cap layer 104 may be the same as that used in forming the sige body layer 105. And the first germanium-silicon epitaxial reaction gas can adopt a setting mode of linear gradual change according to the flow rate. For example, at the beginning of the process, the initial ratio for the first sige epitaxial reaction gas may be set as:
DCS：GeH 4 ：HCl≌1：8：2.5；
at the end of the process, the termination ratio of the first sige epitaxy reaction gas may be set as:
DCS：GeH 4 ：HCl≌2：1：2。
wherein, when DCS and GeH 4 When the flow ratio between HCl and HCl is taken to be approximately equal to the above ratio, the fluctuation range of each ratio may be plus or minus 10%.
In a preferred embodiment, the flow rate of germane in the first sige epitaxial reaction gas is gradually decreased to 1/10 of the initial value when the sige cap layer 104 is formed and the process is finished.
The thickness of the formed silicon germanium cap layer 104 can be about 15-35 angstroms, and the germanium concentration in the silicon germanium cap layer 104 is gradually reduced from about 5% -10% consistent with the silicon germanium body layer 105, and can be used as a buffer layer between the silicon germanium body layer 105 and the silicon cap layer 103.
And step S4: and executing a gradient temperature rise process, and simultaneously processing the surface of the silicon germanium cap layer 104 by adopting a second silicon germanium epitaxial reaction gas without a germanium precursor.
In a preferred embodiment, a gradient temperature rise process (Ramp up) is performed to gradually raise the temperature to the process temperature of the silicon cap layer 103, and during this process, the introduction of germane is stopped, and DCS and HCl introduced into the first sige epitaxial reaction gas are maintained, so as to form the introduction state of the second sige epitaxial reaction gas without germane.
In a preferred embodiment, DCS and HCl gases are continuously introduced. And the second germanium-silicon epitaxial reaction gas can adopt a setting mode of linear gradual change according to the flow rate.
Care should be taken to control the gas ratio when performing the activation process on the surface of the sige cap layer 104. For example, the initial set ratio of the second sige epitaxial reaction gas may be set as:
DCS:HCl≌1：1；
when the treatment is finished, the flow setting of the second germanium-silicon epitaxial reaction gas can be halved from the initial value, and the proportion can be set as follows:
DCS:HCl≌1：1。
wherein, when the flow ratio between DCS and HCl is about equal to the above ratio, the fluctuation range of each ratio can be plus or minus 10%.
This process step does not require a growth film, but can keep the crystalline surface of the sige capping layer 104 in an active state of heat absorption and heat release at all times, so that the risk of relaxation can be greatly reduced.
Step S5: a silicon cap layer 103 is formed on the surface of the processed silicon germanium cap layer 104.
Thereafter, a conventional epitaxial process may be used to further form the silicon cap layer 103 on the surface of the processed sige silicon cap layer 104.
In summary, in the present invention, the sige cap layer 104 is additionally disposed between the sige main body layer 105 and the silicon cap layer 103, and the germanium concentration in the sige cap layer 104 is in a decreasing state from bottom to top by adjusting the flow rate of the germanium precursor and the flow rate ratio of each reaction gas in the first sige epitaxial reaction gas, so that the sige buffer layer with gradually decreasing concentration is formed between the sige main body layer 105 and the silicon cap layer 103, which can significantly reduce the probability of lattice mismatch between the sige intrinsic layer and the silicon cap layer 103 at the interface, and thus can effectively solve the problem of relaxation defect. In addition, in the invention, in the gradient temperature rise stage before the silicon capping layer 103 is formed, the second germanium-silicon epitaxial reaction gas without a germanium precursor is adopted to activate the surface of the germanium-silicon capping layer 104, so that the surface of the germanium-silicon crystal is always in an active state of heat absorption and heat release, and the risk of generating relaxation on the surface of the crystal can be greatly reduced.
Although the embodiments of the present invention have been described in detail hereinabove, it is apparent to those skilled in the art that various modifications and variations can be made to the embodiments. However, it is to be understood that such modifications and variations fall within the scope and spirit of the present invention as set forth in the appended claims. Moreover, the invention as described herein is capable of other embodiments and of being practiced or of being carried out in various ways.

Claims (10)

1. A PMOS device structure with germanium-silicon source drain regions is characterized by comprising:
a substrate;
the gate is arranged on the substrate, and the source drain regions are positioned on two sides of the gate;
the source drain region comprises a germanium-silicon seed crystal layer, a germanium-silicon main body layer, a germanium-silicon cap layer and a silicon cap layer which are formed from bottom to top;
the germanium-silicon capping layer has a surface treated by germanium-silicon epitaxial reaction gas without a germanium precursor in a gradient temperature rise process.
2. The PMOS device structure with the SiGe source-drain region as claimed in claim 1, wherein the source-drain region is provided with a source-drain trench, the SiGe seed layer, the SiGe bulk layer, the SiGe capping layer and the Si capping layer are formed in the source-drain trench from bottom to top, and the surface of the SiGe bulk layer is exposed from the source-drain trench and is higher than the surface of the substrate.
3. The PMOS device structure with SiGe source/drain regions as claimed in claim 1 wherein the Ge concentration in the SiGe capping layer decreases from bottom to top; and/or the concentration of germanium in the germanium-silicon main body layer is increased progressively from bottom to top, and the concentration of germanium in the germanium-silicon capping layer is decreased progressively from bottom to top to 5% -10% consistent with the concentration of germanium in the surface of the germanium-silicon main body layer.
4. A method for manufacturing a PMOS device structure with a germanium-silicon source drain region is characterized by comprising the following steps:
providing a substrate;
forming a grid on the substrate, and forming source-drain grooves on the surface of the substrate on two sides of the grid;
forming a germanium-silicon seed crystal layer, a germanium-silicon main body layer and a germanium-silicon cap layer from bottom to top in the source-drain groove by epitaxial growth by adopting a first germanium-silicon epitaxial reaction gas containing a silicon precursor, a germanium precursor and an etching gas;
executing a gradient temperature rise process, and simultaneously processing the surface of the germanium-silicon cap layer by adopting a second germanium-silicon epitaxial reaction gas without a germanium precursor;
and forming a silicon capping layer on the surface of the processed germanium-silicon capping layer.
5. The method for manufacturing a PMOS device structure having sige source drain regions as claimed in claim 4, wherein when forming said sige cap layer, a method of gradually decreasing the flow rate of a ge precursor in said first sige epitaxial reaction gas is employed to decrease the ge concentration in said sige cap layer from bottom to top.
6. The method for manufacturing a PMOS device structure having sige source drain regions as claimed in claim 5, wherein the flow rate of the ge precursor in the first sige epitaxial reaction gas is gradually reduced to 1/10 of the initial value.
7. The method for manufacturing a PMOS device structure having sige source drain regions according to claim 5, wherein a flow ratio among the si precursor, the ge precursor and the etching gas satisfies:
silicon precursor from the beginning of the process: germanium precursor: etching gas ≡ 1:8:2.5 starting ratio, linearly graded by flow size to silicon precursor at the end of the process: germanium precursor: etching gas ≡ 2:1: 2.
8. The method for manufacturing the PMOS device structure with the SiGe source/drain region as claimed in claim 4, wherein when the surface of the SiGe cap layer is processed, the flow ratio between the Si precursor and the etching gas satisfies:
silicon precursor: etching gas ≡ 1:1.
9. the method of claim 8, wherein the flow rates of the silicon precursor and the etching gas are gradually reduced to half of the initial value.
10. The method of claim 4, wherein the silicon precursor comprises dichlorosilane, the germanium precursor comprises germane, and the etching gas comprises HCl.
CN202211042108.8A 2022-08-29 2022-08-29 PMOS device structure with germanium-silicon source drain region and manufacturing method thereof Pending CN115394855A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202211042108.8A CN115394855A (en) 2022-08-29 2022-08-29 PMOS device structure with germanium-silicon source drain region and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202211042108.8A CN115394855A (en) 2022-08-29 2022-08-29 PMOS device structure with germanium-silicon source drain region and manufacturing method thereof

Publications (1)

Publication Number Publication Date
CN115394855A true CN115394855A (en) 2022-11-25

Family

ID=84121709

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202211042108.8A Pending CN115394855A (en) 2022-08-29 2022-08-29 PMOS device structure with germanium-silicon source drain region and manufacturing method thereof

Country Status (1)

Country Link
CN (1) CN115394855A (en)

Similar Documents

Publication Publication Date Title
US8450775B2 (en) Method to control source/drain stressor profiles for stress engineering
US7405142B2 (en) Semiconductor substrate and field-effect transistor, and manufacturing method for same
US10529857B2 (en) SiGe source/drain structure
US10658175B2 (en) Semiconductor device and manufacturing method therefor
KR100647457B1 (en) A semiconductor device and a method for manufacturing the same
CN1732556A (en) Method of forming a thick strained silicon layer and semiconductor structures incorporating a thick strained silicon layer
CN116013962B (en) Method for manufacturing semiconductor device
JP4207548B2 (en) Semiconductor substrate manufacturing method, field effect transistor manufacturing method, semiconductor substrate, and field effect transistor
CN103943508A (en) Method for manufacturing PMOS device
JP3488914B2 (en) Semiconductor device manufacturing method
CN103000499B (en) A kind of germanium silicon boron outer layer growth method
US20030077882A1 (en) Method of forming strained-silicon wafer for mobility-enhanced MOSFET device
CN115394855A (en) PMOS device structure with germanium-silicon source drain region and manufacturing method thereof
US11646196B2 (en) Method for germanium enrichment around the channel of a transistor
US11121254B2 (en) Transistor with strained superlattice as source/drain region
US8587026B2 (en) Semiconductor device and manufacturing method thereof
JP2002359189A (en) SEMICONDUCTOR SUBSTRATE AND FIELD EFFECT TRANSISTOR, METHOD FOR FORMING SiGe LAYER, METHOD FOR FORMING STRAINED Si LAYER USING IT AND METHOD FOR MANUFACTURING FIELD EFFECT TRANSISTOR
US20060088966A1 (en) Semiconductor device having a smooth EPI layer and a method for its manufacture
JP3714230B2 (en) Semiconductor substrate, field effect transistor, and manufacturing method thereof
US20170213897A1 (en) Method of fabricating pmos devices with embedded sige
JP4345249B2 (en) Semiconductor substrate, field effect transistor, and manufacturing method thereof
TWI520225B (en) Method of fabricating a semiconductor structure
JPH04283935A (en) Manufacture of semiconductor device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination