CN115379147B

CN115379147B - Signal readout circuit, method and system, pixel unit array circuit and equipment

Info

Publication number: CN115379147B
Application number: CN202211301756.0A
Authority: CN
Inventors: 韩润泽
Original assignee: Pulse Vision Beijing Technology Co ltd
Current assignee: Pulse Vision Beijing Technology Co ltd
Priority date: 2022-09-14
Filing date: 2022-10-24
Publication date: 2023-02-03
Anticipated expiration: 2042-10-24
Also published as: CN115379147A

Abstract

A signal readout circuit, a method and a system, a pixel unit array circuit and a device are disclosed, which belong to the technical field of image communication. In the signal readout circuit, a readout row selector is used for gating a row of pixel cells in a pixel array; a reset row selector for gating the first reset switches of the pixel units in the row; each pixel unit of the row in the pixel sub-array included in the pixel array converts the optical signal into an electric signal and outputs the electric signal to the pixel sub-array read-out feedback unit connected with the pixel sub-array; the first pixel unit which receives the row reset signal and the reset signal gates a second reset switch of the first pixel unit to carry out reset operation; the pixel sub-array reading feedback unit is connected with the pixel units in the pixel sub-array, generates the reset signal when the condition of signal generation is judged to be met according to the electric signal, sends the reset signal to the first pixel unit, generates a signal and outputs the signal through the output signal unit. By using the technical scheme of the embodiment of the application, the miniaturization of the circuit is realized.

Description

Signal readout circuit, method and system, pixel unit array circuit and equipment

Technical Field

The present disclosure relates to the field of imaging technologies of image sensors, and in particular, to a signal readout circuit, a method and a system thereof, a pixel cell array circuit and a device thereof.

Background

The image sensor is always a hotspot of research, and the bionic pulse sequence type image sensor serving as a nerve morphology vision sensor has the characteristics of high frame frequency and low data throughput, and meets the requirement of high-speed imaging. The pulse sequence type image sensor records continuous light intensity information in a scene through the distribution of a high-density pulse sequence in an imaging mode simulating retina in primate organism, can capture and record high-speed movement, and can reconstruct texture details in the scene, so that the pulse sequence type image sensor has great application value in the machine vision, dynamic scene capture and other directions.

Disclosure of Invention

In view of this, embodiments of the present application provide a signal readout circuit, method and system, which can improve the imaging uniformity of an imaging array and achieve miniaturization of the circuit.

The embodiment of the application also provides a pixel array circuit and equipment, which can improve the imaging uniformity of an imaging array and realize the miniaturization of the circuit.

In one embodiment of the present application, there is provided a signal readout circuit including: a pixel array 201, a readout row selector 202, a reset row selector 203, at least one pixel sub-array readout feedback unit 204, and an output signal unit 205;

the readout row selector 202 transmits row readout signals to the pixel units in the corresponding row in the pixel array 201 to gate one row of pixel units in the pixel array 201;

the reset row selector 203 is used for sending a row reset signal to the pixel units of the row so as to gate the first reset switches of the pixel units in the row;

the pixel array 201 is composed of a plurality of pixel units arranged in at least one row, the pixel array 201 comprises at least one pixel sub-array, each pixel sub-array comprises a part of the pixel units, a first pixel unit which is positioned in a selected row in one pixel sub-array, and a pixel sub-array readout feedback unit 204 which is connected with the first pixel unit and converts optical signals into electric signals and outputs the electric signals; the first pixel unit receiving the reset signal sent by the pixel sub-array readout feedback unit 204 and the row reset signal sent by the reset row selector 203 gates the second reset switch and the first reset switch thereof, respectively, and executes a reset operation;

the pixel sub-array readout feedback unit 204 is connected to at least one pixel sub-array in the pixel array 201, receives the electrical signal transmitted by the first pixel unit, generates the reset signal when it is determined that a signal generation condition is met according to the electrical signal, and sends the reset signal to the first pixel unit, so as to gate the second reset switch of the first pixel unit, generate the signal, and output the signal through the output signal unit 205.

In the above circuit, the signal comprises: a pulse signal, or a level signal, or a value with a limit.

In the above circuit, the first pixel unit includes: a reset signal receiving module 301, a light sensing integration module 302 and an electric signal output module 303, wherein,

the reset signal receiving module 301 receives the row reset signal, gates the first reset switch, receives the reset signal, gates the second reset switch to execute the reset operation, and turns on the light sensing integration module 302;

the light sensing integration module 302, when in a conducting state, converts the optical signal into the electrical signal, and outputs the electrical signal to the electrical signal output module 303;

the electrical signal output module 303 receives the row readout signal, and outputs the electrical signal to the pixel sub-array readout feedback unit 204.

In the above circuit, the reset signal receiving block 301 includes: a first transistor 3a1 and a second transistor 3a2, the sensitization integration module 302 comprising: a photodiode 3a3, the electric signal output module 303 including: a third transistor 3a4 and a fourth transistor 3a5; wherein the content of the first and second substances,

the gate of the first transistor 3a1 is the first reset switch, receives the row reset signal, the source is the second reset switch, receives the reset signal, and the drain is connected to the gate of the second transistor 3a 2; the drain of the second transistor 3a2 is connected to a high-level voltage signal, and the source is connected to the output end of the photodiode 3a 3; the input end of the photodiode 3a3 is grounded; the gate of the third transistor 3a4 is connected to the output terminal of the photodiode 3a3, the drain is connected to the drain of the second transistor 3a2, and the source is connected to the drain of the fourth transistor 3a5; the source of the fourth transistor 3a5 outputs an electrical signal and the gate receives the row readout signal.

In the above circuit, the reset signal receiving module 301 includes: a first transistor 3b1 and a second transistor 3b2, wherein the light sensing integration module 302 comprises: a photodiode 3b3, the electric signal output module 303 including: a third transistor 3b4 and a fourth transistor 3b5; wherein the content of the first and second substances,

the gate of the first transistor 3b1 is the first reset switch, receives the row reset signal, the drain is connected to a high level, and the source is connected to the drain of the second transistor 3b 2; the gate of the second transistor 3b2 is the second reset switch, receives the reset signal, the source is connected to the output end of the photodiode 3b3, and the input end of the photodiode 3b3 is grounded; the gate of the third transistor 3b4 is connected to the output terminal of the photodiode 3b3, the drain of the third transistor 3b4 is connected to the drain of the first transistor 3b1, the source of the third transistor 3b4 is connected to the drain of the fourth transistor 3b5, the source of the fourth transistor 3b5 outputs the electrical signal, and the gate receives the row readout signal.

In the above circuit, the reset signal receiving block 301 includes: a first transistor 3c1, a second transistor 3c2, and a fifth transistor 3c3; the light sensing integration module 302 comprises: a photodiode 3c4 and a capacitor 3c5, and the electric signal output module 303 includes: a third transistor 3c6 and a fourth transistor 3c7; wherein, the first and the second end of the pipe are connected with each other,

the gate of the first transistor 3c1 is the first reset switch, receives the row reset signal, the source is the second reset switch, receives the reset signal, and the drain is connected to the gate of the second transistor 3c 2; the drain of the second transistor 3c2 is connected to a high-level voltage signal, and the source is connected to the drain of the fifth transistor 3c3; a source of the fifth transistor 3c3 is connected to an output terminal of the photodiode 3c4, an input terminal of the photodiode 3c4 is grounded and connected to one end of the capacitor 3c5, and the other end of the capacitor 3c5 is connected to a source of the second transistor 3c2 and a gate of the third transistor 3c 6; the source of the third transistor 3c6 is connected to the drain of the fourth transistor 3c7, the drain of the third transistor 3c6 is connected to the drain of the second transistor 3c2, the source of the fourth transistor 3c7 outputs the electrical signal, and the gate receives the row readout signal;

before the gate of the first transistor 3c1 receives the row reset signal and the source thereof receives the reset signal, the gate of the fifth transistor 3c3 receives a high-level voltage signal, so that the electric signal generated by the photodiode 3c4 from the optical signal is transferred to the capacitor 3c 5.

In the above circuit, the pixel sub-array readout feedback unit 204 includes: the pixel sub-array includes pixel units in a setting area, the area readout feedback unit 2041 is connected to the pixel units in the setting area in the pixel array 201, the pixel units in the setting area include a plurality of pixel units arranged in at least one column, the number of columns of the pixel units in the setting area is less than or equal to the number of columns of the pixel units in the pixel array 201, and the number of rows of the pixel units in the setting area is less than the number of rows of the pixel units in the pixel array 201.

In the circuit, one of the regional readout feedback units 2041 is connected to a plurality of corresponding pixel units arranged in a row, receives the electrical signal transmitted by the first pixel unit, and sends the reset signal to the first pixel unit; or

When one of the area readout feedback units 2041 is connected to a plurality of corresponding pixel units arranged in multiple columns, the area readout feedback unit is further configured to receive an electrical signal sent by a second pixel unit located in a different column from the first pixel unit, send the reset signal to the first pixel unit at a first time, and send the reset signal to the second pixel unit at a second time.

The pixel sub-array readout feedback unit 204 includes: the column-level readout feedback unit 2042, where the column-level readout feedback unit 2042 is connected to the pixel units in at least one set column in the pixel array 201, and the number of rows of the pixel units in the set column is the same as the number of rows of the pixel units in the pixel array 201.

In the above circuit, the pixel sub-array readout feedback unit 204 includes: a comparison module 501, an output module 502, and a multiplexing module 503, wherein,

the comparing module 501 receives the electrical signal transmitted by the first pixel unit, compares the electrical signal with a preset threshold signal, obtains a comparison result including the signal and a reset signal when the signal generation condition is determined to be met, and outputs the comparison result to the output module 502;

the output module 502 latches the comparison result, outputs the reset signal in the comparison result to the multi-channel selection module 503, and outputs the signal in the comparison result through the output signal unit 205;

the multi-path selection module 503 is configured to select a link with the first pixel unit, and send the reset signal to the first pixel unit through the link.

In the above circuit, the comparing module 501 includes: comparator, the output module 502 includes: reset set RS flip-flop and tristate gate device, the multichannel selection module includes: a multiplexer MUX, in which, among other things,

one input end of the comparator receives the electric signal transmitted by the first pixel unit, the other input end of the comparator receives the threshold signal, and the comparator compares the electric signal with the threshold signal to obtain a comparison result;

the comparator outputs the comparison result to an S end of the RS trigger, an R end of the RS trigger serves as a reset end, the output of the RS trigger is respectively connected with an input end of the MUX and an input end of the tri-state gate device, the reset signal in the comparison result is sent to the MUX, and the signal in the comparison result is sent to the tri-state gate device;

the MUX determines whether the reset signal is valid, and when the reset signal is determined to be valid, the MUX transmits the reset signal to the first pixel unit through the link;

when the resistance end of the tri-state gate device is set to a low level voltage, the output end outputs the signal to the output signal unit 205, and when the resistance end of the tri-state gate device is set to a high level voltage, the comparison result is latched.

In another embodiment of the present application, there is provided a signal readout method including:

a readout row selector in the signal readout circuit, which transmits a row readout signal to pixel units of a corresponding row in a pixel array to gate the pixel units of the row, wherein the pixel array is composed of a plurality of pixel units arranged in at least one row and at least one pixel sub-array, and each pixel sub-array comprises a part of the pixel units;

the pixel units in a selected row in one pixel sub-array output the electric signals converted by the optical signals to the pixel sub-array readout feedback units connected with the pixel sub-array readout feedback units;

the pixel sub-array reading feedback unit receives the electric signal, generates and outputs a signal when the condition of signal generation is judged to be met according to the electric signal, generates a reset signal and outputs the reset signal to the pixel unit which sends the electric signal;

a reset row selector in the circuit sends a row reset signal to the pixel units of the row, and the pixel units receiving the row reset signal and the reset signal are reset;

and returning to the readout row selector in the circuit, and sending the row readout signal to the pixel unit of the next row in the pixel array.

In another embodiment of the present application, there is provided a pixel cell array circuit including: a pixel unit array 1001 formed by pixel units arranged in at least one row in a row-column manner, wherein the pixel unit array 1001 comprises at least one pixel sub-array, the number of columns of the pixel units in the pixel sub-array is smaller than that of the pixel units in the pixel unit array 1001, and the number of rows of the pixel units in the pixel sub-array is equal to that of the pixel units in the pixel unit array 1001;

or the number of columns of pixel units in the pixel sub-array is less than or equal to the number of columns of pixel units in the pixel unit array 1001, and the number of rows of pixel units in the pixel sub-array is less than the number of rows of pixel units in the pixel unit array 1001;

the pixel cells of the pixel sub-array are connected to a pixel sub-array readout feedback unit 104, wherein the pixel cells of the pixel sub-array,

the pixel sub-array readout feedback unit 104 is used for converting an optical signal into an electrical signal, outputting the electrical signal to a connected pixel sub-array readout feedback unit 104 in a board level circuit after receiving a row readout signal, so that when the pixel sub-array readout feedback unit 104 judges that the electrical signal meets a signal generation condition, a reset signal is generated and sent to a connected pixel unit, and a signal is generated and output;

the pixel unit receiving the reset signal gates the second reset switch thereof in response to the reset signal, gates the first reset switch thereof in response to the row reset signal received from the reset row selector, and performs a reset operation.

In the above circuit, the pixel unit includes: a reset signal receiving module 301, a light sensing integration module 302 and an electric signal output module 303, wherein,

the reset signal receiving module 301 receives the row reset signal to gate the first reset switch, receives the reset signal sent by the pixel sub-array readout feedback unit 104 connected to the row reset signal receiving module, gates the second reset switch to execute the reset operation, and turns on the light sensing integration module 302;

the electrical signal output module 303 receives the row readout signal, and outputs the electrical signal to the pixel sub-array readout feedback unit 104.

In another embodiment of the present application, a signal readout method is provided, in a pixel unit array composed of pixel units arranged in at least one row in a row-column manner, the pixel unit array includes at least one pixel sub-array, each pixel sub-array includes a part of the pixel units, wherein the number of columns of the pixel units in the pixel sub-array is smaller than the number of columns of the pixel units in the pixel unit array, and the number of rows of the pixel units in the pixel sub-array is equal to the number of rows of the pixel units in the pixel unit array; or the number of columns of the pixel units in the pixel sub-array is less than or equal to the number of columns of the pixel units in the pixel unit array, and the number of rows of the pixel units in the pixel sub-array is less than the number of rows of the pixel units in the pixel unit array;

connecting pixel cells in the pixel sub-array to a pixel sub-array readout feedback unit, the method comprising:

after receiving the row reading signal, the pixel units in the pixel sub-array output an electric signal obtained by converting the optical signal to a pixel sub-array reading feedback unit in a board level circuit connected with the pixel units, so that when the pixel sub-array reading feedback unit judges that the electric signal meets a signal generation condition, the pixel sub-array reading feedback unit generates a reset signal and sends the reset signal to the connected pixel units, generates a signal and outputs the signal;

the pixel unit which receives the reset signal gates the second reset switch of the pixel unit, responds to the row reset signal received from the reset row selector, gates the first reset switch of the pixel unit, and executes the reset operation.

Another embodiment of the present application provides a signal processing system having a signal readout circuit, including: the signal readout circuit 11 and the processor 12, wherein,

the signal readout circuit 11 is configured to transmit the generated signals of the pixel units in the pixel array 201 to the processor 12 in a set transmission mode;

the processor 12 is configured to determine a set sending mode adopted by the signal readout circuit 11, locate the pixel unit and receive a signal of the corresponding pixel unit, and reconstruct an image based on the signal of the pixel unit and the position of the pixel unit; or the signals of the corresponding pixel units are adopted for detection based on the positions of the pixel units.

In another embodiment of the present application, there is provided an apparatus having a signal readout circuit for use in image sensor imaging, the apparatus comprising: the above-mentioned signal readout circuit, and/or the above-mentioned pixel cell array circuit, and/or the above-mentioned chip of the pixel cell array circuit.

In the above apparatus, the apparatus includes at least one of:

cameras, audio/video players, navigation devices, fixed location terminals, entertainment devices, smart phones, communication devices, mobile devices, vehicles or facilities, industrial devices, medical devices, security devices, flight devices, home appliance devices.

In an embodiment provided by the present application, a signal readout circuit includes: the pixel array, a readout row selector, a reset row selector, at least one pixel sub-array readout feedback unit and an output signal unit. The readout row selector transmits row readout signals to the pixel units of the corresponding row in the pixel array so as to gate one row of pixel units in the pixel array; the reset row selector is used for sending a row reset signal to the pixel units of the row so as to gate the first reset switches of the pixel units in the row; the pixel array is composed of a plurality of pixel units arranged in at least one row, the pixel array comprises at least one pixel sub-array, each pixel sub-array comprises a part of pixel units in the plurality of pixel units, a first pixel unit which is positioned in a selected row in one pixel sub-array converts an optical signal into an electric signal and outputs the electric signal to a pixel sub-array readout feedback unit connected with the pixel sub-array; the first pixel unit which receives the reset signal sent by the pixel sub-array readout feedback unit and the row reset signal sent by the reset row selector respectively gates the second reset switch and the first reset switch of the first pixel unit to execute reset operation; and the pixel sub-array reading feedback unit is connected with at least one pixel sub-array in the pixel array, receives the electric signal transmitted by the first pixel unit, generates the reset signal when the condition of signal generation is judged to be met according to the electric signal, and sends the reset signal to the first pixel unit so as to gate the second reset switch of the first pixel unit, generate the signal and output the signal through the output signal unit. In the embodiment of the present application, the functional modules for generating signals and reset signals in the pixel units in the circuit are implemented outside the pixel units, that is, the pixel sub-array readout feedback units are arranged to generate signals and reset signals of a plurality of pixel units connected to the pixel sub-array readout feedback units. And the pixel unit is provided with a functional module for generating an electric signal by an optical signal and a functional module for resetting according to the received row reset signal and the reset signal. In the embodiment of the present application, the multiplexing of the pixel sub-array readout feedback unit can multiplex the functional modules for determining and generating the signal and the reset signal in the plurality of pixel units located in the same pixel sub-array, so that the circuit area occupied by each pixel unit in the pixel array circuit can be reduced, and on the premise that the number of the pixel units is determined, the circuit scale can be reduced, thereby realizing the miniaturization of the circuit. By using the circuit structure provided by the embodiment of the application, the signal and reset signal generation functions of a plurality of different pixel units in the same pixel sub-array are uniformly realized by the connected pixel sub-array reading feedback units, so that the imaging uniformity of the imaging array is improved.

Drawings

Fig. 1 is a schematic circuit structure diagram of each pixel circuit unit in a pixel array circuit of a pulse sequence type image sensor;

fig. 2 is a general schematic diagram of a structure of a signal readout circuit according to an embodiment of the present disclosure;

fig. 3 is a schematic circuit diagram of a pixel unit according to an embodiment of the present disclosure;

fig. 3a is a schematic diagram of a specific implementation structure of a pixel unit according to an embodiment of the present disclosure;

fig. 3b is a schematic structural diagram of a specific implementation of a circuit of a pixel unit according to an embodiment of the present disclosure;

fig. 3c is a schematic diagram of a three-structure circuit implementation of a pixel unit according to an embodiment of the present disclosure;

fig. 4a is a schematic diagram of a structure of a signal readout circuit according to an embodiment of the present disclosure;

fig. 4b is a schematic diagram of a second structure of a signal readout circuit according to an embodiment of the present disclosure;

fig. 4c is a schematic structural diagram of another specific example of a second structure of a signal readout circuit according to an embodiment of the present disclosure;

fig. 5 is a schematic structural diagram of a column-level readout feedback unit according to an embodiment of the present application;

fig. 5a is a schematic diagram of a specific implementation structure of a column-level readout feedback unit according to an embodiment of the present application;

fig. 6 is a flowchart of a signal readout method according to an embodiment of the present application;

fig. 7 is a schematic structural diagram of a specific example of a signal readout circuit according to an embodiment of the present disclosure;

fig. 8 is a flowchart illustrating an exemplary embodiment of a signal reading method according to an embodiment of the present disclosure;

fig. 9 is a timing diagram of various signals involved in a signal readout process according to an embodiment of the present application;

fig. 10 is a schematic structural diagram of a pixel array circuit according to an embodiment of the present disclosure;

fig. 11 is a flowchart of a signal readout method based on the pixel array circuit of fig. 10 according to an embodiment of the present disclosure;

FIG. 12 is a block diagram of a signal processing system with signal readout circuitry according to an embodiment of the present disclosure;

fig. 13 is a schematic structural diagram of a pulse camera according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The terms "first," "second," "third," "fourth," and the like in the description and in the claims of the present application and in the drawings described above, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged under appropriate circumstances such that the embodiments of the application described herein may be implemented, for example, in sequences other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements explicitly listed, but may include other steps or elements not explicitly listed or inherent to such process, method, article, or apparatus.

The technical solution of the present application will be described in detail with specific examples. Several of the following embodiments may be combined with each other and some details of the same or similar concepts or processes may not be repeated in some embodiments.

In an embodiment of the present application, an imaging array circuit in a pulse sequence type image sensor is composed of a plurality of single pixel units arranged in an array manner, and the imaging array can also be referred to as a pixel array. The circuit structure of each pixel unit is shown in fig. 1, and fig. 1 is a schematic circuit structure diagram of each pixel circuit unit in a pixel array circuit of a pulse sequence type image sensor, including: the pixel unit comprises a photodiode, a reset transistor, a comparator, a self-reset unit and a pixel unit internal readout circuit. Under the condition of illumination, the photodiode integrates to generate photo-generated currentI _D Generating photo-generated chargeQ _D When generating electric chargeQ _D The threshold is reached after the judgment of the comparatorQ _ref The self reset unit resets the photodiode through the reset transistor and restarts integration, and simultaneously generates a signal 1, which is transmitted through the read circuit unit when a synchronous read signal arrives. Due to arrival of read signalIs one frame period, and thus no signal 1 is generated within one frame period, a signal 0 is output when the synchronous read signal comes.

It can be seen that the circuit of each pixel unit in the pixel array of the pulse sequence type image sensor includes a plurality of other devices besides the photodiode, and therefore the occupied area is large. On the premise that the whole circuit area is determined, a plurality of devices occupy more circuit space, so that the scale of an imaging array is limited, the Fill Factor (Fill Factor) of the pixel unit is reduced, the proportion of photosensitive area is smaller, and the imaging performance under the dark light condition is poor. In the pulse sequence type image sensor, an independent comparator is arranged in each pixel unit and used for realizing signal reading of the pixel unit and generation of a reset signal. Therefore, as many pixel units as there are, there are required as many independent comparators, making the circuit of the pixel unit complicated and making the scale of the pixel array large. In addition, since the offset voltages of the comparators in different pixel cells may be different, the imaging uniformity of the imaging array is reduced.

Therefore, in order to solve the above problem, in the embodiments of the present application, functional blocks for generating signals and reset signals in the pixel units in the circuit are implemented outside the pixel units, that is, signals and reset signals of a plurality of pixel units connected to the pixel units are generated by the pixel sub-array readout feedback units. And the pixel unit is provided with a functional module for generating an electric signal by an optical signal and a functional module for resetting according to a received row reset signal and a reset signal. The pixel unit outputs an electric signal to the connected pixel sub-array reading feedback unit under the control of the row reading signal, and resets under the control of the reset signal output by the pixel sub-array reading feedback unit and the row reset signal of the reset row selector.

Thus, the circuit area occupied by the circuit of each pixel unit in the pixel array circuit is reduced, and the circuit scale can be reduced on the premise that the number of the pixel units is determined, so that the miniaturization of the circuit is realized. Or, on the premise that the circuit scale is determined, because the circuit area of each pixel unit is reduced, more pixel units can be arranged for realizing photoelectric conversion, the dynamic range of imaging can be improved, and particularly the imaging performance under the dark light condition can be improved. By using the circuit structure provided by the embodiment of the application, the signal and reset signal generation functions of a plurality of different pixel units in the same pixel sub-array are uniformly realized by the connected pixel sub-array reading feedback units, so that the imaging uniformity of the imaging array is improved.

Specifically, due to the reduction of the implementation function modules in each pixel unit in the pixel array circuit, the occupied area of the function modules for generating electric signals by optical signals, namely photodiodes, can be increased, the fill factor of each pixel unit can be increased, the proportion of the photosensitive area of each pixel unit can be increased, and the imaging performance under the dark light condition can be improved. Because the functions of generating signals and resetting signals in different pixel units are uniformly realized by the pixel sub-array reading feedback unit, the problem that offset voltages adopting comparators in different pixel units connected with the pixel sub-array reading feedback unit in the pixel sub-array cannot be uniform is solved, and the imaging uniformity of a pixel array circuit serving as an imaging array is improved.

Here, the pulse train type image sensor is implemented by the signal readout circuit provided in the embodiment of the present application.

Fig. 2 is a schematic diagram of an overall structure of a signal readout circuit according to an embodiment of the present application, where the signal readout circuit is an imaging array circuit in a pulse sequential image sensor, and includes: a pixel array 201, a readout row selector 202, a reset row selector 203, at least one pixel sub-array readout feedback unit 204 and an output signal unit 205;

the reset row selector 203 sends a row reset signal to the pixel units of the row to gate the first reset switches of the pixel units in the row;

the pixel sub-array readout feedback unit 204 is connected to at least one pixel sub-array in the pixel array 201, receives the electrical signal transmitted by the first pixel unit, generates the reset signal when the electrical signal is judged to meet a signal generation condition according to the electrical signal, and sends the reset signal to the first pixel unit so as to gate a second reset switch of the first pixel unit; generates the signal and outputs the signal through the output signal unit 205.

As can be seen from the signal readout circuit described in fig. 2, in the embodiment of the present application, the functions of generating a signal and generating a reset signal in each pixel unit of the pixel array 201 are integrated in the pixel sub-array readout feedback unit 204 connected to the pixel unit, so that the circuit area of each pixel unit is reduced, the area of the signal readout circuit is further reduced, and the miniaturization of the circuit is realized. In addition, on the premise of not changing the scale of a signal reading circuit, the number of pixel units can be increased, the dynamic range of photoelectric conversion is improved, and the imaging performance under the dark light condition is improved. And the process of converting the electric signals into the signals of different pixel units governed by the same pixel sub-array reading feedback unit 204 is uniform, so that the nonuniformity of an array image caused by the offset voltage of the comparator in different pixel units is reduced.

In an embodiment of the present application, the signal includes: a pulse signal, a level signal, a value with a limit, etc., without limitation. Accordingly, the output signal unit 205 outputs a pulse signal, a level signal, a value with a limit, or the like, which is not limited herein.

In particular, the detailed description will be given by taking the signal as a pulse signal as an example.

In the circuit shown in fig. 2, the pixel array 201 includes a plurality of pixel units arranged in rows and columns, where m × n pixel units are m rows and n columns of pixel units, where m and n represent natural numbers.

In the embodiment of the present application, a circuit structure of the pixel unit is as shown in fig. 3, and includes: a reset signal receiving module 301, a light sensing integration module 302 and an electric signal output module 303, wherein,

the reset signal receiving module 301 receives the row reset signal, gates the first reset switch, receives the reset signal sent by the pixel sub-array readout feedback unit 204, gates the second reset switch to execute the reset operation, and turns on the photosensitive integration module 302;

the light sensing integration module 302, in a conducting state, converts the optical signal into the electrical signal under an illumination condition, and outputs the electrical signal to the electrical signal output module 303;

Specifically, the light sensing integration module 302 is usually implemented by a Photodiode (PD) or the like, the reset signal receiving module 301 is implemented by a cascade of a plurality of transistors, and the electrical signal output module 303 is implemented by a transistor.

Here, the electrical signal is a voltage signal or a current signal, and is not limited here.

As shown in fig. 3a, fig. 3a is a schematic diagram of a specific implementation structure of a circuit of a pixel unit according to an embodiment of the present disclosure. In this specific implementation, the reset signal receiving module 301 includes: a first transistor 3a1 and a second transistor 3a2, the light sensing integration module 302 comprises: a Photodiode (PD) 3a3, the electric signal output module 303 including: a third transistor 3a4 and a fourth transistor 3a5. Wherein the first transistor 3a1 includes: m _RS-SEL The second transistor 3a2 includes: m _RS The third transistor 3a4 includes: m is a group of _SF The fourth transistor 3a5 includes: m is a group of _SEL 。

The M is _RS-SEL The grid of the first reset switch receives the row reset signal, the source of the first reset switch receives the reset signal, the drain of the first reset switch and the M _RS The gate of (1) is connected; the M is _RS The drain of the PD is connected to a high level voltage signal, and the source is connected to the output end of the PD; an input terminal of the PD is grounded; said M _SF The grid electrode of the grid electrode is connected to the output end of the PD, and the drain electrode is connected to the M _RS A source electrode connected to the M _SEL A drain electrode of (1); the M is _SEL The gate receives the row readout signal.

In this particular implementation, the application is to the M _SEL Phi of _SEL The signal is a read signal, the voltage signal on the PD is transferred to the column output line of the array and is applied to the M _{RS_SEL} Phi of _{RS_SEL} Is a row reset signal phi _RS The signal is a reset signal for jointly controlling the reset operation of the PD.

As shown in fig. 3b, fig. 3b is a schematic diagram of a second specific structure of a circuit of a pixel unit according to an embodiment of the present disclosure. In this specific implementation, the reset signal receiving module 301 includes: a first transistor 3b1 and a second transistor 3b2, and the light sensing integration module 302 includes: a photodiode 3b3, the electric signal output module 303 including: a third transistor 3b4 and a fourth transistor 3b5. The first transistor 3b1, the second transistor 3b2, the third transistor 3b4, and the fourth transistor 3b5 are respectively: m _RS-SEL 、M _RS 、M _SF And M _SEL 。

Said M _RS-SEL The grid of the first reset switch is used for receiving the row reset signal, the drain is connected with a high level, and the source is connected with the M _RS The drain electrodes of the two electrodes are connected; the M is _RS The gate of the second reset switch is used for receiving the reset signal, the source of the second reset switch is connected to the output end of the PD, and the input end of the PD is grounded; the gate is connected to the output end of the PD, M _SF Is connected to the M _RS-SEL The drain electrode of (1), the M _SF Source electrode of the M _SEL The drain electrode of, the M _SEL The source outputs the electrical signal and the gate receives the row readout signal.

For the specific implementation circuit shown in fig. 3a or fig. 3b, which is a 3T-Active Pixel Sensor (APS), the application of each signal is the same. With the pixel cell shown in fig. 3a or fig. 3b, photoelectric conversion can be achieved with 3T-APS, and thus signal generation, readout, and reset operations of the pixel cell can be achieved.

As shown in fig. 3c, fig. 3c is a schematic diagram of a three-structure specific implementation of a circuit of a pixel unit provided in the embodiment of the present application. In this specific implementation, the reset signal receiving module 301 includes: a first transistor 3c1, a second transistor 3c2, and a fifth transistor 3c3; the sensitization integrating module 302 comprises: PD3c4 and a capacitor (FD) 3c5, and the electric signal output module 303 includes: a third transistor 3c6 and a fourth transistor 3c7. The first transistor 3c1, the second transistor 3c2, the third transistor 3c6, the fourth transistor 3c7, and the fifth transistor 3c3 each include: m _RS-SEL 、M _RS 、M _SF 、M _SEL And M _TG 。

The M is _RS-SEL The grid of the first reset switch receives the row reset signal, the source of the first reset switch receives the reset signal, the drain of the second reset switch and the M _RS The gate of (1) is connected; the M is _RS The drain electrode of the transistor is connected with a high level voltage signal, the source electrode of the transistor and the M _TG Is connected with the drain electrode of the transistor; said M _TG The input end of the PD is grounded and is connected with one end of the FD, and the other end of the FD is connected with the M _RS Source electrode of and the M _SF A gate electrode of (1); the M is _SF Source electrode of the M _SEL The drain electrode of (1), the M _SF Is connected to the M _RS The drain electrode of, the M _SEL The source electrode outputs the electric signal, and the grid electrode receives the row readout signal;

in specific implementation, the M _RS-SEL Before the source receives the reset signal, the grid receives the row reset signal, and the source receives the reset signal, the M _TG Receives a high-level voltage signal so that the PD transfers an electrical signal generated by an optical signal onto the FD.

In the embodiment shown in fig. 3c, the pixel cell is implemented by a 4T-APS circuit, in which M is arranged between PD and FD _TG And is used for controlling the on-off between the PD and the FD. In this embodiment, the 4T-APS may be utilized to implement the photoelectric conversion, and thus the generation and readout of signals and the reset operation of the pixel unit.

In the embodiment of the present application, based on the different positions and numbers of the pixel units managed by the pixel sub-array readout feedback unit 204, there may be two specific circuit implementation structures.

Fig. 4a is a schematic diagram illustrating a first circuit implementation structure, where fig. 4a is a schematic diagram illustrating a structure of a signal readout circuit according to an embodiment of the present disclosure. The pixel array is divided into different areas, the pixel units included in each area are set to be pixel sub-arrays, the area readout feedback unit 2041 is set for the different areas, and the area readout feedback unit 2041 generates reset signals and output signals required by the pixel units in the pixel sub-arrays. Specifically, the pixel sub-array readout feedback unit 204 includes an area readout feedback unit 2041, the area readout feedback unit 2041 is connected to the pixel units in the setting area in the pixel array 201, the pixel units in the setting area include a plurality of pixel units arranged in at least one column, the number of columns of the pixel units in the setting area is less than or equal to the number of columns of the pixel units in the pixel array 201, and the number of rows of the pixel units in the setting area is less than the number of rows of the pixel units in the pixel array 201.

The setting size of the pixel sub-array is not limited, and may be, for example, a pixel sub-array composed of 3 × 3 pixel units, or a pixel sub-array composed of multiple columns and at least one row of pixel units.

Here, when there is only one column of pixel units in the pixel sub-array (in this case, the number of rows of pixel units in the pixel sub-array is smaller than the number of rows of pixel units in the pixel array), one of the area readout feedback units 2041 is connected to a corresponding plurality of pixel units arranged in one column, receives the electrical signal transmitted by the first pixel unit, and transmits the reset signal to the first pixel unit.

Or, when there are multiple columns of pixel units in the pixel sub-array (in this case, the number of rows of pixel units in the pixel sub-array is less than or equal to the number of rows of pixel units in the pixel array, and when the number of columns of pixel units in the pixel sub-array is equal to the number of columns of pixel units in the pixel array, the number of rows of pixel units in the pixel sub-array is less than the number of rows of pixel units in the pixel array), one of the area readout feedback units 2041 is connected to a corresponding multiple of pixel units arranged in multiple columns, and is further configured to receive an electrical signal sent by a second pixel unit located in a different column from the first pixel unit, send the reset signal to the first pixel unit at a first time, and send the reset signal to the second pixel unit at a second time.

Fig. 4b is a schematic diagram illustrating a second circuit structure of a signal readout circuit according to an embodiment of the present disclosure. The pixel array is divided into different columns according to columns, the column-level readout feedback unit 2042 managed by the pixel array is set for at least one column of pixel units, and the column-level readout feedback unit 2042 generates reset signals and output signals required by pixel units in different rows in the managed column.

Specifically, the pixel sub-array readout feedback unit 204 includes a column-level readout feedback unit 2042, and the column-level readout feedback unit 2042 is connected to the pixel units in at least one set column in the pixel array 201, where the number of rows of the pixel units in the set column is the same as the number of rows of the pixel units in the pixel array 201.

In the second circuit structure of the embodiment of the present application, for each column of pixel units in the pixel array 201 of the circuit, a column-level readout feedback unit 2042 may be provided for one-to-one correspondence. Of course, for multiple columns of pixel units, a corresponding column level readout feedback unit 2042 may also be in a many-to-one relationship, so that multiple columns of pixel units share one corresponding column level readout feedback unit 2042, and thus, the circuit area of the pulse sequence type image sensor may be further reduced. Specifically, one of the column-level readout feedback units 2042 is connected to a corresponding column of pixel units, receives the electrical signal transmitted by a first pixel unit in the corresponding column of pixel units, and sends the reset signal to the first pixel unit; or, the column-level readout feedback unit 2042 is connected to the corresponding multiple columns of pixel units, and is further configured to receive an electrical signal sent by a second pixel unit located in a different column from the first pixel unit, send the reset signal to the first pixel unit at a first time, and send the reset signal to the second pixel unit at a second time.

As shown in fig. 4c, fig. 4c is a schematic structural diagram of another specific example of a second structure of a signal readout circuit according to an embodiment of the present disclosure. As can be seen from fig. 4c, a plurality of columns of pixel cells in the pixel array 201 of the circuit correspond to a column of the readout feedback units 2042. In this case, the column-level readout feedback unit 2042 receives an electrical signal and feeds back a reset signal by interacting with the corresponding pixel units in different columns at different times. For example, when three columns of pixel elements are connected to the column-level readout feedback unit 2042, a first column of pixel elements interacts with the column-level readout feedback unit 2042 at a first time of the frame period, such as the first third, a second column of pixel elements interacts with the column-level readout feedback unit 2042 at a second time of the frame period, such as the middle third, and a third column of pixel elements interacts with the column-level readout feedback unit 2042 at a third time of the frame period, such as the last third.

In a specific implementation, when the area readout feedback unit 2041 in the first circuit structure is connected to a plurality of pixel units in different columns in the setting area, the above time-division multiplexing manner is also used to implement interaction between the area readout feedback unit 2041 and the pixel units in different columns in the setting area, and the reset signals are fed back to the pixel units in different columns in the setting area at different times.

Fig. 5 is a schematic structural diagram of a column-level readout feedback unit according to an embodiment of the present disclosure. As shown, the column-level readout feedback unit 2042 includes: a comparison module 501, an output module 502, and a multiplexing module 503, wherein,

the output module 502 latches the comparison result of the first pixel unit, outputs the reset signal in the comparison result to the multi-channel selection module 503, and outputs the signal in the comparison result through the output signal unit 205;

In specific implementation, the specific structure of the area readout feedback unit 2041 is the same as the structure of the column-level readout feedback unit 2042 shown in fig. 5. And is the same as the specific implementation structure of the column-level readout feedback unit 2042 described in fig. 5a below, and is not described here again.

In specific implementation, the comparing module 501 in the column-level readout feedback unit 2042 is implemented by a comparator, the output module 502 is implemented by an RS flip-flop and a tristate gate device, and the multiplexing module 503 is implemented by a Multiplexer (MUX). As shown in fig. 5a, fig. 5a is a schematic diagram of a specific implementation structure of a column-level readout feedback unit according to an embodiment of the present application. The method comprises the following steps: the comparing module 501 includes: a comparator, the output module 502 includes: RS flip-flop and tristate gate device, multichannel selection module includes: a MUX that, among other things,

one input end of the comparator receives the electric signal transmitted by the first pixel unit, the other input end of the comparator receives the threshold signal, and the comparator compares the electric signal with the threshold signal to obtain the comparison result;

the comparator outputs the comparison result to an S end of the RS trigger, an R end of the RS trigger serves as a reset end, the output of the RS trigger is respectively connected with an input end of the MUX and an input end of the tristate gate device, the reset signal in the comparison result is sent to the MUX, and the signal in the comparison result is sent to the tristate gate device;

the MUX determines whether the reset signal in the comparison result is valid, and when the reset signal in the comparison result is valid, the MUX transmits the reset signal to the first pixel unit through the link;

when the impedance end of the tristate gate device is set to be a low level voltage, the output end outputs the signal to the output signal unit 205, and when the impedance end of the tristate gate device is set to be a high level voltage, the comparison result in the comparator is latched.

In the above specific example, a tristate gate device is included between the RS flip-flop and the output signal unit 205, and the RS flip-flop transmits a signal to the output signal unit 205 through the tristate gate device. When the output signal unit needs to be protected or no signal is output, the e end in the tristate gate device is set to be in a high impedance state, so that the RS trigger and the output signal unit are disconnected.

In the embodiment of the present application, the comparator may also adopt a multi-bit analog-to-digital converter (ADC), in which case, the obtained comparison result is multi-bit data, instead of merely "0" or "1" (0 indicates that it is an invalid reset signal, and cannot turn on the second reset switch in the corresponding pixel unit, so that the corresponding pixel unit cannot be reset, that is, does not meet the signal and reset signal generation condition), and before the RS flip-flop sends a reset signal to the MUX, when it is determined whether the comparison result is greater than the set reset threshold, the reset signal is sent.

In the embodiment of the present application, the RS flip-flop may be replaced by a D flip-flop, which is not limited herein.

Fig. 6 is a flowchart of a signal reading method provided in an embodiment of the present application, where the method is implemented based on the system shown in fig. 2, and includes the specific steps of:

step 601, a readout row selector in the signal readout circuit sends a row readout signal to pixel units in a corresponding row in a pixel array to gate the pixel units in the row, wherein the pixel array is composed of a plurality of pixel units arranged in at least one row and at least one pixel sub-array, and each pixel sub-array comprises a part of pixel units in the plurality of pixel units;

step 602, the selected pixel unit in a pixel sub-array outputs the electrical signal converted from the optical signal to the connected pixel sub-array read-out feedback unit;

step 603, the connected pixel sub-array reading feedback unit receives the electric signal, generates and outputs a signal when the condition of signal generation is judged to be met according to the electric signal, generates a reset signal and outputs the reset signal to the pixel unit which sends the electric signal;

step 604, a reset row selector in the circuit sends a row reset signal to the pixel units of the row, and the pixel units receiving the row reset signal and the reset signal perform reset.

In this step, the pixel unit receiving the reset signal gates the second reset switch of itself, and after receiving the row reset signal sent by the reset row selector, the pixel unit gates the first reset switch of itself. After the second reset switch and the first reset switch of the pixel unit are sequentially gated, the pixel unit performs a reset operation.

In this method, after the pixel unit receiving the row reset signal and the reset signal is reset, the method further includes:

returning to step 601, continuing to execute, that is, returning to the readout row selector in the circuit, sending the row readout signal to the pixel unit in the next row in the pixel array, and continuing to execute.

In the method, the pixel sub-array readout feedback unit connected to receive the electric signal, and when it is determined from the electric signal that a signal generation condition is satisfied, outputting the generated signal and outputting the generated reset signal to the pixel unit that transmitted the electric signal includes:

comparing the electric signal with a set threshold signal, and judging whether the electric signal reaches the set threshold signal, if so, outputting a signal of 1 and a reset signal of 1, and if not, outputting a signal of 0 and a reset signal of 0; a reset signal of 0 indicates an inactive reset signal and a reset signal of 1 indicates an active reset signal. When the reset signal is 0, the reset signal is not generated, which indicates that the reset signal received by the corresponding pixel unit is invalid, and the second reset switch of the pixel unit sending the electric signal cannot be turned on, so that the pixel unit sending the electric signal cannot be reset.

In the method, outputting the generated reset signal to the pixel unit transmitting the electric signal includes:

when the pixel sub-array comprises pixel cells within a set area of the pixel array, the pixel cells in the pixel sub-array are connected by an area readout feedback unit, wherein,

when a plurality of pixel units arranged in a column in the pixel sub-array are connected with one region readout feedback unit, receiving the electric signals transmitted by the pixel units sending the electric signals, and sending the reset signals to the pixel units sending the electric signals;

or, when a plurality of pixel units arranged in multiple columns in the pixel sub-array are connected to one of the region readout feedback units, the pixel sub-array is further configured to receive an electrical signal sent by a second pixel unit located in a different column from a first pixel unit sending the electrical signal, send the reset signal to the first pixel unit at a first time, and send the reset signal to the second pixel unit at a second time.

the pixel sub-array readout feedback units are column-level readout feedback units, and at least one column in the pixel array is connected with the column-level readout feedback units,

when a column of pixel units is connected with a column of level readout feedback units, the reset signal is directly output to the pixel units which send the electrical signals;

when the pixel units in multiple columns are connected with the readout feedback unit in one column level, if the electrical signals transmitted by the pixel units in each column are judged to meet the signal generation condition, the reset signals are respectively output to the pixel units in each column sent to the electrical signals at different moments.

The following description will be made in detail with reference to a specific embodiment.

Fig. 7 is a schematic structural diagram of a specific example of a signal readout circuit according to an embodiment of the present application, where a structure of a pixel unit in the structure adopts the specific implementation structure of fig. 3a, and a structure of a column-level readout feedback unit adopts the specific implementation structure of fig. 5a, and in the drawing, the column-level readout feedback unit is labeled as a column-level readout feedback module, which is not limited herein. In this specific example, a column of pixel units is cascaded with a column of readout feedback units, that is, a column of pixel units is in one-to-one correspondence with a column of readout feedback units.

Based on fig. 7, as shown in fig. 8, fig. 8 is a flowchart illustrating an embodiment of a signal reading method according to an embodiment of the present application, which includes the following steps:

step 801, selecting an ith row of signals to be read by a read row selector, wherein 0< = i < = m-1, m is a natural number, and sending row read signals to pixel units of the ith row;

step 802, the pixel units in the ith row receive row readout signals, output electrical signals converted from optical signals to a connected column-level readout feedback unit, and compare the electrical signals with a set threshold value by the connected column-level readout feedback unit to obtain signals and reset signals of the pixel units in the ith row; outputting the obtained signal;

in this step, if the trigger condition is reached, the signal is 1 and is valid and a reset signal is generated; if the trigger condition is not met, the signal is 0 and an invalid reset signal is obtained, namely the reset signal is not generated;

step 803, the column-level readout feedback unit transmits the obtained reset signal of the pixel unit connected to the ith row to the pixel unit;

step 804, selecting the ith row to be reset by a reset row selector, wherein 0< = i < = m-1, m is a natural number, and transmitting a row reset signal to the pixel units of the ith row; the pixel unit receiving the row reset signal and the reset signal carries out reset operation;

in this step, if the reset signal is an invalid reset signal, for example, if the reset signal is set to 0, it is determined that the reset signal is not received, and the reset operation is not performed.

Step 805, selecting the pixel unit of the (i + 1) th row as the pixel unit to output the signal, returning to step 801 and continuing to execute.

Referring to fig. 9, fig. 9 is a timing diagram of various signals involved in a signal readout process according to an embodiment of the present application.

In this example, the column-level readout feedback unit latches the comparison result by using a D flip-flop, whose trigger terminal is D _ clk.

At time t 0-t 1, a high-level voltage signal is applied to SEL [0] row in the circuit, the pixel unit of the 0 th row is gated, and the pixel unit of the 0 th row sends an electric signal generated by an optical signal to a connected column-level readout feedback unit.

And a comparator in the connected column-level readout feedback unit compares the transmitted electric signal with the Ref terminal voltage signal to obtain a comparison result, outputs the comparison result to the D trigger, applies a high-level voltage signal to the D _ clk terminal of the D trigger, and latches the comparison result.

And applying a high-level voltage signal to the Read end of the tristate gate device in the connected column-level reading feedback unit, outputting a comparison result latched in the D flip-flop as a signal, and obtaining a reset signal, namely VRS _ pix or 0, in the MUX in the connected column-level reading feedback unit according to the comparison result latched by the D flip-flop for outputting.

A high-level voltage signal is applied to the RS _ SEL [0] signal line to reset each pixel element in the 0 th row, and VRS _ pix or 0 in the j th column (0 < = j < = n) is applied to the pixel element at the (0, j) position to determine whether to reset the pixel element at the (0, j) position. Each pixel cell in row 0 receives a row reset signal, i.e., a high level voltage signal applied to the RS _ SEL [0] signal line, and only the pixel cells in the row that receive the reset signal perform a reset operation.

In the embodiment of the application, the signal readout circuit is composed of a pixel array circuit and a board level circuit, the structure of each pixel unit in the pixel array circuit is changed, so that each pixel unit generates an electric signal by an optical signal, and correspondingly, a pixel sub-array readout feedback unit comprising a column level readout feedback unit or an area readout feedback unit is added in the board level circuit to generate an electric signal to a signal and generate and feed back a reset signal, so that the imaging uniformity as an imaging array is improved, and the miniaturization of the circuit is realized.

Fig. 10 is a schematic structural diagram of a pixel cell array circuit provided in an embodiment of the present application, where the pixel cell array 1001 circuit structure includes: the pixel unit array 1001 comprises at least one pixel sub-array, wherein the number of columns of pixel units in the pixel unit sub-array is less than that of the pixel units in the pixel unit array 1001, and the number of rows of the pixel units in the pixel sub-array is equal to that of the pixel units in the pixel unit array 1001; or the number of columns of pixel units in the pixel sub-array is less than or equal to the number of columns of pixel units in the pixel unit array 1001, and the number of rows of pixel units in the pixel sub-array is less than the number of rows of pixel units in the pixel unit array 1001;

the pixel units in the pixel sub-array are connected with a pixel sub-array readout feedback unit 104, wherein the pixel units in the pixel sub-array are configured to convert optical signals into electrical signals, and output the electrical signals to the pixel sub-array readout feedback unit 104 connected in the board level circuit after receiving row readout signals, so that when the pixel sub-array readout feedback unit 104 determines that the electrical signals meet signal generation conditions, the pixel sub-array readout feedback unit generates reset signals and sends the reset signals to the connected pixel units, and generates signals for output;

the pixel unit which receives the reset signal gates the second reset switch of the pixel unit in response to the reset signal, and gates the first reset switch of the pixel unit in response to the row reset signal received from the reset row selector to execute the reset operation.

The structure of each pixel unit in the pixel array circuit provided in fig. 10 is specifically shown in fig. 3, and the specific implementation structure thereof is shown in fig. 3a to 3 c.

On the basis of the pixel unit array circuit provided in fig. 10, an embodiment of the present application further provides a signal readout method flowchart based on the pixel array circuit of fig. 10, as shown in fig. 11, in a pixel unit array composed of pixel units arranged in rows and columns to form at least one row, the pixel unit array includes at least one pixel sub-array, each pixel sub-array includes a part of the pixel units in the pixel units, where the number of columns of the pixel units in the pixel sub-array is less than the number of columns of the pixel units in the pixel unit array, and the number of rows of the pixel units in the pixel sub-array is equal to the number of rows of the pixel units in the pixel unit array; or the number of columns of the pixel units in the pixel sub-array is less than or equal to the number of columns of the pixel units in the pixel unit array, and the number of rows of the pixel units in the pixel sub-array is less than the number of rows of the pixel units in the pixel unit array; connecting pixel cells in the pixel sub-array to a pixel sub-array readout feedback unit, the method comprising:

step 1101, after receiving a row readout signal, a pixel unit in the pixel sub-array outputs an electrical signal obtained by converting an optical signal to a pixel sub-array readout feedback unit in a board level circuit connected to the pixel unit, so that when the pixel sub-array readout feedback unit determines that the electrical signal meets a signal generation condition, the pixel sub-array readout feedback unit generates a reset signal and sends the reset signal to the connected pixel unit, generates a signal and outputs the signal;

step 1102, the pixel unit receiving the reset signal gates the second reset switch of itself, responds to the row reset signal received from the reset row selector, gates the first reset switch of itself, and executes the reset operation.

It can be seen that in the embodiment of the present application, the provided pixel sub-array readout feedback unit implements the functions of the multiple pixel units connected to the pixel sub-array readout feedback unit, which generate signals from electrical signals and generate reset signals to reset the corresponding pixel units, and combines the function of generating electrical signals from optical signals in the corresponding pixel units in the pixel array circuit, which not only can effectively reduce the circuit area of the pixel units, but also can ensure that the original pulse transmission mode is not changed. On the premise of reducing the circuit area of the pixel unit, the filling factor of the pixel unit can be improved, so that the photosensitive area proportion of the pixel unit is improved. And the uniformity of the pixel array serving as an imaging array is improved by sharing the pixel subarray readout feedback unit by the plurality of pixel units.

In another embodiment of the present application, as shown in fig. 12, fig. 12 is a schematic structural diagram of a signal processing system with a signal reading circuit according to an implementation of the present application, including: the signal readout circuit 11 and the processor 12, wherein,

Specifically, when the readout feedback unit is an area readout feedback unit or a column-level readout feedback unit based on the pixel sub-array in the signal readout circuit 11, the transmission mode of transmitting the signal of each pixel unit is different: when the feedback unit is read out from the area, signals of the pixel units in the area are sent in the area according to a preset sending sequence, and the processor 12 receives the signals of the pixel units in each area and collects the signals to obtain the signals of the pixel units in the complete pixel array; when the feedback units are read out in a column level, signals of the pixel units in the set column are sent in the set column according to a preset sending sequence by taking the column level as a unit, and the processor 12 receives the signals of the pixel units in each column and sums the signals to obtain the signals of the pixel units in the complete pixel array.

Therefore, in order to locate which pixel unit the received signal of the pixel unit is transmitted, the processor 12 needs to determine the set transmission mode adopted by the signal readout circuit 11 to adapt the signal of the received pixel unit for locating each pixel unit to prepare for the reconstructed image of the subsequent pixel array or the detection of the subsequent pixel array.

In the system, after the processor 12 receives and sums the signals of each pixel unit in the pixel array, an image can be reconstructed, and subsequent detection and other processing can be performed; the signal can also be used directly for detection.

Specifically, in the first mode, the reconstructed image: the signals of the respective pixel units in the pixel array are converted into an image in a set image format, and subsequent detection and other processing are performed. Here, there are two ways of converting the image into the set image format: one is to reconstruct an image after converting the signal transmission interval of each pixel unit into multi-bit data; the other method is to convert the signal distribution number of the pixel unit into multi-bit data in a set time period to reconstruct an image.

The second mode is as follows: direct detection application: such as regarding the emission frequency of the signal of each pixel unit as the brightness of the pixel unit in the image, not reconstructing the image, acquiring the emission frequency of the signal of each pixel unit, and performing the brightness detection application.

In another embodiment of the present application, there is also provided an apparatus having a signal readout circuit, which is applied to imaging of an image sensor, the apparatus including the signal readout circuit described above, and/or including the pixel cell array circuit described above, and/or a chip having the pixel cell array circuit described above.

Specifically, the apparatus includes at least one of: cameras, audio/video players, navigation devices, fixed location terminals, entertainment devices, smart phones, communication devices, mobile devices, vehicles or facilities, industrial devices, medical devices, security devices, flight devices, home appliance devices.

In embodiments of the present application, the camera includes, but is not limited to, a pulse camera, a high speed camera, an industrial inspection camera, and the like. Cameras include, but are not limited to: the device comprises a vehicle-mounted camera, a mobile phone camera, a traffic camera, a camera installed on a flyable object, a medical camera, a security camera or a household appliance camera.

The device provided by the embodiment of the application is described in detail by taking a pulse camera as an example. Fig. 13 is a schematic structural diagram of a pulse camera according to an embodiment of the present application. As shown in fig. 13, the pulse camera includes: a lens 1301, a signal circuit 1302, a data processing circuit 1303, a nonvolatile memory 1304, a power supply circuit 1305, a volatile memory 1306, a control circuit 1307, and an I/O interface 1308.

The lens 1301 is used for receiving incident light from a subject, i.e., an optical signal.

A signal circuit 1302 for converting the optical signal received through the lens 1301 into an electrical signal and generating a signal from the electrical signal. The signal circuit 1302 includes, for example, the above-described signal readout circuit, and/or the above-described pixel cell array circuit, and/or a chip having the above-described pixel cell array circuit.

A data processing circuit 1303, configured to control a signal reading process, the data processing circuit 1303, for example, includes: the arithmetic processing unit (e.g., CPU) and/or the image processing unit (GPU) control, for example, a signal readout process of the signal readout circuit, control a readout row selector among them to send a row readout signal, a reset row selector to send a reset signal, and the like.

1306 is a volatile memory such as a Random Access Memory (RAM), 1304 is a non-volatile storage device such as a Solid State Disk (SSD), a Hybrid Hard Disk (HHD), a Secure Digital (SD) card, a mini SD card, and the like.

In an embodiment of the present application, the pulse camera further includes: and a display unit for real-time/playback displaying the signal/image information. The pulse camera according to the embodiment of the present application may further include at least one of: a wired/wireless transmission interface such as a WiFi interface, a bluetooth interface, a usb interface, an RJ45 interface, a Mobile Industry Processor Interface (MIPI) interface, a Low Voltage Differential Signaling (LVDS) interface, and other interfaces having a wired or wireless transmission function.

The pulse camera provided by the embodiment of the application can be used for detecting visible light, infrared light, ultraviolet light, X-rays and the like, and can be applied to various scenes, wherein common scenes comprise but are not limited to:

the vehicle-mounted camera can be used as a vehicle-mounted camera and installed in various vehicles or facilities, such as information acquisition and control for vehicle-road coordination, intelligent traffic and automatic driving. For example, the recording instrument is installed in rail vehicles such as high-speed rails or on rail transit lines and used as a high-speed rail driving recorder; it may also be installed in an autonomous vehicle or a vehicle installed with an Advanced Driving Assistance System (ADAS), for example, to perform detection and warning of information of a vehicle, a pedestrian, a lane, a driver, and the like.

The traffic camera can be used as a traffic camera and installed on a traffic signal rod to perform shooting, early warning, cooperative control and the like of vehicles and pedestrians on urban roads and expressways.

Can be used as an industrial inspection camera, for example, installed on a high-speed rail traffic line for high-speed rail line patrol, and for inspection of high-speed rail safety; the method can also be used for detecting and early warning specific industrial scenes such as coal mine conveyor belt breakage detection, transformer substation arc detection, real-time detection of wind power generation blades, non-stop detection of high-speed turbines and the like.

The imaging device is mounted on a flyable object, such as an airplane, a satellite and the like, and is used for high-definition imaging of the object in a high-speed flying and even high-speed rotating scene.

Industrial (machine vision in smart manufacturing, etc.), civilian (judicial evidence, sports penalties, etc.), and consumer electronics (cameras, movie media, etc.).

Can be used as a medical camera and can carry out high-definition medical imaging in clinical diagnosis and treatment such as medical treatment, cosmetology, health care and the like.

The camera can be used as a sports camera or a wearable camera, such as a head-mounted camera or a camera embedded in a wristwatch, and can shoot scenes such as various sports competition fields, daily leisure sports and the like.

The camera can also be used as a security camera, a mobile phone camera or a household appliance camera and the like.

The flowchart and block diagrams in the figures of the present application illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments disclosed herein. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams or flowchart illustration, and combinations of blocks in the block diagrams or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

It will be appreciated by those skilled in the art that various combinations and/or combinations of features recited in the various embodiments of the disclosure and/or in the claims may be made even if such combinations or combinations are not explicitly recited in the present application. In particular, various combinations and/or combinations of features recited in the various embodiments and/or claims of the present application may be made without departing from the spirit and teachings of the present application, and all such combinations and/or combinations are intended to fall within the scope of the present disclosure.

The principles and embodiments of the present application are described herein using specific examples, which are provided only for the purpose of understanding the method and the core idea of the present application and are not intended to limit the present application. It will be appreciated by those skilled in the art that changes may be made in this embodiment and its broader aspects and without departing from the principles, spirit and scope of the invention, and that all such modifications, equivalents, improvements and equivalents as may be included within the scope of the invention are intended to be protected by the claims.

Claims

1. A signal readout circuit, applied to a pulse sequential image sensor, comprising: the pixel array (201), a readout row selector (202), a reset row selector (203), at least one pixel sub-array readout feedback unit (204) and an output signal unit (205);

the readout row selector (202) transmits row readout signals to pixel units of a corresponding row in the pixel array (201) to gate a row of pixel units in the pixel array (201);

the reset row selector (203) sends a row reset signal to the pixel units of the row to gate the first reset switches of the pixel units in the row;

the pixel array (201) is composed of a plurality of pixel units which are arranged in at least one row, the pixel array (201) comprises at least one pixel sub-array, each pixel sub-array comprises a part of pixel units in the plurality of pixel units, a first pixel unit which is positioned in a selected passing mode in one pixel sub-array converts an optical signal into an electric signal and outputs the electric signal to a connected pixel sub-array readout feedback unit (204); the first pixel unit gates a second reset switch of the first pixel unit after receiving a reset signal sent by the pixel sub-array readout feedback unit (204) connected with the first pixel unit, gates the first reset switch of the first pixel unit after the second reset switch of the first pixel unit gates the second reset switch of the first pixel unit and after receiving the row reset signal sent by the reset row selector (203), and executes reset operation;

and the pixel sub-array reading feedback unit (204) is connected with at least one pixel sub-array in the pixel array (201), receives the electric signal transmitted by the first pixel unit, generates the reset signal when the condition of signal generation is judged to be met according to the electric signal, and transmits the reset signal to the first pixel unit so as to gate the second reset switch of the first pixel unit, generate the signal and output the signal through the output signal unit (205).

2. The signal sensing circuit of claim 1, wherein the signal comprises: a pulse signal, or a level signal, or a value with a limit.

3. A signal readout circuit according to claim 2, wherein the first pixel unit includes: a reset signal receiving module (301), a light sensing integration module (302) and an electric signal output module (303), wherein,

the reset signal receiving module (301) receives the row reset signal, gates the first reset switch, receives the reset signal, gates the second reset switch to execute the reset operation, and turns on the light sensing integration module (302);

the light sensing integration module (302) converts the optical signal into the electric signal and outputs the electric signal to the electric signal output module (303) when in a conducting state;

and the electric signal output module (303) receives the row readout signals and outputs the electric signals to the pixel sub-array readout feedback units (204) connected with the row readout signals.

4. A signal readout circuit according to claim 3, wherein the reset signal receiving module (301) comprises: a first transistor (3 a 1) and a second transistor (3 a 2), the sensitization integration module (302) comprising: a photodiode (3 a 3), the electric signal output module (303) comprising: a third transistor (3 a 4) and a fourth transistor (3 a 5); wherein the content of the first and second substances,

the grid electrode of the first transistor (3 a 1) is the first reset switch and receives the row reset signal, the source electrode of the first transistor is the second reset switch and receives the reset signal, and the drain electrode of the first transistor is connected with the grid electrode of the second transistor (3 a 2); the drain electrode of the second transistor (3 a 2) is connected to a high-level voltage signal, and the source electrode of the second transistor is connected to the output end of the photodiode (3 a 3); the input end of the photodiode (3 a 3) is grounded; the grid electrode of the third transistor (3 a 4) is connected to the output end of the photodiode (3 a 3), the drain electrode is connected to the drain electrode of the second transistor (3 a 2), and the source electrode is connected to the drain electrode of the fourth transistor (3 a 5); the source of the fourth transistor (3 a 5) outputs an electrical signal and the gate receives the row readout signal.

5. A signal readout circuit according to claim 3, wherein the reset signal receiving module (301) comprises: a first transistor (3 b 1) and a second transistor (3 b 2), wherein the light reception integration module (302) comprises: a photodiode (3 b 3), the electric signal output module (303) comprising: a third transistor (3 b 4) and a fourth transistor (3 b 5); wherein the content of the first and second substances,

the grid electrode of the first transistor (3 b 1) is the first reset switch, the grid electrode of the first transistor receives the row reset signal, the drain electrode of the first transistor is connected with a high level, and the source electrode of the first transistor is connected with the drain electrode of the second transistor (3 b 2); the grid electrode of the second transistor (3 b 2) is the second reset switch, the second reset switch receives the reset signal, the source electrode of the second transistor is connected to the output end of the photodiode (3 b 3), and the input end of the photodiode (3 b 3) is grounded; the gate of the third transistor (3 b 4) is connected to the output terminal of the photodiode (3 b 3), the drain of the third transistor (3 b 4) is connected to the drain of the first transistor (3 b 1), the source of the third transistor (3 b 4) is connected to the drain of the fourth transistor (3 b 5), the source of the fourth transistor (3 b 5) outputs the electrical signal, and the gate receives the row readout signal.

6. A signal readout circuit according to claim 3, wherein the reset signal receiving module (301) comprises: a first transistor (3 c 1), a second transistor (3 c 2), and a fifth transistor (3 c 3); the sensitization integrating module (302) comprises: a photodiode (3 c 4) and a capacitor (3 c 5), wherein the electric signal output module (303) includes: a third transistor (3 c 6) and a fourth transistor (3 c 7); wherein, the first and the second end of the pipe are connected with each other,

the grid electrode of the first transistor (3 c 1) is the first reset switch and receives the row reset signal, the source electrode of the first transistor is the second reset switch and receives the reset signal, and the drain electrode of the first transistor is connected with the grid electrode of the second transistor (3 c 2); the drain electrode of the second transistor (3 c 2) is connected with a high-level voltage signal, and the source electrode of the second transistor is connected with the drain electrode of the fifth transistor (3 c 3); the source of the fifth transistor (3 c 3) is connected to the output end of the photodiode (3 c 4), the input end of the photodiode (3 c 4) is grounded and connected to one end of the capacitor (3 c 5), and the other end of the capacitor (3 c 5) is connected to the source of the second transistor (3 c 2) and the gate of the third transistor (3 c 6); the source of the third transistor (3 c 6) is connected to the drain of the fourth transistor (3 c 7), the drain of the third transistor (3 c 6) is connected to the drain of the second transistor (3 c 2), the source of the fourth transistor (3 c 7) outputs the electrical signal, and the gate receives the row readout signal;

before the gate of the first transistor (3 c 1) receives the row reset signal and the source receives the reset signal, the gate of the fifth transistor (3 c 3) receives a high-level voltage signal, so that the electric signal generated by the photodiode (3 c 4) through the optical signal is transferred to the capacitor (3 c 5).

7. A signal readout circuit according to claim 2, wherein the pixel sub-array readout feedback unit (204) comprises: the pixel sub-array comprises a region readout feedback unit (2041), the region readout feedback unit (2041) is connected with the pixel units in the setting region in the pixel array (201), the pixel units in the setting region comprise a plurality of pixel units arranged in at least one column, the number of columns of the pixel units in the setting region is less than or equal to the number of columns of the pixel units in the pixel array (201), and the number of rows of the pixel units in the setting region is less than the number of rows of the pixel units in the pixel array (201).

8. The signal sensing circuit of claim 7,

the region readout feedback unit (2041) is connected with the plurality of corresponding pixel units which are arranged in a row, receives the electric signal transmitted by the first pixel unit, and sends the reset signal to the first pixel unit; or

When the regional readout feedback unit (2041) is connected with a plurality of corresponding pixel units which are arranged in multiple columns, the regional readout feedback unit is further used for receiving an electric signal sent by a second pixel unit which is positioned in a different column from the first pixel unit, sending the reset signal to the first pixel unit at a first moment, and sending the reset signal to the second pixel unit at a second moment.

9. A signal readout circuit according to claim 2, wherein the pixel sub-array readout feedback unit (204) comprises: a column level readout feedback unit (2042), wherein the column level readout feedback unit (2042) is connected with the pixel units in at least one set column in the pixel array (201), and the number of rows of the pixel units in the set column is the same as that of the pixel units in the pixel array (201).

10. A signal readout circuit according to claim 2, wherein the pixel sub-array readout feedback unit (204) comprises: a comparison module (501), an output module (502) and a multi-path selection module (503), wherein,

the comparison module (501) receives the electrical signal transmitted by the first pixel unit, compares the electrical signal with a preset threshold signal, obtains a comparison result including the signal and a reset signal when the signal generation condition is judged to be met, and outputs the comparison result to the output module (502);

the output module (502) latches the comparison result, outputs the reset signal in the comparison result to the multi-path selection module (503), and outputs the signal in the comparison result through the output signal unit (205);

the multi-path selection module (503) is used for selecting a link between the multi-path selection module and the first pixel unit, and the reset signal is sent to the first pixel unit through the link.

11. A signal sensing circuit according to claim 10, wherein the comparing module (501) comprises: a comparator, the output module (502) comprising: reset set RS flip-flop and tristate gate device, multichannel selection module includes: a multiplexer MUX, in which, among other things,

when the resistance state end of the tri-state gate device is set to be low level voltage, the output end outputs the signal to the output signal unit (205), and when the resistance state end of the tri-state gate device is set to be high level voltage, the comparison result is latched.

12. A signal readout method applied to a pulse sequence type image sensor, comprising:

a readout row selector in the signal readout circuit, which sends a row readout signal to pixel units of a corresponding row in a pixel array to gate the pixel units of the row, wherein the pixel array is composed of a plurality of pixel units arranged in at least one row and at least one pixel sub-array, and each pixel sub-array comprises a part of the pixel units;

the selected pixel units in one pixel sub-array output the electric signals converted by the optical signals to the connected pixel sub-array read-out feedback unit;

a reset row selector in the circuit sends row reset signals to the pixel cells of the row;

the pixel unit receiving the reset signal resets after receiving the row reset signal;

returning to the readout row selector in the circuit, and sending the row readout signal to the pixel unit of the next row in the pixel array.

13. A pixel unit array circuit, which is applied to a pulse sequence type image sensor, comprises: a pixel cell array (1001) composed of pixel cells arranged in at least one row in a row-column manner, wherein the pixel cell array (1001) comprises at least one pixel sub-array, the number of columns of pixel cells in the pixel sub-array is smaller than the number of columns of pixel cells in the pixel cell array (1001), and the number of rows of pixel cells in the pixel sub-array is equal to the number of rows of pixel cells in the pixel cell array (1001);

or the number of columns of pixel units in the pixel sub-array is less than or equal to the number of columns of pixel units in the pixel unit array (1001), and the number of rows of pixel units in the pixel sub-array is less than the number of rows of pixel units in the pixel unit array (1001);

the pixel cells of the pixel sub-array are connected to a pixel sub-array readout feedback unit (104), wherein the pixel cells of the pixel sub-array,

the pixel sub-array read-out feedback unit (104) is used for converting the optical signal into an electrical signal and outputting the electrical signal to the connected pixel sub-array read-out feedback unit (104) in the board level circuit after receiving the row read-out signal, so that the pixel sub-array read-out feedback unit (104) generates a reset signal and sends the reset signal to the connected pixel unit when judging that the electrical signal meets the signal generation condition, and generates and outputs the signal;

and the pixel unit receiving the reset signal responds to the reset signal, responds to the row reset signal received from the reset row selector after gating the second reset switch of the pixel unit, and gates the first reset switch of the pixel unit to execute reset operation.

14. The pixel cell array circuit of claim 13, wherein the pixel cell comprises: a reset signal receiving module (301), a light sensing integration module (302) and an electric signal output module (303), wherein,

the reset signal receiving module (301) receives the row reset signal to gate the first reset switch, receives the reset signal sent by the connected pixel sub-array readout feedback unit (104), gates the second reset switch to execute the reset operation, and turns on the photosensitive integration module (302);

the light sensing integration module (302) converts the optical signal into the electric signal and outputs the electric signal to the electric signal output module (303) when the light sensing integration module is in a conducting state;

and the electric signal output module (303) receives the row readout signal and outputs the electric signal to the connected pixel sub-array readout feedback unit (104).

15. A signal readout method applied to a pulse sequence type image sensor, wherein in a pixel unit array composed of pixel units arranged in at least one row in a row-column manner, the pixel unit array comprises at least one pixel sub-array, each pixel sub-array comprises a part of the pixel units, wherein the number of columns of the pixel units in the pixel sub-array is less than that of the pixel units in the pixel unit array, and the number of rows of the pixel units in the pixel sub-array is equal to that of the pixel units in the pixel unit array; or the number of columns of the pixel units in the pixel sub-array is less than or equal to the number of columns of the pixel units in the pixel unit array, and the number of rows of the pixel units in the pixel sub-array is less than the number of rows of the pixel units in the pixel unit array;

connecting pixel cells in said pixel sub-array to a pixel sub-array readout feedback unit, said method comprising:

after receiving a row read signal, a pixel unit in the pixel sub-array outputs an electric signal obtained by converting an optical signal to a pixel sub-array read feedback unit in a board level circuit connected with the pixel unit, so that when the pixel sub-array read feedback unit judges that the electric signal meets a signal generation condition, the pixel sub-array read feedback unit generates a reset signal and sends the reset signal to the connected pixel unit, and generates a signal for output;

and after the second reset switch and the first reset switch of the pixel unit are sequentially gated, the pixel unit executes reset operation.

16. A signal processing system having a signal readout circuit, comprising: the signal readout circuit (11) and the processor (12) of any of claims 1-11,

the signal readout circuit (11) is used for transmitting the generated signals of the pixel units in the pixel array (201) to the processor (12) by adopting a set transmission mode;

the processor (12) is used for determining a set sending mode adopted by the signal reading circuit (11), positioning the pixel units and receiving signals of the corresponding pixel units, and reconstructing an image based on the signals of the pixel units and the positions of the pixel units; or the signals of the corresponding pixel units are adopted for detection based on the positions of the pixel units.

17. An apparatus having a signal readout circuit for use in image sensor imaging, the apparatus comprising: a signal readout circuit according to any one of claims 1 to 11, and/or a pixel cell array circuit according to any one of claims 13 to 14, and/or a chip having a pixel cell array circuit according to any one of claims 13 to 14.

18. The apparatus of claim 17, wherein the apparatus comprises at least one of:

cameras, audio/video players, navigation devices, fixed-location terminals, entertainment devices, smart phones, communication devices, mobile devices, vehicles or facilities, industrial devices, medical devices, security devices, flight devices, home appliance devices.