CN115378840B - Communication chip test system and method - Google Patents
Communication chip test system and method Download PDFInfo
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- CN115378840B CN115378840B CN202211299332.5A CN202211299332A CN115378840B CN 115378840 B CN115378840 B CN 115378840B CN 202211299332 A CN202211299332 A CN 202211299332A CN 115378840 B CN115378840 B CN 115378840B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/14—Arrangements for monitoring or testing data switching networks using software, i.e. software packages
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/50—Testing arrangements
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
- H04L7/0033—Correction by delay
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Abstract
The invention discloses a communication chip testing system and a method, relating to the technical field of chip testing, wherein the system comprises: the device comprises a test board, a test accompanying communication device, an interception communication device and an upper computer, wherein a chip to be tested is arranged on the test board; the test accompanying communication equipment is communicated with the chip to be tested so as to send a first signal to the chip to be tested or receive a second signal of the chip to be tested; the interception communication equipment is used for intercepting the second signal and generating a corresponding interception result; the upper computer communicates with the chip to be tested, the accompanying and testing communication equipment and the interception communication equipment respectively, and is used for sending a test command carrying the first time to the accompanying and testing communication equipment and sending an interception command carrying the second time to the interception communication equipment. The automatic test of the communication chip is realized through the upper computer and the accompanying test communication equipment, the test efficiency is improved, meanwhile, the accurate acquisition of the test result can be realized through the interception communication equipment, and the accuracy and the reliability of the test result are improved.
Description
Technical Field
The invention relates to the technical field of chip testing, in particular to a communication chip testing system and a communication chip testing method.
Background
Chip testing is the last pass of chip design, and if no good sample test is passed, the failure rate may be too high after mass production, resulting in a large amount of cost loss.
At present, most of common communication chip tests are manual tests, the workload is huge, the tests can be completed only for a long time through the manual tests, in the testing process, personnel are required to be relied on to observe and record the testing results in real time, errors occur easily in the testing results, and the accuracy and the reliability of the testing results are poor.
Disclosure of Invention
The present invention is directed to solving, at least in part, one of the technical problems in the related art. Therefore, a first object of the present invention is to provide a communication chip testing system, which implements automatic testing of a communication chip through an upper computer and an accompanying testing communication device, reduces testing workload, improves testing efficiency, and simultaneously can implement accurate acquisition of a testing result through monitoring the communication device, thereby improving accuracy and reliability of the testing result.
The second objective of the present invention is to provide a communication chip testing method.
In order to achieve the above object, an embodiment of a first aspect of the present invention provides a communication chip testing system, which includes: the test board, the chip to be tested locates on test board; the test accompanying communication equipment is communicated with the chip to be tested so as to send a first signal to the chip to be tested or receive a second signal of the chip to be tested, and the chip to be tested works in a preset communication state; the interception communication equipment is used for intercepting the second signal and generating a corresponding interception result; the host computer, the host computer respectively with by the chip of being surveyed, accompany and survey communication equipment and listen communication equipment and communicate, a test command who carries the very first time is sent to accompanying and surveying communication equipment, so that accompany and survey communication equipment and send the first signal to being surveyed the chip according to the test command when reaching the very first time, and send the interception command who carries the second time to listening communication equipment, so that listening communication equipment when reaching the second time listens the second signal that is surveyed the chip based on first signal feedback according to listening command, and generate corresponding interception result, and receive the interception result, and generate the test result according to the interception result.
According to the communication chip testing system provided by the embodiment of the invention, the upper computer sends a testing command carrying first time to the test communication equipment, so that the test communication equipment sends a first signal to the chip to be tested according to the testing command when reaching the first time, the chip to be tested works in a preset communication state, and sends an interception command carrying second time to the interception communication equipment, so that the interception communication equipment intercepts a second signal fed back by the chip to be tested based on the first signal according to the interception command when reaching the second time, generates a corresponding interception result, receives the interception result, and generates a testing result according to the interception result. Therefore, automatic testing of the communication chip is achieved through the upper computer and the accompanying testing communication equipment, testing workload is reduced, testing efficiency is improved, meanwhile, accurate obtaining of a testing result can be achieved through monitoring the communication equipment, and accuracy and reliability of the testing result are improved.
According to an embodiment of the invention, the upper computer is further configured to send time synchronization information to the accompanied test communication device and the interception communication device before sending the test command carrying the first time to the accompanied test communication device, so that the accompanied test communication device and the interception communication device perform time synchronization.
According to one embodiment of the invention, the system further comprises: the attenuation control equipment is arranged on a communication channel between the accompanied test communication equipment and the chip to be tested and is used for controlling the attenuation degree of the communication channel; the upper computer is further communicated with the attenuation control equipment and used for sending the attenuation value to the attenuation control equipment so that the attenuation control equipment can control the attenuation degree of the communication channel according to the attenuation value, the first signal or the second signal is transmitted in an attenuation mode, and the maximum anti-attenuation value of the tested chip is determined according to the monitoring result.
According to one embodiment of the invention, the system further comprises: the detector is communicated with the detected chip and is used for detecting the characteristic information of the second signal; the upper computer is further communicated with the detector to receive the characteristic information of the second signal and generate a test result according to the characteristic information of the second signal and the monitoring result.
According to one embodiment of the present invention, a test meter includes at least one of an oscilloscope for detecting at least one of frequency information and status information of a second signal, a spectrometer for detecting at least one of frequency information and amplitude information of the second signal, and a meter for detecting at least one of voltage, current, and power of a chip under test.
According to one embodiment of the invention, the system further comprises: the signal source is communicated with the chip to be tested and used for providing a preset signal for the chip to be tested; the upper computer is also communicated with the signal source to determine the characteristic information of the preset signal and send the characteristic information to the signal source so that the signal source can generate the preset signal according to the characteristic information.
According to one embodiment of the invention, the system further comprises: the instrument adapter is respectively connected with the detector and the signal source and is used for controlling the on-off of the detector, the signal source and the chip to be detected; the upper computer is also communicated with the instrument adapter and used for sending on-off signals to the instrument adapter so that the instrument adapter can control the on-off of the detector, the signal source and the chip to be detected according to the on-off signals.
According to one embodiment of the invention, the system further comprises: the power supply is used for supplying power to the test board; the upper computer is further connected with the power supply and used for sending a power supply instruction to the power supply so that the power supply can supply power to the test board according to the power supply instruction, wherein the power supply instruction comprises at least one of an on/off instruction, power supply voltage and power supply current.
According to one embodiment of the invention, the system further comprises: the switch, host computer pass through the switch and accompany and survey communication equipment, listen communication equipment, detector, signal source and power and communicate.
According to one embodiment of the invention, the system further comprises: the shielding box, test panel, chip under test, accompany and survey communication equipment, listen communication equipment and decay controlgear locate in the shielding box for shield other signals except first signal and second signal.
In order to achieve the above object, an embodiment of a second aspect of the present invention provides a communication chip testing method, which is applied to the communication chip testing system in the embodiment of the first aspect, and the method includes: sending a test command carrying a first time to the test accompanying communication equipment so that the test accompanying communication equipment sends a first signal to the chip to be tested according to the test command when reaching the first time; sending an interception command carrying second time to the interception communication equipment, so that the interception communication equipment intercepts a second signal fed back by the chip to be detected based on the first signal according to the interception command when the second time is reached, and generates a corresponding interception result; and receiving the interception result and generating a test result according to the interception result.
According to the communication chip testing method, the upper computer sends the testing command carrying the first time to the accompanying communication equipment, so that the accompanying communication equipment sends the first signal to the tested chip according to the testing command when the accompanying communication equipment reaches the first time, and sends the interception command carrying the second time to the interception communication equipment, so that the interception communication equipment intercepts the second signal fed back by the tested chip based on the first signal according to the interception command when the interception communication equipment reaches the second time, generates the corresponding interception result, and the upper computer receives the interception result and generates the testing result according to the interception result. Therefore, automatic testing of the communication chip is achieved through the upper computer and the accompanying testing communication equipment, testing workload is reduced, testing efficiency is improved, meanwhile, accurate obtaining of a testing result can be achieved through monitoring the communication equipment, and accuracy and reliability of the testing result are improved.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
FIG. 1 is a schematic diagram of a communication chip test system according to an embodiment of the present invention;
FIG. 2 is a diagram illustrating successful interception of test results according to an embodiment of the present invention;
FIG. 3 is a diagram illustrating test result interception failure according to one embodiment of the present invention;
FIG. 4 is a schematic structural diagram of a communication chip test system according to another embodiment of the present invention;
FIG. 5 is a schematic structural diagram of a communication chip test system according to another embodiment of the present invention;
FIG. 6 is a flow chart of a method for testing a communication chip according to an embodiment of the invention.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative and intended to explain the present invention and should not be construed as limiting the present invention.
The following describes a communication chip test system and method according to an embodiment of the present invention with reference to the drawings.
Fig. 1 is a schematic structural diagram of a communication chip test system according to an embodiment of the present invention. As shown in fig. 1, the communication chip test system includes: the test board 11, accompany and survey communication equipment 12, listen communication equipment 13 and host computer 14.
Wherein, the chip 110 under test is disposed on the test board 11; the test-accompanying communication device 12 communicates with the chip 110 to send a first signal to the chip 110 or receive a second signal of the chip 110, so that the chip 110 operates in a preset communication state; the interception communication device 13 is configured to intercept the second signal and generate a corresponding interception result; the upper computer 14 is respectively communicated with the tested chip 110, the accompanied test communication device 12 and the interception communication device 13, and is used for sending a test command carrying a first time to the accompanied test communication device 12, so that the accompanied test communication device 12 sends a first signal to the tested chip 110 according to the test command when reaching the first time, and sends an interception command carrying a second time to the interception communication device 13, so that the interception communication device 13 intercepts a second signal fed back by the tested chip 110 based on the first signal according to the interception command when reaching the second time, and generates a corresponding interception result, receives the interception result, and generates a test result according to the interception result.
It should be noted that the chip 110 under test is in serial communication connection with the upper computer 14 through the JTAG port on the test board 11, and the upper computer 14 can read and write the chip register, change the working state of the chip, and use various functions of the chip through this link, for example, in the chip receiving performance test process, read the data in the chip register to verify whether the receiving performance of the chip meets the requirements; the test-accompanying communication device 12 is connected with the chip 110 to be tested and the test board 11 through signal lines, and mainly has the functions of receiving a chip automatic test command and carrying out continuous communication with the chip 110 to be tested in a certain function so as to keep the chip 110 to be tested in a preset communication state; the main function of the interception communication device 13 is to intercept the communication message between the chip under test 110 and the test board 11 to determine whether the chip under test 110 is operating in a designated operating state.
Specifically, in the chip test process, the upper computer 14 runs chip automatic test software, and has a main function of loading various test scripts to read parameters such as instrument devices, IP addresses, and commands pre-stored in the test scripts, positioning the various instrument devices through the IP addresses, sending various command parameters to the corresponding instrument devices through the ethernet, initializing the instrument devices according to the test scripts, controlling the instrument devices according to steps according to a test flow specified in the scripts to automatically test each sample point, and after the test is finished, reading test results from the corresponding instrument devices and recording the test results in a result file.
The upper computer 14 sends a test command carrying a first time to the test accompanying communication device 12 according to the test script, the test accompanying communication device 12 sends a first signal to the test accompanying chip 110 according to the test command when reaching the first time, the test accompanying chip 110 starts to execute corresponding chip tests after receiving the first signal, a second signal is formed and sent after a series of tests, the upper computer 14 also sends a listening command carrying a second time to the listening communication device 13 according to the test script, it needs to be stated that the sequence and the interval time of sending commands to the test accompanying communication device 12 and the listening communication device 13 are preset in the test script, optionally, after sending the test command carrying the first time to the test accompanying communication device 12 according to the test script, a period of time passes, then sending the listening command carrying the second time to the listening communication device 13, when the time reaches the second time, the listening communication device 13 listens to the second signal fed back by the test accompanying chip 110 according to the listening command, if the listening communication device 13 can successfully obtain the second signal, and record the test result, and if the second signal can not be obtained, the test accompanying communication device 12 can record the second signal can not successfully obtain the test result.
From this, realized the automatic test to communication chip through host computer and accompanying and testing communication equipment, reduced test load, improved efficiency of software testing, can realize the accuracy acquisition to the test result through listening communication equipment simultaneously, improved the accuracy and the reliability of test result.
In some embodiments, as shown in fig. 1, the upper computer 14 is further configured to send time synchronization information to the accompanied test communication device 12 and the listening communication device 13 before sending the test command carrying the first time to the accompanied test communication device 12, so as to synchronize the accompanied test communication device 12 and the listening communication device 13 in time.
That is to say, time synchronization information is also prestored in the test script in the upper computer 14, before the upper computer 14 sends a test command carrying the first time to the accompanied test communication device 12, the upper computer 14 also sends time synchronization information to the accompanied test communication device 12 and the interception communication device 13 so as to realize time synchronization of the accompanied test communication device 12 and the interception communication device 13, and after the accompanied test communication device 12 and the interception communication device 13 realize time synchronization, the upper computer 14 sends the test command and the detection command to the accompanied test communication device 12 and the interception communication device 13 respectively and performs subsequent chip tests.
Further, as a specific example, as shown in fig. 2, when performing chip testing, the automatic test software periodically sends a time synchronization command for synchronizing the time of the test communication device and the interception communication device, after receiving the time synchronization command, the test communication device and the interception communication device calibrate their own running clocks according to the time synchronization command to achieve time synchronization, after time synchronization of the test communication device and the interception communication device, the automatic test software sends a test command 1 with a delay time td1, and sends a test command 2 with a delay time td2 and a window time tp1 after a certain time, the test communication device sends the test command 1 to the chip to be tested according to the received test command 1, so that the chip to be tested automatically tests according to the test command 1, and forms a corresponding test result, after receiving the test command 2 by the interception communication device, the delay 2 executes the test command 2, the window time continuously executed by the test command 2 is the tp1, and if the test result is successfully sent to the interception communication device within the test window tp1, and the interception communication device can report the test result to the interception communication device after receiving the test command 2; as shown in fig. 3, if the test time of the tested chip executing the test command 1 is too long to meet the requirement of time slot response, that is, the interception communication device cannot receive the test result within the window time tp1, and then the interception failure result is uploaded to the upper computer, and the upper computer records the test failure result.
In some embodiments, as shown in fig. 4, the system further comprises: the attenuation control device 15, the attenuation control device 15 is arranged on the communication channel between the accompanied communication device 12 and the chip 110 to be tested, and is used for controlling the attenuation degree of the communication channel; the upper computer 14 is further in communication with the attenuation control device 15, and is configured to send an attenuation value to the attenuation control device 15, so that the attenuation control device 15 controls the attenuation degree of the communication channel according to the attenuation value, so that the first signal or the second signal is transmitted in an attenuation manner, and the maximum anti-attenuation value of the chip to be tested is determined according to the interception result.
Specifically, as shown in fig. 4, the above-mentioned communication chip testing system further includes an attenuation control device 15, where the attenuation control device 15 is a device installed on a communication channel between the test-accompanied communication device 12 and the chip 110 under test, and mainly functions to receive an attenuation value issued by the automatic test software, control the attenuation degree of the communication channel according to the attenuation value, make the first signal or the second signal perform attenuation transmission, and determine the maximum anti-attenuation value of the chip under test according to the interception result, thereby determining the transceiving performance of the chip under test.
In some embodiments, as shown in fig. 4, the system further comprises: the detector 16, the detector 16 communicates with the chip 110 to be detected, and is configured to detect characteristic information of the second signal; the upper computer 14 is also in communication with the detector 16 to receive the characteristic information of the second signal and generate a test result according to the characteristic information of the second signal and the interception result.
Further, the detector comprises at least one of an oscilloscope, a frequency spectrograph and a meter, wherein the oscilloscope is used for detecting at least one of frequency information and state information of the second signal, the frequency spectrograph is used for detecting at least one of frequency spectrum information and amplitude information of the second signal, and the meter is used for detecting at least one of voltage, current and power of the chip to be detected.
Specifically, as shown in fig. 4, the above-mentioned communication chip testing system further includes a detector 16, where the detector 16 is connected to the chip 110 under test through a signal line, and is configured to obtain characteristic information of a second signal fed back by the chip 110 under test according to the first signal, and the detector 16 includes at least one of an oscilloscope, a spectrometer, and a meter, where when the detector 16 includes the oscilloscope, the oscilloscope is configured to feed back characteristic information of the second signal, such as frequency or state, to the test chip, and if the fed back characteristic information of the second signal, such as frequency or state, can be sensed by the sensing communication device 13 within the window time tp1, the characteristic information of the second signal is fed back to the host computer 14 to generate a test result; when the detector 16 includes a spectrometer, the spectrometer is configured to feed back, by the test chip, characteristic information such as a frequency spectrum or an amplitude of the second signal, and if the fed back characteristic information such as the frequency spectrum or the amplitude of the second signal can be sensed by the sensing communication device 13 within the window time tp1, the characteristic information of the second signal is fed back to the upper computer 14 to generate a test result; when the detector 16 includes a meter, the meter is configured to feed back characteristic information of the second signal, such as voltage, current, and power, to the test chip, and if the fed back characteristic information of the second signal, such as voltage, current, and power, can be sensed by the sensing communication device 13 within the window time tp1, the characteristic information of the second signal is fed back to the upper computer 14 to generate a test result.
It should be noted that, according to the requirement of the test type, other types of detectors may be added, for example, a programmable digital multimeter may be connected when measuring the current and voltage of the chip, and the automatic test software controls the detectors to read the measurement result.
Therefore, when the performance test is carried out, the required test instrument can be preset according to the requirement so as to realize the detection of different characteristic information, the test efficiency is improved, the previous manual adjustment is avoided, and the test workload is reduced.
Further, to make those skilled in the art clearly understand the present invention, as a specific example, taking the anti-attenuation performance of the tested chip as an example, in the process of executing the test, the automatic test software in the upper computer 14 first performs time synchronization on the accompanied test communication device 12, the interception communication device 13, and the tested chip 110, then starts the interception communication device 13, and configures the interception duration, that is, sets the interception window time tp1.
It should be noted that the automatic test software is the core of the system operation, and the automatic test software includes a physical layer sending library of a tested chip, a physical layer receiving library, a tested chip configuration library, an instrument control database, an accompanied test communication device library, and an interception communication device library.
The automatic test software executes parameters in the test script in the test process, as shown in table 1, all sample points to be tested, parameters of used instrument and equipment and register addresses and assignments of chips to be tested are stored in the test script, each row of the test script corresponds to each test sample point, each column corresponds to a test step, parameters and data are stored in each cell, in the test process, the automatic test software reads data line by line, the corresponding cell contents of each column are sequentially read from the first column to the last column, the test data are filled in corresponding data positions in a test instruction, after the data reading is finished, corresponding chip tests are executed according to the test instruction, and test results are recorded in corresponding tables. Therefore, the automatic test software configures parameters of various instruments according to a test flow designed by a given test script, completes the test of a large number of sample points circularly, reads and records the required test result from the corresponding instrument, and greatly shortens the test time.
TABLE 1
| Attenuation control apparatus | Accompany survey communication equipment | Interception communication device | Chip to be tested | Other steps 8230 | Test results | |
| |
|
|
|
|
Register address assignment for parameter or control chip | Store the |
| Test sample Point 2 | Parameter 2 | Parameter 2 | Parameter 2 | Register address 2+ value 2 | Parameter or control chip register address assignment | Store the result 2 in this cell |
| … | … | … | … | … | … | … |
| Test sample point n | Parameter n | Parameter n | Parameter n | Register address n + value n | Register address assignment for parameter or control chip | Store the result n in this cell |
In some embodiments of the present invention, the upper computer 14 finds the initialization commands of the chip under test 110, the test-assisting communication device 12, the interception communication device 13, the attenuation control device 15, and the oscilloscope corresponding to the anti-attenuation test from the chip under test 110, the test-assisting communication device 12, the interception communication device 13, the attenuation control device 15, and the oscilloscope library according to the automated test script, and reads the initialization parameters of the chip under test 110 and the instruments from the test script, so as to form a complete test instruction with the initialization commands and the parameters and send the complete test instruction to the corresponding instruments.
When the anti-attenuation performance test is carried out, the attenuation value of the current test point in the test script is read according to the test flow information, the attenuation value is sent to the chip 110 to be tested through the test communication device 12, meanwhile, the test communication device 12 continuously sends a test signal to the chip 110 to be tested, the monitoring communication device 13 monitors the test result fed back by the chip 110 to be tested within the monitoring window time tp1, if the monitoring communication device 13 can detect the feedback signal, the feedback signal is sent to the automatic test software, whether the test result meets the expectation is judged by the automatic test software, the automatic test software can also obtain the output waveform of the oscilloscope to judge whether the waveform meets the expectation, if both meet the expectation requirements, the test result passes the test, the next test point is read from the test script, the attenuation value of the signal between the test communication device 12 and the chip 110 to be tested is increased until the communication device 13 does not receive or receive the feedback data wrong by the chip 110 to be tested within the set monitoring window time tp1, and the attenuation value of the signal waveform output by the oscilloscope does not meet the expected, the maximum attenuation value of the anti-attenuation value of the chip to be tested on the chip to be tested is recorded in the anti-attenuation file line-by line.
In some embodiments, as shown in fig. 5, the system further comprises: the signal source 17, the signal source 17 communicates with the chip 110 under test, is used for providing the chip 110 under test with the preset signal; the upper computer 14 also communicates with the signal source 17 to determine characteristic information of the preset signal and sends the characteristic information to the signal source 17 so that the signal source 17 generates the preset signal according to the characteristic information. That is to say, the above-mentioned communication chip test system further includes the signal source 17, which is used for providing a preset signal to the chip under test 110, specifically, the signal source 17 is mainly used for injecting noise into the tested environment of the analog test, simulating signal interference in some actual working scenes, and testing the working condition of the communication chip under the condition of simulating signal interference.
In some embodiments, as shown in fig. 5, the system further comprises: the instrument adapter 18 is connected with the detector 16 and the signal source 17 respectively, and is used for controlling the on-off of the detector 16, the signal source 17 and the tested chip 110; the upper computer 14 is also in communication with the instrument adapter 18 and is used for sending an on-off signal to the instrument adapter 18, so that the instrument adapter 18 controls the on-off of the detector 16, the signal source 17 and the tested chip 110 according to the on-off signal.
Specifically, the communication chip test system further includes an instrument adapter 18, and its main function is to switch a signal path between the detector 16 and the chip 110 to be tested and to control signal on/off between the signal source 17 and the chip 110 to be tested, for example, when the detector 16 includes an oscilloscope, a spectrometer, and a meter, if the upper computer 14 sends an oscilloscope on signal to the instrument adapter 18, the instrument adapter 18 controls the signal path between the oscilloscope and the chip 110 to be tested to be on, and if the upper computer 14 sends an oscilloscope off signal and a spectrometer on signal to the instrument adapter 18, the instrument adapter 18 controls the signal path between the oscilloscope and the chip 110 to be tested to be off, and simultaneously controls the signal path between the spectrometer and the chip 110 to be tested to be on; similarly, the upper computer 14 can realize on-off control of the signal source 17 by sending a signal source on-off signal to the instrument adapter 18, and therefore, by sending the on-off signal to each instrument, automatic switching of signal channels between a chip to be tested and different instruments can be realized, switching time in the testing process of the instruments is greatly saved, and testing efficiency is improved.
In some embodiments, as shown in fig. 5, the system further comprises: a power supply 19, wherein the power supply 19 is used for supplying power to the test board 11; the upper computer 14 is further connected to the power supply 19 and configured to send a power supply instruction to the power supply 19, so that the power supply 19 supplies power to the test board 11 according to the power supply instruction, where the power supply instruction includes at least one of an on/off instruction, a power supply voltage, and a power supply current.
Specifically, the power supply 19 is connected with the test board 11 through a power line and used for supplying power to the test board 11, the power supply 19 is also connected with the upper computer 14, the upper computer 14 can be used for controlling the on-off of the power supply 19 and changing the power supply voltage and/or power supply current of the power supply, the automation degree of the test system is improved, and the defects that the voltage current and the power supply switch need to be adjusted manually in the prior art are overcome.
In some embodiments, as shown in fig. 5, the system further comprises: and the switch 20 and the upper computer 14 are communicated with the accompanied and tested communication equipment 12, the interception communication equipment 13, the detector 16, the signal source 17 and the power supply 19 through the switch 20. That is, the switch 20 is configured to forward the test name sent by the automatic test software to each instrument, receive the test result fed back by each instrument, and forward the test result to the upper computer 14.
In some embodiments, as illustrated with continued reference to fig. 5, the system further comprises: the shielding box 21, the test board 11, the chip 110 to be tested, the test-accompanying communication device 12, the listening communication device 13 and the attenuation control device 15 are arranged in the shielding box 21 and used for shielding other signals except the first signal and the second signal. That is to say, the system is further provided with a shielding box 21, and the shielding box 21 is mainly used for shielding various external interference signals irrelevant to the first signal and the second signal, so that the working environment of the chip 110 to be tested and the accompanied test communication device 12 is cleaner, and the test result is more accurate.
In summary, according to the communication chip testing system of the embodiment of the present invention, the upper computer sends the test command carrying the first time to the accompanied test communication device, so that the accompanied test communication device sends the first signal to the chip to be tested according to the test command when reaching the first time, so that the chip to be tested works in the preset communication state, and sends the interception command carrying the second time to the interception communication device, so that the interception communication device intercepts the second signal fed back by the chip to be tested based on the first signal according to the interception command when reaching the second time, generates the corresponding interception result, receives the interception result, and generates the test result according to the interception result. From this, realized the automatic test to communication chip through host computer and accompanying and testing communication equipment, reduced test load, improved efficiency of software testing, can realize the accuracy acquisition to the test result through listening communication equipment simultaneously, improved the accuracy and the reliability of test result.
FIG. 6 is a flow chart of a method for testing a communication chip according to an embodiment of the invention. As shown in fig. 6, the communication chip testing method includes the steps of:
step S101, a test command carrying first time is sent to the test accompanying communication device, so that the test accompanying communication device sends a first signal to the chip to be tested according to the test command when reaching the first time.
And step S102, sending an interception command carrying second time to the interception communication equipment, so that the interception communication equipment intercepts a second signal fed back by the detected chip based on the first signal according to the interception command when reaching the second time, and generating a corresponding interception result.
And step S103, receiving the interception result and generating a test result according to the interception result.
It should be noted that, for the description of the communication chip testing method in the present application, reference may be made to the description of the communication chip testing system in the present application, and details are not repeated here.
According to the communication chip testing method provided by the embodiment of the invention, the upper computer sends the testing command carrying the first time to the test accompanying communication equipment, so that the test accompanying communication equipment sends the first signal to the tested chip according to the testing command when reaching the first time, and sends the interception command carrying the second time to the interception communication equipment, so that the interception communication equipment intercepts the second signal fed back by the tested chip based on the first signal according to the interception command when reaching the second time, and generates the corresponding interception result, and the upper computer receives the interception result and generates the testing result according to the interception result. From this, realized the automatic test to communication chip through host computer and accompanying and testing communication equipment, reduced test load, improved efficiency of software testing, can realize the accuracy acquisition to the test result through listening communication equipment simultaneously, improved the accuracy and the reliability of test result.
It should be noted that the logic and/or steps represented in the flowcharts or otherwise described herein, such as an ordered listing of executable instructions that can be considered to implement logical functions, can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. For the purposes of this description, a "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable medium would include the following: an electrical connection (electronic device) having one or more wires, a portable computer diskette (magnetic device), a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium could even be paper or another suitable medium upon which the program is printed, as the program can be electronically captured, via for instance optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner if necessary, and then stored in a computer memory.
It should be understood that portions of the present invention may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the various steps or methods may be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any one or combination of the following techniques, which are known in the art, may be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application specific integrated circuit having an appropriate combinational logic gate circuit, a Programmable Gate Array (PGA), a Field Programmable Gate Array (FPGA), or the like.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or to implicitly indicate the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless explicitly specified otherwise.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship, unless expressly stated otherwise. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
Although embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are exemplary and not to be construed as limiting the present invention, and that changes, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.
Claims (9)
1. A communication chip test system, the system comprising:
the test board is used for arranging the tested chip on the test board;
the test accompanying communication equipment is communicated with the chip to be tested so as to send a first signal to the chip to be tested or receive a second signal of the chip to be tested, and the chip to be tested works in a preset communication state;
the interception communication device is used for intercepting the second signal and generating a corresponding interception result;
the detector is communicated with the chip to be detected and is used for detecting the characteristic information of the second signal; the detecting instrument comprises at least one of an oscilloscope, a frequency spectrograph and a measuring instrument, wherein the oscilloscope is used for detecting at least one of frequency information and state information of the second signal, the frequency spectrograph is used for detecting at least one of frequency spectrum information and amplitude information of the second signal, and the measuring instrument is used for detecting at least one of voltage, current and power of the chip to be detected;
the instrument adapter is connected with the detector and used for controlling the on-off of the detector and the chip to be detected;
the upper computer is respectively communicated with the tested chip, the accompanied test communication equipment, the interception communication equipment, the detector and the instrument adapter, and is used for sending a test command carrying first time to the accompanied test communication equipment, so that the accompanied test communication equipment sends the first signal to the tested chip according to the test command when reaching the first time, sends an interception command carrying second time to the interception communication equipment, so that the interception communication equipment intercepts a second signal fed back by the tested chip based on the first signal according to the interception command when reaching the second time, generates a corresponding interception result, and sends an on-off signal to the instrument adapter, so that the instrument controls the on-off of the detector according to the on-off signal, so that the detector detects the characteristic information of the second signal, receives the interception result and the characteristic information of the second signal, and generates a test result according to the characteristic information of the second signal and the interception result.
2. The test system according to claim 1, wherein the upper computer is further configured to send time synchronization information to the test assistant communication device and the interception communication device before sending the test command carrying the first time to the test assistant communication device, so that the test assistant communication device and the interception communication device perform time synchronization.
3. The test system of claim 1 or 2, wherein the system further comprises:
the attenuation control device is arranged on a communication channel between the accompanied test communication device and the chip to be tested and is used for controlling the attenuation degree of the communication channel;
the upper computer is further communicated with the attenuation control equipment and used for sending an attenuation value to the attenuation control equipment so that the attenuation control equipment can control the attenuation degree of the communication channel according to the attenuation value, the first signal or the second signal is enabled to be transmitted in an attenuation mode, and the maximum anti-attenuation value of the tested chip is determined according to the monitoring result.
4. The test system according to claim 1 or 2, wherein the system further comprises:
the signal source is communicated with the chip to be tested and used for providing a preset signal for the chip to be tested;
the upper computer is further communicated with the signal source to determine characteristic information of the preset signal and send the characteristic information to the signal source, so that the signal source can generate the preset signal according to the characteristic information.
5. The test system of claim 4, wherein the instrument adapter is connected to the signal source for controlling the connection and disconnection between the signal source and the chip under test;
the upper computer is further used for sending a switching signal to the instrument adapter so that the instrument adapter can control the switching between the signal source and the chip to be tested according to the switching signal.
6. The test system of claim 5, wherein the system further comprises:
the power supply is used for supplying power to the test board;
the upper computer is further connected with the power supply and used for sending a power supply instruction to the power supply so that the power supply can supply power to the test board according to the power supply instruction, wherein the power supply instruction comprises at least one of an on/off instruction, power supply voltage and power supply current.
7. The test system of claim 6, wherein the system further comprises:
the upper computer communicates with the accompanying and measuring communication equipment, the interception communication equipment, the detector, the signal source and the power supply through the switch.
8. The test system of claim 3, wherein the system further comprises:
and the test board, the chip to be tested, the test accompanying communication equipment, the interception communication equipment and the attenuation control equipment are arranged in the shielding box and used for shielding other signals except the first signal and the second signal.
9. A communication chip testing method applied to the communication chip testing system according to any one of claims 1 to 8, the method comprising:
sending a test command carrying a first time to the test accompanying communication equipment so that the test accompanying communication equipment sends the first signal to the chip to be tested according to the test command when reaching the first time;
sending an interception command carrying a second time to the interception communication device, so that the interception communication device intercepts a second signal fed back by the chip to be detected based on the first signal according to the interception command when the second time is reached, and generates a corresponding interception result;
and receiving the interception result, and generating a test result according to the interception result.
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