CN115377956A - Electrostatic discharge protection circuit - Google Patents

Electrostatic discharge protection circuit Download PDF

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Publication number
CN115377956A
CN115377956A CN202110542166.6A CN202110542166A CN115377956A CN 115377956 A CN115377956 A CN 115377956A CN 202110542166 A CN202110542166 A CN 202110542166A CN 115377956 A CN115377956 A CN 115377956A
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CN
China
Prior art keywords
transistor
coupled
power rail
esd protection
protection circuit
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Pending
Application number
CN202110542166.6A
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Chinese (zh)
Inventor
许至淳
王昭龙
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Winbond Electronics Corp
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Winbond Electronics Corp
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Publication date
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Priority to CN202110542166.6A priority Critical patent/CN115377956A/en
Publication of CN115377956A publication Critical patent/CN115377956A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
    • H02H9/045—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere
    • H02H9/046—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere responsive to excess voltage appearing at terminals of integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H01L27/027—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements specially adapted to provide an electrical current path other than the field effect induced current path
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0292—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

The invention provides an electrostatic discharge protection circuit which comprises a first transistor, a second transistor, a capacitor, a voltage division circuit and a first diode. The first transistor is coupled between the first power rail line and the second power rail line. The second transistor is coupled between the first power rail and the second power rail, and the block of the second transistor is coupled to the control terminal of the first transistor. The capacitor is coupled between the first power rail and the control terminal of the second transistor. The voltage division circuit is coupled between the control terminal of the second transistor and the second power rail, and has a voltage division voltage output terminal coupled to the block of the second transistor. The first diode is coupled between the divided voltage output end and the second power rail line.

Description

Electrostatic discharge protection circuit
Technical Field
The present invention relates to an electrostatic discharge protection circuit, and more particularly, to an electrostatic discharge protection circuit capable of improving electrostatic discharge protection capability.
Background
In the prior art, to ensure that the integrated circuit is not damaged by the esd, an esd protection circuit is usually added to the integrated circuit to provide a leakage path for the esd current and prevent the circuit components from being damaged. In the prior art, a power clamp (power clamp) circuit is often provided between the power rails as an esd protection circuit.
Due to the electrostatic discharge phenomenon, a positive pulse voltage or a negative pulse voltage may be generated between the power rails of the integrated circuit. The esd protection circuit needs to generate a current leakage path effectively in response to these conditions, so as to perform an effective protection operation on the integrated circuit. In the prior art, circuit elements are usually configured according to different voltage pulse states in the esd event to provide a current leakage path. Such an approach often requires additional circuit components and results in wasted circuit layout area.
Disclosure of Invention
The invention is directed to an electrostatic discharge protection circuit, which can reduce the circuit layout area and improve the protection capability of electrostatic discharge.
According to an embodiment of the present invention, an esd protection circuit includes a first transistor, a second transistor, a capacitor, a voltage divider circuit, and a first diode. The first transistor is coupled between the first power rail line and the second power rail line. The second transistor is coupled between the first power rail and the second power rail, and the block of the second transistor is coupled to the control terminal of the first transistor. The capacitor is coupled between the first power rail and the control terminal of the second transistor. The voltage division circuit is coupled between the control end of the second transistor and the second power supply rail and is provided with a voltage division voltage output end which is coupled to the block of the second transistor. The first diode is coupled between the divided voltage output end and the second power rail line.
In accordance with the above, a diode is formed between the bulk of the second transistor and the capacitor-resistor network for providing the bias voltage of the control terminal of the second transistor. By the diode, when the negative voltage pulse is generated, a path can be provided to conduct the first transistor in real time, a leakage path of the electrostatic discharge current is rapidly provided, and the electrostatic discharge protection capability is effectively improved. In this embodiment, the diode can be formed by the resistor (N-type) and the substrate (P-type) of the integrated circuit, and no additional layout is required, thereby saving circuit area.
Drawings
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and together with the description serve to explain the principles of the invention.
FIG. 1 is a schematic diagram of an ESD protection circuit according to an embodiment of the present invention;
FIG. 2 is a cross-sectional view of the layout structure of the resistor R2 and the diode D1 in the embodiment of FIG. 1 according to the present invention;
FIG. 3A and FIG. 3B are schematic diagrams illustrating ESD protection operations of an ESD protection circuit according to an embodiment of the present invention;
FIG. 4 is a circuit diagram of an ESD protection circuit according to another embodiment of the present invention;
FIG. 5 is a top view of a layout structure of a portion of the ESD protection circuit 400 according to the embodiment of the present invention in FIG. 4.
Description of the reference numerals
100. 300, 400: an electrostatic discharge protection circuit;
110. 410: a voltage dividing circuit;
210: a well region;
211. 212, 221: a doped region;
220: a substrate;
BK: a block body;
c1: a capacitor;
d1, D2: a diode;
DOE: a divided voltage output terminal;
g1: a gate electrode;
GND: a ground voltage;
m1, M2: a transmission wire;
ND1 to ND3: a doped region;
NW: an N-type well region;
PATH1 to PATH4: a path;
PS1: a negative pulse voltage;
PS2: a positive pulse voltage;
PWR1, PWR2: a power rail;
r1 and R2: a resistance;
SUB: a substrate;
t1, T2 transistors;
VDD: a supply voltage;
VIA1 to VIA5: and connecting the window.
Detailed Description
Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.
Referring to fig. 1, fig. 1 is a schematic diagram of an esd protection circuit according to an embodiment of the invention. The esd protection circuit 100 includes transistors T1 and T2, a capacitor C1, a voltage divider circuit 110 and a diode D1. The transistor T1 is coupled between the first power supply rail PWR1 and the second power supply rail PWR2. The transistor T2 is coupled between the first power supply rail PWR1 and the second power supply rail PWR2. The bulk (bulk) of the transistor T2 is coupled to the control terminal of the transistor T1. In the present embodiment, the Transistor T1 is a Bipolar Junction Transistor (BJT), and the Transistor T2 can be a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). In detail, the transistor T1 may be an NPN type bipolar transistor, and the transistor T2 may be an N type mosfet.
In this embodiment, the first power rail PWR1 is configured to receive a power voltage, and the second power rail PWR2 is configured to receive a ground voltage.
In addition, the capacitor C1 is coupled between the first power rail PWR1 and a control terminal of the transistor T2, wherein the control terminal of the transistor T2 is the gate terminal thereof. The voltage divider circuit 110 is coupled between the control terminal of the transistor T2 and the second power rail PWR2. The voltage divider circuit 110 has a divided voltage output DOE coupled to the bulk of the transistor T2. In the present embodiment, the voltage divider circuit 110 includes resistors R1 and R2. One end of the resistor R1 is coupled to the control end of the transistor T2, and the other end of the resistor R1 is coupled to the divided voltage output DOE. One end of the resistor R2 is coupled to the divided voltage output DOE, and the other end of the resistor R2 is coupled to the second power rail PWR2.
The anode of the diode D1 is coupled to the second power rail PWR2, and the cathode of the diode D1 is coupled to the divided voltage output DOE and coupled to the bulk of the transistor T2 through the divided voltage output DOE.
In the present embodiment, the capacitor C1 and the voltage divider circuit 110 are used for dividing the positive pulse voltage generated on the first power rail PWR1 due to the electrostatic discharge phenomenon, and generating a bias voltage at the divided voltage output DOE to turn on the transistor T1. The transistor T1 is turned on to generate a current leakage path, thereby achieving the protection function of electrostatic discharge.
On the other hand, when the first power rail PWR1 generates the negative pulse voltage due to the electrostatic discharge phenomenon, the diode D1 is turned on in response to the negative pulse voltage and provides the bias voltage to turn on the transistor T1. Similarly, the current leakage path can be generated by turning on the transistor T1 to achieve the protection function against electrostatic discharge.
Referring to fig. 1 and fig. 2 synchronously, fig. 2 is a cross-sectional view of a layout structure of the resistor R2 and the diode D1 in the embodiment of fig. 1. The esd protection circuit 100 is disposed in an integrated circuit. The integrated circuit has a substrate (substrate) 220 and a well (well) 210. The well region 210 is disposed in a substrate 220. The well region 210 includes doped regions 211 and 212. In the present embodiment, the substrate 220 may be a P-type substrate, the well may be an N-type well, and the doped regions 211 and 212 may both be N + type doped regions.
In this embodiment, the resistor R2 may be an N-well formed between the doped regions 211 and 212. The circuit architecture of fig. 1 can be implemented by coupling the doped region 211 to the divided voltage output DOE and coupling the doped region 212 to the second power rail PWR2.
On the other hand, the substrate 220 further has a doped region 221. The doped region 221 may be a P + type doped region and is coupled to the second power trace PWR2. Thus, the diode D1 is constructed by the P-N junction formed by the substrate 220 and the well 210. The anode of the diode D1 may be coupled to the second power rail PWR2 through the doped region 221, and the cathode of the diode D1 may be coupled to the divided voltage output DOE through the doped region 212.
As is apparent from the above description, the diode D1 in the present embodiment can be formed by the parasitic effect generated when the resistor R2 is disposed, and does not require an additional layout area. Therefore, the layout area of the esd protection circuit 100 according to the embodiment of the present invention can be effectively reduced.
Referring to fig. 3A and 3B, fig. 3A and 3B are schematic diagrams illustrating an esd protection operation of an esd protection circuit according to an embodiment of the invention. In fig. 3A, the esd protection circuit 300 has the same circuit structure as the esd protection circuit 100, and details thereof are not repeated. When the negative pulse voltage PS1 is generated between the first power rail PWR1 and the second power rail PWR2 due to the electrostatic discharge phenomenon, the diode D1 is turned on according to the negative pulse voltage PS1, and a PATH1 is generated between the negative pulse voltage PS1, the diode D1, and the control terminal (base) of the transistor T1. Through the PATH1, a bias voltage VB is provided to the control terminal of the transistor T1 according to the negative pulse voltage PS1, and the transistor T1 is turned on. As a result, the transistor T1 can provide the current leakage PATH2 for esd protection.
On the other hand, when the positive pulse voltage PS2 is generated between the first power supply rail PWR1 and the second power supply rail PWR2 due to the electrostatic discharge phenomenon, the capacitor resistor network formed by the capacitor C1 and the resistors R1 and R2 can generate the bias voltage VB at the divided voltage output terminal DOE according to the positive pulse voltage PS 2. The bias voltage VB is provided to the control terminal of the transistor T1 through the PATH3, so that the transistor T1 can be turned on and provide the current leakage PATH4 for esd protection.
Referring to fig. 4, fig. 4 is a circuit diagram of an esd protection circuit according to another embodiment of the invention. The esd protection circuit 400 includes transistors T1 and T2, a capacitor C1, a voltage divider circuit 410, and diodes D1 and D2. The transistor T1 is coupled between the first power rail PWR1 and the second power rail PWR2. The transistor T2 is coupled between the first power rail PWR1 and the second power rail PWR2. The bulk of the transistor T2 is coupled to the control terminal of the transistor T1. In the present embodiment, the transistor T1 is a bipolar transistor, and the transistor T2 can be a mosfet. In detail, the transistor T1 may be an NPN type bipolar transistor, and the transistor T2 may be an N type mosfet.
In addition, the capacitor C1 is coupled between the first power rail PWR1 and the control terminal of the transistor T2, wherein the control terminal of the transistor T2 is connected to the gate terminal. The voltage divider circuit 410 is coupled between the control terminal of the transistor T2 and the second power rail PWR2. The voltage divider circuit 410 has a divided voltage output DOE coupled to the bulk of the transistor T2. In the present embodiment, the voltage divider circuit 410 includes resistors R1 and R2. One end of the resistor R1 is coupled to the control end of the transistor T2, and the other end of the resistor R1 is coupled to the divided voltage output DOE. One end of the resistor R2 is coupled to the divided voltage output DOE, and the other end of the resistor R2 is coupled to the second power rail PWR2. The first power supply rail PWR1 and the second power supply rail PWR2 receive the power supply voltage VDD and the ground voltage GND, respectively.
In the present embodiment, the anode of the diode D1 is coupled to the second power rail PWR2, and the cathode of the diode D1 is coupled to the divided voltage output DOE and coupled to the bulk of the transistor T2 through the divided voltage output DOE. In addition, unlike the previous embodiments, the esd protection circuit 400 of the present embodiment further includes a diode D2. The anode of the diode D2 is coupled to the divided voltage output DOE, and the cathode of the diode D2 is coupled to the control terminal of the transistor T2, i.e. the gate of the transistor T2.
Referring to fig. 5, fig. 5 is a top view of a partial layout structure of the esd protection circuit 400 according to the embodiment of the invention in fig. 4. The first plate of the capacitor C1 is electrically connected to the first power rail PWR1 through a plurality of connection windows VIA 2. The first power rail PWR1 is used for receiving a power voltage VDD. The second plate of the capacitor C1 is electrically connected to the gate G1 of the transistor T2 through a plurality of connection windows VIA3 and a transmission line M1. In addition, the second plate of the capacitor C1 is electrically connected to the N-type well NW through the transmission line M2. The N-type well region has a plurality of doped regions ND1 ND3, wherein a resistor R1 is formed between the doped regions ND1 ND2, and a resistor R2 is formed between the doped regions ND2 ND 3. The doped region ND2 is provided with a divided voltage output DOE.
In addition, an N-type well NW is disposed in the substrate SUB, and the substrate SUB is electrically connected to the second power trace PWR2 through a plurality of connection windows VIA 4. The second power rail PWR2 is used for receiving the ground voltage GND. The substrate SUB is a P-type substrate and forms a P-N junction with the N-well NW to produce diodes D1, D2. That is, in the present invention, the diodes D1 and D2 do not need to be laid out additionally, thereby effectively reducing the area required by the circuit.
In addition, the bulk BK of the transistor T2 is electrically connected to the divided voltage output DOE through the plurality of connection windows VIA 1. The first terminal (drain) of the transistor T2 is electrically coupled to the first power rail PWR1 through a plurality of windows VIA6, and the second terminal (source) of the transistor T2 is electrically coupled to the second power rail PWR2 through a plurality of windows VIA 5. The control terminal (base) of the transistor T1 is embedded in the block of the transistor T2 and electrically coupled to the divided voltage output terminal DOE through a plurality of connection windows VIA 1. The first terminal (collector) of the transistor T1 is embedded in the first terminal (drain) of the transistor T2, and is electrically coupled to the first power rail PWR1 through a plurality of VIA holes VIA 6. The second terminal (emitter) of the transistor T1 is embedded in the second terminal (source) of the transistor T2, and is electrically coupled to the second power trace PWR2 through a plurality of connection windows V1 A5. Therefore, the transistor T1 does not require an additional layout space, and the area required by the entire circuit can be effectively reduced.
According to the above, the esd protection circuit provided by the present invention can effectively improve the protection capability of the esd phenomenon of the negative pulse voltage by disposing the reverse biased diode between the block of the mosfet and the second power rail without occupying additional layout area, thereby improving the reliability of the integrated circuit.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims (10)

1. An ESD protection circuit, comprising:
a first transistor coupled between the first power rail and the second power rail;
a second transistor coupled between the first power rail and the second power rail, a bulk of the second transistor being coupled to a control terminal of the first transistor;
a capacitor coupled between the first power rail and the control terminal of the second transistor;
a voltage divider circuit coupled between the control terminal of the second transistor and the second power rail and having a divided voltage output terminal coupled to the bulk of the second transistor; and
and the first diode is coupled between the divided voltage output end and the second power supply rail line.
2. The ESD protection circuit of claim 1, wherein the voltage divider circuit comprises:
a first resistor, a first terminal of which is coupled to the control terminal of the second transistor, and a second terminal of which is coupled to the divided voltage output terminal; and
the second resistor is coupled between the divided voltage output end and the second power supply rail line.
3. The ESD protection circuit of claim 2, wherein the second resistor is formed by a well of the first conductivity type.
4. The ESD protection circuit of claim 3, wherein the well region is disposed in a substrate having the second conductivity type, the well region has a first doped region and a second doped region therein, and the second resistor is formed between the first doped region and the second doped region.
5. The ESD protection circuit of claim 4, wherein the first doped region is coupled to a bulk of the second transistor, and the second doped region is coupled to the second power rail.
6. The ESD protection circuit of claim 5, wherein the body has a third doped region therein, the third doped region coupled to the second power rail, the third doped region and the first doped region forming the first diode.
7. The esd protection circuit of claim 1, further comprising:
and the second diode is coupled between the block of the second transistor and the divided voltage output end.
8. The ESD protection circuit of claim 1, wherein the first transistor is a bipolar transistor and the second transistor is a MOSFET.
9. The ESD protection circuit of claim 1, wherein when a negative pulse voltage occurs between the first power rail and the second power rail, the negative pulse voltage passes through the first diode to turn on the first transistor, and provides a current drain path for ESD protection by turning on the first transistor.
10. The ESD protection circuit of claim 1 wherein when a positive pulse voltage occurs between the first power rail and the second power rail, the capacitor and the voltage divider generate a bias voltage at the voltage divider output according to the positive pulse voltage, and turn on the first transistor according to the bias voltage, and provide a current leakage path for ESD protection by turning on the first transistor.
CN202110542166.6A 2021-05-18 2021-05-18 Electrostatic discharge protection circuit Pending CN115377956A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110542166.6A CN115377956A (en) 2021-05-18 2021-05-18 Electrostatic discharge protection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110542166.6A CN115377956A (en) 2021-05-18 2021-05-18 Electrostatic discharge protection circuit

Publications (1)

Publication Number Publication Date
CN115377956A true CN115377956A (en) 2022-11-22

Family

ID=84058446

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110542166.6A Pending CN115377956A (en) 2021-05-18 2021-05-18 Electrostatic discharge protection circuit

Country Status (1)

Country Link
CN (1) CN115377956A (en)

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