CN115377642A - High-precision linear nine-bit delayer based on MEMS switch - Google Patents
High-precision linear nine-bit delayer based on MEMS switch Download PDFInfo
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Abstract
The invention belongs to the technical field of radio frequency MEMS, and particularly relates to a high-precision linear nine-bit delayer based on an MEMS switch. The invention can have a wide-range delay amount on the premise of not increasing the size of the delayer through the control of each sub-unit, and can realize the delay range of 0-317 ps through the control of the MEMS switch on the microwave signal passing path.
Description
Technical Field
The invention belongs to the technical field of radio frequency MEMS, and particularly relates to a high-precision linear nine-bit delayer based on an MEMS switch.
Background
The radio frequency MEMS delayer is one of basic components of a radio frequency system, transmits or isolates microwave signals through a capacitor formed by metal-metal contact or metal-insulating medium-metal, has good microwave performance such as low insertion loss, good time delay performance and the like, can be widely applied to various radio frequency, microwave and millimeter wave communication systems, and has important significance for military fields such as radar early warning, tactical strategy reconnaissance, satellite networking, guidance and the like.
Most of the commonly used current time delayers are formed by hybrid integration, and a time delay unit is realized by a cable, so that the time delayer has the defects of large volume, low integration level, difficult control of product consistency and great performance change at high and low temperature and is difficult to meet the requirements of future products.
Disclosure of Invention
Aiming at the technical problems that the conventional commonly used delayer is large in size, low in integration level, difficult to control product consistency and large in performance change at high and low temperatures, and the requirement of future products is difficult to meet, the invention provides the high-precision linear nine-bit delayer based on the MEMS switch, which is low in transmission loss, high in integration level and small in occupied area of the switch.
In order to solve the technical problems, the technical scheme adopted by the invention is as follows:
the utility model provides a nine time delay units of high accuracy linearity based on MEMS switch, includes switch line type time delay unit, substrate, switch line type time delay unit is provided with nine, nine switch line type time delay unit cascades mutually, nine switch line type time delay unit all set up on the substrate, switch line type time delay unit includes input signal line, output signal line, first merit divides the ware, first MEMS switch, second MEMS switch, time delay reference transmission line, delay line, third MEMS switch, fourth MEMS switch, second merit divide the ware, the end of input signal line is equipped with first merit and divides the ware, the horizontal end of first merit divides the ware to connect input signal line, the upper end of first merit divides the ware to be connected with first MEMS switch, the lower extreme of merit divides the ware to connect on the second MEMS switch, first MEMS switch is connected in the one end of time delay reference transmission line, the one end of second MEMS switch is connected in the time delay line, the other end of time delay reference transmission line is connected with the third MEMS switch, the other end of time delay reference switch is connected in the fourth switch, the upper end of second merit divides the ware to be connected with the second MEMS switch, the output of second MEMS switch is connected with the second merit division signal line.
The two sides of the input signal line are respectively provided with a first ground wire and a second ground wire, the two sides of the output signal line are respectively provided with a third ground wire and a fourth ground wire, one side of the delay reference transmission line is provided with a fifth ground wire, one side of the delay line is provided with a sixth ground wire, and an eighth ground wire is arranged between the first power divider and the second power divider.
The power divider is characterized in that a first air bridge is erected at the upper end of the first power divider, two ends of the first air bridge are connected to a first ground wire and an eighth ground wire respectively, a second air bridge is erected at the lower end of the first power divider, two ends of the second air bridge are connected to a second ground wire and an eighth ground wire respectively, a third air bridge is erected at the upper end of the second power divider, two ends of the third air bridge are connected to a third ground wire and an eighth ground wire respectively, a fourth air bridge is erected at the lower end of the second power divider, two ends of the fourth air bridge are connected to a fourth ground wire and an eighth ground wire respectively, and a fifth air bridge is connected between the third air bridge and the fourth air bridge.
The first MEMS switch, the second MEMS switch, the third MEMS switch and the fourth MEMS switch respectively comprise an MEMS switch upper electrode, an MEMS switch lower electrode, an MEMS switch contact and an MEMS switch anchor point, one end of the MEMS switch upper electrode is fixedly connected to the MEMS switch anchor point, the other end of the MEMS switch upper electrode is arranged right above the MEMS switch contact, and the MEMS switch lower electrode is arranged right below the MEMS switch upper electrode.
The MEMS switch anchor point of the first MEMS switch is fixed at the upper end of the first power divider, the MEMS switch contact of the first MEMS switch is fixed at one end of a delay reference transmission line, the MEMS switch anchor point of the second MEMS switch is fixed at the lower end of the power divider, the MEMS switch contact of the second MEMS switch is fixed at one end of the delay line, the MEMS switch anchor point of the third MEMS switch is fixed at the upper end of the second power divider, the MEMS switch contact of the third MEMS switch is fixed at the other end of the delay reference transmission line, the MEMS switch anchor point of the fourth MEMS switch is fixed at the lower end of the second power divider, and the MEMS switch contact of the fourth MEMS switch is fixed at the other end of the delay line; the MEMS switch lower electrodes of the first MEMS switch and the third MEMS switch are electrically connected with a first driving electrode through leads, and the MEMS switch lower electrodes of the second MEMS switch and the fourth MEMS switch are electrically connected with a second driving electrode through leads.
The first power divider and the second power divider adopt arc corners, and the substrate adopts a silicon dioxide substrate.
And sixth air bridges are erected on two sides of the first MEMS switch, the second MEMS switch, the third MEMS switch and the fourth MEMS switch, and thickening anchor points are arranged on the sixth air bridges.
The nine switch line type delayer units are respectively an eighth switch line type delayer unit, a first switch line type delayer unit, a second switch line type delayer unit, a fifth switch line type delayer unit, a third switch line type delayer unit, a seventh switch line type delayer unit, a sixth switch line type delayer unit, a fourth switch line type delayer unit and a ninth switch line type delayer unit, the delay line and the delay reference transmission line of the eighth switch line type delayer unit are respectively an eighth delay line and an eighth delay reference transmission line, the delay line and the delay reference transmission line of the first switch line type delayer unit are respectively a first delay line and a first delay reference transmission line, the delay line and the delay reference transmission line of the second switch line type delayer unit are respectively a second delay line and a second delay reference transmission line, the delay line and the delay reference transmission line of the fifth switch linear delayer unit are respectively a fifth delay line and a fifth delay reference transmission line, the delay line and the delay reference transmission line of the third switch linear delayer unit are respectively a third delay line and a third delay reference transmission line, the delay line and the delay reference transmission line of the seventh switch linear delayer unit are respectively a seventh delay line and a seventh delay reference transmission line, the delay line and the delay reference transmission line of the sixth switch linear delayer unit are respectively a sixth delay line and a sixth delay reference transmission line, the delay line and the delay reference transmission line of the fourth switch linear delayer unit are respectively a fourth delay line and a fourth delay reference transmission line, and the delay line and the delay reference transmission line of the ninth switch linear delayer unit are respectively a ninth delay line, and a ninth bit delayed reference transmission line.
The delay amount of the eighth bit switch line type time delay unit is 154.88ps, the delay amount of the first bit switch line type time delay unit is 1.21ps, the delay amount of the second bit switch line type time delay unit is 2.42ps, the delay amount of the fifth bit switch line type time delay unit is 19.36ps, the delay amount of the third bit switch line type time delay unit is 4.84ps, the delay amount of the seventh bit switch line type time delay unit is 77.44ps, the delay amount of the sixth bit switch line type time delay unit is 38.76ps, the delay amount of the fourth bit switch line type time delay unit is 9.68ps, and the delay amount of the ninth bit switch line type time delay unit is 309.76ps.
A control method of a high-precision linear nine-bit delayer based on an MEMS switch is characterized in that when an eighth delay reference transmission line, a first delay line, a second delay reference transmission line, a fifth delay reference transmission line, a third delay reference transmission line, a seventh delay reference transmission line, a sixth delay reference transmission line, a fourth delay reference transmission line and a ninth delay reference transmission line are switched on, the eighth delay line, the first delay reference transmission line, the second delay line, the fifth delay line, the third delay line, the seventh delay line, the sixth delay line, the fourth delay line and the ninth delay line are switched off, so that 1.21ps delay is realized;
when the eighth time delay reference transmission line, the first time delay reference transmission line, the second time delay line, the fifth time delay reference transmission line, the third time delay reference transmission line, the seventh time delay reference transmission line, the sixth time delay reference transmission line, the fourth time delay reference transmission line and the ninth time delay reference transmission line are switched on, the eighth time delay line, the first time delay line, the second time delay reference transmission line, the fifth time delay line, the third time delay line, the seventh time delay line, the sixth time delay line, the fourth time delay line and the ninth time delay line are switched off, the 2.42ps time delay is realized;
when the eighth time delay reference transmission line, the first time delay reference transmission line, the second time delay reference transmission line, the fifth time delay reference transmission line, the third time delay line, the seventh time delay reference transmission line, the sixth time delay reference transmission line, the fourth time delay reference transmission line and the ninth time delay reference transmission line are switched on, the eighth time delay line, the first time delay line, the second time delay line, the fifth time delay line, the third time delay reference transmission line, the seventh time delay line, the sixth time delay line, the fourth time delay line and the ninth time delay line are switched off, so that the 4.84ps time delay is realized;
when the eighth time delay reference transmission line, the first time delay reference transmission line, the second time delay reference transmission line, the fifth time delay reference transmission line, the third time delay reference transmission line, the seventh time delay reference transmission line, the sixth time delay reference transmission line, the fourth time delay line and the ninth time delay reference transmission line are switched on, the eighth time delay line, the first time delay line, the second time delay line, the fifth time delay line, the third time delay line, the seventh time delay line, the sixth time delay line, the fourth time delay reference transmission line and the ninth time delay line are switched off, so that 9.68ps time delay is realized;
when the eighth bit delay reference transmission line, the first bit delay reference transmission line, the second bit delay reference transmission line, the fifth bit delay line, the third bit delay reference transmission line, the seventh bit delay reference transmission line, the sixth bit delay reference transmission line, the fourth bit delay reference transmission line and the ninth bit delay reference transmission line are switched on, the eighth bit delay line, the first bit delay line, the second bit delay line, the fifth bit delay reference transmission line, the third bit delay line, the seventh bit delay line, the sixth bit delay line, the fourth bit delay line and the ninth bit delay line are switched off, the 19.36ps delay amount is realized;
when the eighth time delay reference transmission line, the first time delay reference transmission line, the second time delay reference transmission line, the fifth time delay reference transmission line, the third time delay reference transmission line, the seventh time delay reference transmission line, the sixth time delay line, the fourth time delay reference transmission line and the ninth time delay reference transmission line are switched on, the eighth time delay line, the first time delay line, the second time delay line, the fifth time delay line, the third time delay line, the seventh time delay line, the sixth time delay reference transmission line, the fourth time delay line and the ninth time delay line are switched off, the 38.72ps time delay is realized;
when the eighth time delay reference transmission line, the first time delay reference transmission line, the second time delay reference transmission line, the fifth time delay reference transmission line, the third time delay reference transmission line, the seventh time delay line, the sixth time delay reference transmission line, the fourth time delay reference transmission line and the ninth time delay reference transmission line are switched on, the eighth time delay line, the first time delay line, the second time delay line, the fifth time delay line, the third time delay line, the seventh time delay reference transmission line, the sixth time delay line, the fourth time delay line and the ninth time delay line are switched off, the 77.44ps time delay is realized;
when the eighth bit delay line, the first bit delay reference transmission line, the second bit delay reference transmission line, the fifth bit delay reference transmission line, the third bit delay reference transmission line, the seventh bit delay reference transmission line, the sixth bit delay reference transmission line, the fourth bit delay reference transmission line and the ninth bit delay reference transmission line are switched on, the eighth bit delay reference transmission line, the first bit delay line, the second bit delay line, the fifth bit delay line, the third bit delay line, the seventh bit delay line, the sixth bit delay line, the fourth bit delay line and the ninth bit delay line are switched off, 154.88ps delay amount is realized;
when the eighth time delay reference transmission line, the first time delay reference transmission line, the second time delay reference transmission line, the fifth time delay reference transmission line, the third time delay reference transmission line, the seventh time delay reference transmission line, the sixth time delay reference transmission line, the fourth time delay reference transmission line and the ninth time delay line are switched on, the eighth time delay line, the first time delay line, the second time delay line, the fifth time delay line, the third time delay line, the seventh time delay line, the sixth time delay line, the fourth time delay line and the ninth time delay reference transmission line are switched off, the 309.76ps time delay is realized.
Compared with the prior art, the invention has the following beneficial effects:
the invention can have a wide-range delay amount on the premise of not increasing the size of the delayer through the control of each sub-unit, and can realize the delay range of 0-317 ps through the control of the MEMS switch on the microwave signal passing path. In addition, the whole transmission line of the invention adopts a coplanar waveguide structure, avoids a complex through hole process, selects a series contact type MEMS switch, minimizes the occupied area of the MEMS switch, adopts fillets at the corners of the power divider and the transmission line, and effectively reduces the signal transmission loss.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below. It should be apparent that the drawings in the following description are merely exemplary and that other implementation drawings may be derived from the drawings provided to one of ordinary skill in the art without inventive effort.
The structures, ratios, sizes, and the like shown in the present specification are only used for matching with the contents disclosed in the specification, so that those skilled in the art will understand and read the present invention, and do not limit the conditions for implementing the present invention, so that the present invention has no technical essence, and any modifications of the structures, changes of the ratio relationships, or adjustments of the sizes, should still fall within the scope covered by the technical contents disclosed in the present invention without affecting the efficacy and the achievable purpose of the present invention.
FIG. 1 is a general schematic diagram of nine switch line type delay units according to the present invention;
FIG. 2 is a schematic diagram of a switch line type delay unit according to the present invention;
FIG. 3 is a schematic diagram of a MEMS switch of the present invention;
fig. 4 is a schematic diagram of a cascade structure of nine switch line type delayer units according to the present invention.
Wherein: 1 is a substrate, 2 is an input signal line, 3 is an output signal line, 4 is a first power divider, 5 is a first MEMS switch, 6 is a second MEMS switch, 7 is a delay reference transmission line, 8 is a delay line, 9 is a third MEMS switch, 10 is a fourth MEMS switch, 11 is a second power divider, 12 is a first ground, 13 is a second ground, 14 is a third ground, 15 is a fourth ground, 16 is a fifth ground, 17 is a sixth ground, 19 is an eighth ground, 21 is a first air bridge, 22 is a second air bridge, 23 is a third air bridge, 24 is a fourth air bridge, 25 is a fifth air bridge, 501 is an MEMS switch upper electrode, 502 is an MEMS switch lower electrode, 503 is an MEMS switch contact, 504 is an MEMS switch anchor, 505 is a sixth air bridge, a is an eighth switch linear delayer unit, B is a first bit switch linear delayer unit, C is a second bit switch line type delayer unit, D is a fifth bit switch line type delayer unit, E is a third bit switch line type delayer unit, F is a seventh bit switch line type delayer unit, G is a sixth bit switch line type delayer unit, H is a fourth bit switch line type delayer unit, I is a ninth bit switch line type delayer unit, A-1 is an eighth bit delay line, A-2 is an eighth bit delay reference transmission line, B-1 is a first bit delay line, B-2 is a first bit delay reference transmission line, C-1 is a second bit delay line, C-2 is a second bit delay reference transmission line, D-1 is a fifth bit delay line, D-2 is a fifth bit delay reference transmission line, E-1 is a third bit delay line, E-2 is a third bit delay reference transmission line, F-1 is a seventh bit delay line, f-2 is a seventh bit delay reference transmission line, G-1 is a sixth bit delay line, G-2 is a sixth bit delay reference transmission line, H-1 is a fourth bit delay line, H-2 is a fourth bit delay reference transmission line, I-1 is a ninth bit delay line, and I-2 is a ninth bit delay reference transmission line.
Detailed Description
To make the objects, technical solutions and advantages of the embodiments of the present invention clearer and more complete, the technical solutions in the embodiments of the present invention will be described below, obviously, the described embodiments are only a part of the embodiments of the present application, but not all embodiments, and the description is only for further explaining the features and advantages of the present invention, and not for limiting the claims of the present invention; all other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The following detailed description of embodiments of the present invention is provided in connection with the accompanying drawings and examples. The following examples are intended to illustrate the invention, but are not intended to limit the scope of the invention.
The terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, the meaning of "a plurality" is two or more unless otherwise specified.
In the description of the present application, it should be noted that unless otherwise explicitly stated or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In this embodiment, as shown in fig. 1-2, the delay line 8 and the delay reference transmission line 7 form two paths for signal transmission, and the first driving electrode 505 and the second driving electrode 506 are applied with driving voltages to respectively control the on/off of the first MEMS switch 5, the second MEMS switch 6, the third MEMS switch 9, and the fourth MEMS switch 10, so that a microwave signal passes through one of the transmission paths selected by the first power divider 4, the second power divider 11, and the MEMS switch, and the switch line type delay unit is disposed on the dielectric substrate 1, thereby implementing different delay ranges.
Further, preferably, the corners of the delay reference transmission line 7 and the delay line 8 both adopt arc corners to reduce the loss of signals in the transmission process through the quarter bend. The first power divider 4 and the second power divider 11 adopt arc corners, so that the loss in the signal transmission process is reduced. The substrate 1 is preferably a silicon dioxide substrate.
Furthermore, sixth air bridges 26 are erected on two sides of the first MEMS switch 5, the second MEMS switch 6, the third MEMS switch 9 and the fourth MEMS switch 10, and thickened anchor points are arranged on the sixth air bridges 26 and used for inhibiting a high-order mode generated by the asymmetry of the coplanar waveguide ground wires.
Further, as shown in fig. 3, when a voltage is applied to the MEMS switch lower electrode 502, the MEMS switch upper electrode 501 is pulled down by an electrostatic force to contact with the MEMS switch contact 503, so that the branch where the switch is located is turned on.
As shown in fig. 4, the delay amount of the eighth bit switch linear type delayer unit a is 154.88ps, the delay amount of the first bit switch linear type delayer unit B is 1.21ps, the delay amount of the second bit switch linear type delayer unit C is 2.42ps, the delay amount of the fifth bit switch linear type delayer unit D is 19.36ps, the delay amount of the third bit switch linear type delayer unit E is 4.84ps, the delay amount of the seventh bit switch linear type delayer unit F is 77.44ps, the delay amount of the sixth bit switch linear type delayer unit G is 38.76ps, the delay amount of the fourth bit switch linear type delayer unit H is 9.68ps, and the delay amount of the ninth bit switch linear type delayer unit I is 309.76ps, so as to form a high-precision linear nine-bit delayer based on the MEMS switch, and the delay range of 0 to 317ps can be realized by controlling the microwave signal passing path through the MEMS switch.
The specific method for realizing the delay range of 0 to 317ps in this embodiment is as follows:
(1) when the eighth time delay reference transmission line A-2, the first time delay line B-1, the second time delay reference transmission line C-2, the fifth time delay reference transmission line D-2, the third time delay reference transmission line E-2, the seventh time delay reference transmission line F-2, the sixth time delay reference transmission line G-2, the fourth time delay reference transmission line H-2 and the ninth time delay reference transmission line I-2 are switched on, the eighth time delay line A-1, the first time delay reference transmission line B-2, the second time delay line C-1, the fifth time delay line D-1, the third time delay line E-1, the seventh time delay line F-1, the sixth time delay line G-1, the fourth time delay line H-1 and the ninth time delay line I-1 are switched off, 1.21 time delay can be realized;
(2) when the eighth time delay reference transmission line A-2, the first time delay reference transmission line B-2, the second time delay line C-1, the fifth time delay reference transmission line D-2, the third time delay reference transmission line E-2, the seventh time delay reference transmission line F-2, the sixth time delay reference transmission line G-2, the fourth time delay reference transmission line H-2 and the ninth time delay reference transmission line I-2 are switched on, the eighth time delay line A-1, the first time delay line B-1, the second time delay reference transmission line C-2, the fifth time delay line D-1, the third time delay line E-1, the seventh time delay line F-1, the sixth time delay line G-1, the fourth time delay line H-1 and the ninth time delay line I-1 are switched off, 2.42ps time delay can be realized;
(3) when the eighth time delay reference transmission line A-2, the first time delay reference transmission line B-2, the second time delay reference transmission line C-2, the fifth time delay reference transmission line D-2, the third time delay line E-1, the seventh time delay reference transmission line F-2, the sixth time delay reference transmission line G-2, the fourth time delay reference transmission line H-2 and the ninth time delay reference transmission line I-2 are switched on, the eighth time delay line A-1, the first time delay line B-1, the second time delay line C-1, the fifth time delay line D-1, the third time delay reference transmission line E-2, the seventh time delay line F-1, the sixth time delay line G-1, the fourth time delay line H-1 and the ninth time delay line I-1 are switched off, 4.84 time delay can be realized;
(4) when the eighth time delay reference transmission line A-2, the first time delay reference transmission line B-2, the second time delay reference transmission line C-2, the fifth time delay reference transmission line D-2, the third time delay reference transmission line E-2, the seventh time delay reference transmission line F-2, the sixth time delay reference transmission line G-2, the fourth time delay line H-1 and the ninth time delay reference transmission line I-2 are switched on, the eighth time delay line A-1, the first time delay line B-1, the second time delay line C-1, the fifth time delay line D-1, the third time delay line E-1, the seventh time delay line F-1, the sixth time delay line G-1, the fourth time delay reference transmission line H-2 and the ninth time delay line I-1 are switched off, 9.68ps time delay can be realized;
(5) when the eighth time delay reference transmission line A-2, the first time delay reference transmission line B-2, the second time delay reference transmission line C-2, the fifth time delay line D-1, the third time delay reference transmission line E-2, the seventh time delay reference transmission line F-2, the sixth time delay reference transmission line G-2, the fourth time delay reference transmission line H-2 and the ninth time delay reference transmission line I-2 are switched on, the eighth time delay line A-1, the first time delay line B-1, the second time delay line C-1, the fifth time delay reference transmission line D-2, the third time delay line E-1, the seventh time delay line F-1, the sixth time delay line G-1, the fourth time delay line H-1 and the ninth time delay line I-1 are switched off, the 19.36ps time delay can be realized;
(6) when the eighth time delay reference transmission line A-2, the first time delay reference transmission line B-2, the second time delay reference transmission line C-2, the fifth time delay reference transmission line D-2, the third time delay reference transmission line E-2, the seventh time delay reference transmission line F-2, the sixth time delay line G-1, the fourth time delay reference transmission line H-2 and the ninth time delay reference transmission line I-2 are switched on, the eighth time delay line A-1, the first time delay line B-1, the second time delay line C-1, the fifth time delay line D-1, the third time delay line E-1, the seventh time delay line F-1, the sixth time delay reference transmission line G-2, the fourth time delay line H-1 and the ninth time delay line I-1 are switched off, 38.72ps of time delay can be realized;
(7) when the eighth time delay reference transmission line A-2, the first time delay reference transmission line B-2, the second time delay reference transmission line C-2, the fifth time delay reference transmission line D-2, the third time delay reference transmission line E-2, the seventh time delay line F-1, the sixth time delay reference transmission line G-2, the fourth time delay reference transmission line H-2 and the ninth time delay reference transmission line I-2 are switched on, the eighth time delay line A-1, the first time delay line B-1, the second time delay line C-1, the fifth time delay line D-1, the third time delay line E-1, the seventh time delay reference transmission line F-2, the sixth time delay line G-1, the fourth time delay line H-1 and the ninth time delay line I-1 are switched off, 77.44ps of time delay can be realized;
(8) when the eighth time delay line A-1, the first time delay reference transmission line B-2, the second time delay reference transmission line C-2, the fifth time delay reference transmission line D-2, the third time delay reference transmission line E-2, the seventh time delay reference transmission line F-2, the sixth time delay reference transmission line G-2, the fourth time delay reference transmission line H-2 and the ninth time delay reference transmission line I-2 are switched on, the eighth time delay reference transmission line A-2, the first time delay line B-1, the second time delay line C-1, the fifth time delay line D-1, the third time delay line E-1, the seventh time delay line F-1, the sixth time delay line G-1, the fourth time delay line H-1 and the ninth time delay line I-1 are switched off, 154.88 time delay can be realized;
(9) when the eighth bit delay reference transmission line A-2, the first bit delay reference transmission line B-2, the second bit delay reference transmission line C-2, the fifth bit delay reference transmission line D-2, the third bit delay reference transmission line E-2, the seventh bit delay reference transmission line F-2, the sixth bit delay reference transmission line G-2, the fourth bit delay reference transmission line H-2 and the ninth bit delay line I-1 are switched on, the eighth bit delay line A-1, the first bit delay line B-1, the second bit delay line C-1, the fifth bit delay line D-1, the third bit delay line E-1, the seventh bit delay line F-1, the sixth bit delay line G-1, the fourth bit delay line H-1 and the ninth bit delay reference transmission line I-2 are switched off, 309.76ps delay amount can be realized.
Although only the preferred embodiments of the present invention have been described in detail, the present invention is not limited to the above embodiments, and various changes can be made without departing from the spirit of the present invention within the knowledge of those skilled in the art, and all changes are encompassed in the scope of the present invention.
Claims (10)
1. The utility model provides a nine time delay units of high accuracy linearity based on MEMS switch which characterized in that: the delay circuit comprises nine switch line type delay units and a substrate (1), wherein the nine switch line type delay units are cascaded, the nine switch line type delay units are all arranged on the substrate (1), each switch line type delay unit comprises an input signal line (2), an output signal line (3), a first power divider (4), a first MEMS switch (5), a second MEMS switch (6), a delay reference transmission line (7), a delay line (8), a third MEMS switch (9), a fourth MEMS switch (10) and a second power divider (11), the tail end of the input signal line (2) is provided with the first power divider (4), the horizontal end of the first power divider (4) is connected with the input signal line (2), the upper end of the first power divider (4) is connected with the first MEMS switch (5), the lower end of the power divider (4) is connected with the second MEMS switch (6), the first switch (5) is connected with one end of the delay reference transmission line (7), the other end of the second switch (9) is connected with the third MEMS switch (9), the other end of the delay line (9) is connected with the second power divider (9), and the other end of the second power divider (9) is connected with the second MEMS switch (9), the fourth MEMS switch (10) is connected to the lower end of a second power divider (11), and the horizontal end of the second power divider (11) is connected with an output signal line (3).
2. The MEMS switch based high precision linear nine-bit delayer of claim 1, wherein: the improved power divider is characterized in that a first ground wire (12) and a second ground wire (13) are respectively arranged on two sides of the input signal wire (2), a third ground wire (14) and a fourth ground wire (15) are respectively arranged on two sides of the output signal wire (3), a fifth ground wire (16) is arranged on one side of the delay reference transmission line (7), a sixth ground wire (17) is arranged on one side of the delay line (8), and an eighth ground wire (19) is arranged between the first power divider (4) and the second power divider (11).
3. The MEMS switch-based high precision linear nine-bit delayer of claim 2, wherein: a first air bridge (21) is erected at the upper end of the first power divider (4), two ends of the first air bridge (21) are respectively connected to a first ground wire (12) and an eighth ground wire (19), a second air bridge (22) is erected at the lower end of the first power divider (4), two ends of the second air bridge (22) are respectively connected to a second ground wire (13) and an eighth ground wire (19), a third air bridge (23) is erected at the upper end of the second power divider (11), two ends of the third air bridge (23) are respectively connected to a third ground wire (14) and an eighth ground wire (19), a fourth air bridge (24) is erected at the lower end of the second power divider (11), two ends of the fourth air bridge (24) are respectively connected to a fourth ground wire (15) and an eighth ground wire (19), and a fifth air bridge (25) is connected between the third air bridge (23) and the fourth air bridge (24).
4. The MEMS switch based high precision linear nine-bit delayer of claim 1, wherein: the MEMS switch comprises a first MEMS switch upper electrode (501), a second MEMS switch (6), a third MEMS switch (9) and a fourth MEMS switch (10), wherein the first MEMS switch (5), the second MEMS switch (6), the third MEMS switch (9) and the fourth MEMS switch (10) respectively comprise an MEMS switch upper electrode (501), an MEMS switch lower electrode (502), an MEMS switch contact (503) and an MEMS switch anchor point (504), one end of the MEMS switch upper electrode (501) is fixedly connected to the MEMS switch anchor point (504), the other end of the MEMS switch upper electrode (501) is arranged right above the MEMS switch contact (503), and the MEMS switch lower electrode (502) is arranged right below the MEMS switch upper electrode (501).
5. The MEMS switch-based high-precision linear nine-bit delayer according to claim 4, wherein: an MEMS switch anchor point (504) of the first MEMS switch (5) is fixed at the upper end of the first power divider (4), an MEMS switch contact (503) of the first MEMS switch (5) is fixed at one end of the delay reference transmission line (7), an MEMS switch anchor point (504) of the second MEMS switch (6) is fixed at the lower end of the power divider (4), an MEMS switch contact (503) of the second MEMS switch (6) is fixed at one end of the delay line (8), an MEMS switch anchor point (504) of the third MEMS switch (9) is fixed at the upper end of the second power divider (11), an MEMS switch contact (503) of the third MEMS switch (9) is fixed at the other end of the delay reference transmission line (7), an MEMS switch anchor point (504) of the fourth MEMS switch (10) is fixed at the lower end of the second power divider (11), and an MEMS switch anchor point (503) of the fourth MEMS switch (10) is fixed at the other end of the delay line (8); the MEMS switch lower electrodes (502) of the first MEMS switch (5) and the third MEMS switch (9) are electrically connected with a first driving electrode (505) through leads, and the MEMS switch lower electrodes (502) of the second MEMS switch (6) and the fourth MEMS switch (10) are electrically connected with a second driving electrode (506) through leads.
6. The high-precision linear nine-bit delayer based on the MEMS switch, according to claim 1, characterized in that: the corners of the delay reference transmission line (7) and the delay line (8) are arc corners, the first power divider (4) and the second power divider (11) are arc corners, and the substrate (1) is a silicon dioxide substrate.
7. The MEMS switch based high precision linear nine-bit delayer of claim 1, wherein: sixth air bridges (26) are erected on two sides of the first MEMS switch (5), the second MEMS switch (6), the third MEMS switch (9) and the fourth MEMS switch (10), and thickening anchor points are arranged on the sixth air bridges (26).
8. The high-precision linear nine-bit delayer based on the MEMS switch, according to claim 1, characterized in that: the nine switch linear delayer units are respectively an eighth switch linear delayer unit (A), a first switch linear delayer unit (B), a second switch linear delayer unit (C), a fifth switch linear delayer unit (D), a third switch linear delayer unit (E), a seventh switch linear delayer unit (F), a sixth switch linear delayer unit (G), a fourth switch linear delayer unit (H) and a ninth switch linear delayer unit (I), the delay line (8) and the delay reference transmission line (7) of the eighth switch linear delayer unit (A) are respectively a second delay line (A-1) and an eighth delay reference transmission line (A-2), the delay line (8) and the delay reference transmission line (7) of the first switch linear delayer unit (B) are respectively a first delay line (B-1) and a first delay reference transmission line (B-2), the delay line (8) and the delay reference transmission line (7) of the second switch linear delayer unit (C) are respectively a fifth delay line (C-1) and a fifth delay reference transmission line (C-2), the delay line (8) and the delay reference transmission line (7) of the second switch linear delayer unit (C-1) are respectively a fifth delay reference transmission line (C-1) and a fifth delay line (7) of the second switch linear delayer unit (C-2), and the delay reference line (C-8-7) are respectively, the delay line (8) and the delay reference transmission line (7) of the seventh switching linear delayer unit (F) are respectively a seventh delay line (F-1) and a seventh delay reference transmission line (F-2), the delay line (8) and the delay reference transmission line (7) of the sixth switching linear delayer unit (G) are respectively a sixth delay line (G-1) and a sixth delay reference transmission line (G-2), the delay line (8) and the delay reference transmission line (7) of the fourth switching linear delayer unit (H) are respectively a fourth delay line (H-1) and a fourth delay reference transmission line (H-2), and the delay line (8) and the delay reference transmission line (7) of the ninth switching linear delayer unit (I) are respectively a ninth delay line (I-1) and a ninth delay reference transmission line (I-2).
9. The MEMS switch based high precision linear nine bit delay of claim 8 wherein: the delay amount of the eighth bit switch line type delayer unit (a) is 154.88ps, the delay amount of the first bit switch line type delayer unit (B) is 1.21ps, the delay amount of the second bit switch line type delayer unit (C) is 2.42ps, the delay amount of the fifth bit switch line type delayer unit (D) is 19.36ps, the delay amount of the third bit switch line type delayer unit (E) is 4.84ps, the delay amount of the seventh bit switch line type delayer unit (F) is 77.44ps, the delay amount of the sixth bit switch line type delayer unit (G) is 38.76ps, the delay amount of the fourth bit switch line type delayer unit (H) is 9.68ps, and the delay amount of the ninth bit switch line type delayer unit (I) is 309.76ps.
10. The control method of the high-precision linear nine-bit time delay based on the MEMS switch as claimed in any one of claims 1 to 9, wherein: when the eighth time delay reference transmission line (A-2), the first time delay line (B-1), the second time delay reference transmission line (C-2), the fifth time delay reference transmission line (D-2), the third time delay reference transmission line (E-2), the seventh time delay reference transmission line (F-2), the sixth time delay reference transmission line (G-2), the fourth time delay reference transmission line (H-2) and the ninth time delay reference transmission line (I-2) are switched on, the eighth time delay line (A-1), the first time delay reference transmission line (B-2), the second time delay line (C-1), the fifth time delay line (D-1), the third time delay line (E-1), the seventh time delay line (F-1), the sixth time delay line (G-1), the fourth time delay line (H-1) and the ninth time delay line (I-1) are switched off, 1.21ps of time delay is realized;
when the eighth time delay reference transmission line (A-2), the first time delay reference transmission line (B-2), the second time delay line (C-1), the fifth time delay reference transmission line (D-2), the third time delay reference transmission line (E-2), the seventh time delay reference transmission line (F-2), the sixth time delay reference transmission line (G-2), the fourth time delay reference transmission line (H-2) and the ninth time delay reference transmission line (I-2) are switched on, the eighth time delay line (A-1), the first time delay line (B-1), the second time delay reference transmission line (C-2), the fifth time delay line (D-1), the third time delay line (E-1), the seventh time delay line (F-1), the sixth time delay line (G-1), the fourth time delay line (H-1) and the ninth time delay line (I-1) are switched off, 2.42ps time delay is realized;
when the eighth time delay reference transmission line (A-2), the first time delay reference transmission line (B-2), the second time delay reference transmission line (C-2), the fifth time delay reference transmission line (D-2), the third time delay line (E-1), the seventh time delay reference transmission line (F-2), the sixth time delay reference transmission line (G-2), the fourth time delay reference transmission line (H-2) and the ninth time delay reference transmission line (I-2) are switched on, the eighth time delay line (A-1), the first time delay line (B-1), the second time delay line (C-1), the fifth time delay line (D-1), the third time delay reference transmission line (E-2), the seventh time delay line (F-1), the sixth time delay line (G-1), the fourth time delay line (H-1) and the ninth time delay line (I-1) are switched off, 4.84ps of time delay is realized;
when the eighth time delay reference transmission line (A-2), the first time delay reference transmission line (B-2), the second time delay reference transmission line (C-2), the fifth time delay reference transmission line (D-2), the third time delay reference transmission line (E-2), the seventh time delay reference transmission line (F-2), the sixth time delay reference transmission line (G-2), the fourth time delay line (H-1) and the ninth time delay reference transmission line (I-2) are switched on, the eighth time delay line (A-1), the first time delay line (B-1), the second time delay line (C-1), the fifth time delay line (D-1), the third time delay line (E-1), the seventh time delay line (F-1), the sixth time delay line (G-1), the fourth time delay reference transmission line (H-2) and the ninth time delay line (I-1) are switched off, 9.68ps delay is realized;
when the eighth bit delay reference transmission line (A-2), the first bit delay reference transmission line (B-2), the second bit delay reference transmission line (C-2), the fifth bit delay line (D-1), the third bit delay reference transmission line (E-2), the seventh bit delay reference transmission line (F-2), the sixth bit delay reference transmission line (G-2), the fourth bit delay reference transmission line (H-2) and the ninth bit delay reference transmission line (I-2) are switched on, the eighth bit delay line (A-1), the first bit delay line (B-1), the second bit delay line (C-1), the fifth bit delay reference transmission line (D-2), the third bit delay line (E-1), the seventh bit delay line (F-1), the sixth bit delay line (G-1), the fourth bit delay line (H-1) and the ninth bit delay line (I-1) are switched off, the delay amount of 19.36ps is realized;
when the eighth time delay reference transmission line (A-2), the first time delay reference transmission line (B-2), the second time delay reference transmission line (C-2), the fifth time delay reference transmission line (D-2), the third time delay reference transmission line (E-2), the seventh time delay reference transmission line (F-2), the sixth time delay line (G-1), the fourth time delay reference transmission line (H-2) and the ninth time delay reference transmission line (I-2) are switched on, the eighth time delay line (A-1), the first time delay line (B-1), the second time delay line (C-1), the fifth time delay line (D-1), the third time delay line (E-1), the seventh time delay line (F-1), the sixth time delay reference transmission line (G-2), the fourth time delay line (H-1) and the ninth time delay line (I-1) are switched off, 38.72ps time delay is realized;
when the eighth time delay reference transmission line (A-2), the first time delay reference transmission line (B-2), the second time delay reference transmission line (C-2), the fifth time delay reference transmission line (D-2), the third time delay reference transmission line (E-2), the seventh time delay line (F-1), the sixth time delay reference transmission line (G-2), the fourth time delay reference transmission line (H-2) and the ninth time delay reference transmission line (I-2) are switched on, the eighth time delay line (A-1), the first time delay line (B-1), the second time delay line (C-1), the fifth time delay line (D-1), the third time delay line (E-1), the seventh time delay reference transmission line (F-2), the sixth time delay line (G-1), the fourth time delay line (H-1) and the ninth time delay line (I-1) are switched off, 77.44ps delay is realized;
when the eighth time delay line (A-1), the first time delay reference transmission line (B-2), the second time delay reference transmission line (C-2), the fifth time delay reference transmission line (D-2), the third time delay reference transmission line (E-2), the seventh time delay reference transmission line (F-2), the sixth time delay reference transmission line (G-2), the fourth time delay reference transmission line (H-2) and the ninth time delay reference transmission line (I-2) are switched on, the eighth time delay reference transmission line (A-2), the first time delay line (B-1), the second time delay line (C-1), the fifth time delay line (D-1), the third time delay line (E-1), the seventh time delay line (F-1), the sixth time delay line (G-1), the fourth time delay line (H-1) and the ninth time delay line (I-1) are switched off, 154.88ps time delay is realized;
when the eighth time delay reference transmission line (A-2), the first time delay reference transmission line (B-2), the second time delay reference transmission line (C-2), the fifth time delay reference transmission line (D-2), the third time delay reference transmission line (E-2), the seventh time delay reference transmission line (F-2), the sixth time delay reference transmission line (G-2), the fourth time delay reference transmission line (H-2) and the ninth time delay line (I-1) are turned on, the eighth time delay line (A-1), the first time delay line (B-1), the second time delay line (C-1), the fifth time delay line (D-1), the third time delay line (E-1), the seventh time delay line (F-1), the sixth time delay line (G-1), the fourth time delay line (H-1) and the ninth time delay reference transmission line (I-2) are turned off, 309.76ps time delay is realized.
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