CN115377024A

CN115377024A - Semiconductor packaging structure

Info

Publication number: CN115377024A
Application number: CN202110540842.6A
Authority: CN
Inventors: 方绪南
Original assignee: Advanced Semiconductor Engineering Inc
Current assignee: Advanced Semiconductor Engineering Inc
Priority date: 2021-05-18
Filing date: 2021-05-18
Publication date: 2022-11-22

Abstract

An embodiment of the present invention provides a semiconductor package structure, including: the first chip is located in the accommodating space of the heat dissipation structure, the substrate is located below the heat dissipation structure, the heat dissipation pipe and the first section of the heat dissipation pipe penetrate through the substrate and the heat dissipation structure, and the end portion of the first section is located in the accommodating space and does not contact with the first chip. The present invention is directed to a semiconductor package structure, so as to enhance the heat dissipation performance of the semiconductor package structure.

Description

Semiconductor packaging structure

Technical Field

Embodiments of the invention relate to semiconductor package structures.

Background

Currently in a two-sided molded structure, the problem of backside component heat dissipation has not been effectively addressed, and existing backside component heat dissipation generally employs two approaches: firstly, a heat dissipation material (TIM) is filled between the back surface of the chip and a Printed Circuit Board (PCB), and if the heat dissipation material seeps in a subsequent pressing process, a circuit is short-circuited because the heat dissipation material has a conductive property; the other is to perform molding process on the back surface, the back surface of the molding compound is completely encapsulated and covered, and the heat energy is guided to the upper part or the periphery, but the heat dissipation efficiency is poorer than that of a heat dissipation material, and the heat energy cannot be effectively guided downwards because the heat dissipation material is isolated from the printed circuit board by air.

If the antenna (AoP) structure is used in a package-on-package structure, the antenna signal conducting area is located above the molding compound, which makes it impossible to place any heat sink, and thus makes heat dissipation more difficult.

Disclosure of Invention

In view of the problems in the related art, an object of the present invention is to provide a semiconductor package structure to enhance the heat dissipation performance of the semiconductor package structure.

To achieve the above object, an embodiment of the present invention provides a semiconductor package structure, including: the first chip is located in the accommodating space of the heat dissipation structure, the substrate is located below the heat dissipation structure, the heat dissipation tube and a first section of the heat dissipation tube penetrate through the substrate and the heat dissipation structure, and the end portion of the first section is located in the accommodating space and does not contact with the first chip.

In some embodiments, the first chip and the heat dissipation structure are both disposed on the first surface of the redistribution layer.

In some embodiments, the heat dissipation structure and the redistribution layer enclose an accommodating space.

In some embodiments, the first chip is not in contact with the heat dissipation structure.

In some embodiments, the heat dissipation structure is formed as a cover surrounding the first chip.

In some embodiments, further comprising: and the second chip is arranged on the second surface of the redistribution layer, the second surface is arranged opposite to the first surface, and the second chip is an antenna element or a sensor element.

In some embodiments, the heat dissipation structure is connected to the redistribution layer through solder balls.

In some embodiments, further comprising: and the adhesive is contacted with the heat dissipation structure, the redistribution layer and part of the surface of the solder ball.

In some embodiments, the pads of the redistribution layer are exposed to the accommodating space.

In some embodiments, the die backside of the first die faces the heat spreading structure upper surface.

In some embodiments, the heat dissipating structure and the base plate have a first insulating material and a second insulating material, respectively, surrounding the heat dissipating tube.

In some embodiments, the first insulating material and the second insulating material comprise different materials.

In some embodiments, further comprising: and the heat dissipation material is positioned on the substrate, contacts the substrate and surrounds the heat dissipation pipe.

In some embodiments, the first section of the radiating pipe extends perpendicular to the base plate, and the second section of the radiating pipe extends parallel to the base plate.

In some embodiments, the heat dissipating material surrounds portions of the first and second sections of the heat dissipating tube and the bend formed by the first and second sections.

In some embodiments, further comprising: and the packaging material is used for coating the side wall of the heat dissipation structure.

In some embodiments, the number of radiating pipes is at least 2.

In some embodiments, the cold fluid flows into the accommodating space from the first heat dissipation tube and flows out of the accommodating space from the second heat dissipation tube.

In some embodiments, the cold fluid contacts the first chip.

In some embodiments, the cold fluid is gas or deionized water.

Drawings

Various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or decreased for clarity of discussion.

Fig. 1 to 12 are cross-sectional views illustrating a process of forming a semiconductor package structure of the present application.

Fig. 13 illustrates an intermediate process of forming a semiconductor package structure according to some embodiments of the present application.

Detailed Description

In order to better understand the spirit of the embodiments of the present application, the following further description is given in conjunction with some preferred embodiments of the present application.

Embodiments of the present application will be described in detail below. Throughout the specification, the same or similar components and components having the same or similar functions are denoted by like reference numerals. The embodiments described herein with respect to the figures are illustrative in nature, are diagrammatic in nature, and are used to provide a basic understanding of the present application. The embodiments of the present application should not be construed as limiting the present application.

As used herein, the terms "substantially", "substantially" and "about" are used to describe and illustrate minor variations. When used in conjunction with an event or circumstance, the terms can refer to both an instance in which the event or circumstance occurs precisely as well as an instance in which the event or circumstance occurs in close proximity. For example, when used in conjunction with numerical values, the term can refer to a range of variation that is less than or equal to ± 10% of the stated numerical value, such as less than or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± 3%, less than or equal to ± 2%, less than or equal to ± 1%, less than or equal to ± 0.5%, less than or equal to ± 0.1%, or less than or equal to ± 0.05%. For example, two numerical values are considered to be "substantially" the same if the difference between the two numerical values is less than or equal to ± 10% (e.g., less than or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± 3%, less than or equal to ± 2%, less than or equal to ± 1%, less than or equal to ± 0.5%, less than or equal to ± 0.1%, or less than or equal to ± 0.05%) of the mean of the values.

In this specification, unless specified or limited otherwise, relative terms such as: the words "central," "longitudinal," "lateral," "front," "rear," "right," "left," "inner," "outer," "lower," "upper," "horizontal," "vertical," "above," "below," "top," "bottom," and derivatives thereof (e.g., "horizontally," "downwardly," "upwardly," etc.) should be construed to refer to the orientation as then described in the discussion or as shown in the drawing. These relative terms are for convenience of description only and do not require that the present application be constructed or operated in a particular orientation.

Additionally, amounts, ratios, and other numerical values are sometimes presented herein in a range format. It is to be understood that such range format is used for convenience and brevity, and it is to be flexibly understood to include not only the values explicitly specified as the limits of the range, but also all the individual values or sub-ranges encompassed within that range as if each value and sub-range is explicitly specified.

Moreover, for convenience in description, "first," "second," "third," etc. may be used herein to distinguish between different elements of a figure or series of figures. "first," "second," "third," etc. are not intended to describe corresponding components.

The semiconductor package structure and the formation process thereof according to the present application will be described in detail with reference to the accompanying drawings.

Referring to fig. 1, a carrier 10 is provided.

Referring to fig. 2, a release layer 20 is disposed on the carrier 10.

Referring to fig. 3, a rewiring layer 30 and support posts 32 are provided on the release layer 20, and in an embodiment, the support posts 32 are electrically connected to the rewiring layer 30.

Referring to fig. 4, a first chip 40 electrically connected to the redistribution layer 30 is formed on the redistribution layer 30.

Referring to fig. 5, an underfill material 50 is disposed between the first chip 40 and the redistribution layer 30.

Referring to fig. 6, a heat dissipation structure 60 surrounding the first chip 40 is disposed on the redistribution layer 30, the heat dissipation structure 60 is connected to the redistribution layer 30 through solder balls 62, and the heat dissipation structure 60 has a first insulating material 64 (e.g., rubber). The first chip 40 is located in the accommodating space 66 surrounded by the heat dissipation structure 60 and the redistribution layer 30. The first chip 40 and the heat dissipation structure 60 are both disposed on the first surface of the redistribution layer 30, i.e., on the same side of the redistribution layer 30. In some embodiments, the first chip 40 is not in contact with the heat dissipation structure 60. In some embodiments, the heat dissipation structure 60 is formed as a cover around the first chip 40. In some embodiments, the pads of the redistribution layer 30 are exposed to the accommodating space 66. In some embodiments, the die backside of the first chip 40 faces the surface of the heat dissipation structure 60. In some embodiments, the heat dissipation structure 60 includes a metal material having a higher hardness than an existing Epoxy Molding Compound (EMC) material, and can maintain structural stability in a subsequent process.

Referring to fig. 7, an adhesive 70 is provided, the adhesive 70 contacting portions of the surfaces of the heat dissipation structure 60, the redistribution layer 30, and the solder balls 62. The adhesive glue 70 is used for adhesion, and because the adhesive glue 70 has elasticity, cracks or fractures of the product can be avoided during thermal cycling, so that the tightness of the accommodating space 66 can be maintained, and water vapor or moisture can be relieved from entering the accommodating space 66.

Referring to fig. 8, an encapsulation material 80 is disposed, wherein the encapsulation material 80 covers the sidewalls of the heat dissipation structure 60 and encapsulates the support posts 32.

Referring to fig. 9, the carrier 10 and the release layer 20 are removed.

Referring to fig. 10, the structure is inverted and first connections 100, in an embodiment, the first connections 100 are solder balls, are provided to the conductive pillars 32.

Referring to fig. 11, the first connector 100 is connected to a substrate 110, and in an embodiment, the substrate 110 is a printed circuit board. The substrate 110 has a second insulating material 112 (e.g., rubber). By providing the first connection member 100, the distance between the heat dissipation structure 60 and the substrate 110 can be precisely controlled. The supporting posts 32 are electrically connected to the substrate 110 through the first connectors 100, which facilitates the signal derivation.

Referring to fig. 12, the first and second radiating

pipes

121 and 122 passing through the first and second

insulating materials

64 and 112 are provided, the first section 1211 of the first radiating pipe 121 passes through the substrate 110 and the radiating structure 60, and the end 1213 of the first section 1211 is located in the receiving space 66 and does not contact the first chip 40. In some embodiments, the first section 1211 of the first heat dissipation tube 121 extends perpendicular to the substrate 110, and the second section 1212 of the first heat dissipation tube 121 extends parallel to the substrate 110. The first and second

insulating materials

64 and 112 surround the first and second radiating

pipes

121 and 122. In some embodiments, the first insulating material 64 and the second insulating material 112 comprise different materials. In some embodiments, further comprising: and a heat dissipating material 124 disposed on the substrate 110, wherein the heat dissipating material 124 contacts the substrate 110 and surrounds the first heat dissipating tube 121 and the second heat dissipating tube 122. In some embodiments, the heat dissipating material 124 surrounds the first heat dissipating tubePortions of the first and

second segments

1211, 1212, and a bend formed by the first and

second segments

1211, 1212. The heat dissipating material 124 contacts the substrate 110, the heat dissipating material reinforces the fixing of the first heat dissipating tube 121 and the second heat dissipating tube 122 against rotation or displacement, and the heat dissipating material 124 transfers heat with the fluid in the first heat dissipating tube 121 and the second heat dissipating tube 122, so that the fluid in the first heat dissipating tube 121 and the second heat dissipating tube 122 dissipates heat more quickly. In some embodiments, the cold fluid flows into the receiving space 66 from the first heat dissipating tube 121 and flows out of the receiving space 66 from the second heat dissipating tube 122. In some embodiments, the cold fluid contacts the first chip 40. In some embodiments, the cooling fluid is a gas or deionized water having a resistance value of less than about 10 ^-10 The ohm does not generate the electrical short circuit problem to the exposed pad of the redistribution layer 30. In some embodiments, the cold fluid flowing into the receiving space 66 can be shared with the cold fluid of the system (e.g., air-cooled/liquid-cooled calculator) for better heat dissipation. The first heat pipe 121 and the second heat pipe 122 of the present application do not contact the first chip 40, so that the first heat pipe 121 and the second heat pipe 122 of the present application can perform large-area heat dissipation on the body of the first chip 40 after the cold fluid is introduced. To this end, a semiconductor package structure 1200 of an embodiment of the present application is formed.

Referring to fig. 12, in some embodiments, further comprising: and a second chip 130 disposed on a second surface of the redistribution layer 30, the second surface being opposite to the first surface, the second chip 130 being an antenna element or a sensor element.

Referring to fig. 13, in some embodiments, the preset screw 140 is disposed in the heat dissipating structure 60, and the preset screw 140 is removed before the substrate 110 is disposed, and after the substrate 110 is disposed, the first heat dissipating tube 121 and the second heat dissipating tube 122 (with threads on the surface) are screwed in to complete sealing. In some embodiments, the preset screw 140 is disposed on the heat dissipating structure 60, the preset screw 140 is removed before the substrate 110 is disposed, the first insulating material 64 is filled after the substrate 110 is disposed, and the first heat dissipating tube 121 and the second heat dissipating tube 122 are inserted to complete sealing.

The semiconductor packaging structure is provided with the accommodating space into which cold fluid can flow, the heat dissipation path of the heating element is increased, gas/liquid can be used for heat dissipation, and the heat dissipation efficiency is improved.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A semiconductor package structure, comprising:

a first chip located in the accommodating space of the heat dissipation structure,

a substrate located below the heat dissipation structure,

the radiating pipe, the first section of radiating pipe runs through the base plate with heat radiation structure, the tip of first section is located in the accommodation space and contactless first chip.

2. The semiconductor package structure of claim 2, wherein the first chip and the heat dissipation structure are both disposed on a first surface of a redistribution layer.

3. The semiconductor package structure of claim 2, wherein the heat dissipation structure and the redistribution layer enclose the accommodating space.

4. The semiconductor package structure of claim 3, wherein the heat dissipation structure is formed as a cover around the first chip.

5. The semiconductor package structure of claim 2, further comprising:

and the second chip is arranged on a second surface of the redistribution layer, the second surface is opposite to the first surface, and the second chip is an antenna element or a sensor element.

6. The semiconductor package structure of claim 2, further comprising:

and the adhesive glue is in contact with the heat dissipation structure and part of the surface of the redistribution layer.

7. The semiconductor package structure of claim 1, wherein the heat dissipation structure and the substrate have a first insulating material and a second insulating material surrounding the heat dissipation tube, respectively.

8. The semiconductor packaging material of claim 7, wherein the first insulating material and the second insulating material comprise different materials.

9. The semiconductor package structure of claim 1, further comprising:

a heat dissipating material on the substrate, the heat dissipating material contacting the substrate and surrounding the heat dissipating tube.

10. The semiconductor package according to claim 9, wherein the first section of the heat pipe extends perpendicular to the substrate and the second section of the heat pipe extends parallel to the substrate.