CN115377017A

CN115377017A - Chip, wafer, equipment with CoWOS packaging structure and generation method thereof

Info

Publication number: CN115377017A
Application number: CN202110536444.7A
Authority: CN
Inventors: 不公告发明人
Original assignee: Cambricon Technologies Corp Ltd
Current assignee: Cambricon Technologies Corp Ltd
Priority date: 2021-05-17
Filing date: 2021-05-17
Publication date: 2022-11-22
Also published as: WO2022242333A1; TW202247028A

Abstract

The present disclosure provides a chip, a wafer, a device, a board card with a CoWoS package structure and a method for generating the chip, wherein the chip of the present disclosure includes a plurality of chips and a plurality of interposer units, the plurality of interposer units are spliced according to a planar layout of the plurality of chips to form an interposer, and the plurality of chips are electrically interconnected through the interposer.

Description

Chip, wafer, equipment with CoWOS packaging structure and generation method thereof

Technical Field

The present disclosure relates generally to semiconductors. More particularly, the present disclosure relates to chips, wafers, devices, cards with CoWoS packaging structures and methods of generating chips thereof.

Background

CoWOS (chip on wafer on substrate) is an integrated manufacturing technique, in which a chip is first connected to a silicon wafer by a CoW (chip on wafer) packaging process, and then the CoW chip is connected to a substrate (substrate) to be integrated into CoWOS. By the technology, a plurality of chips can be packaged together, and bare chips on a plane are mutually connected through a conducting layer below the bare chips, so that the technical effects of small packaging volume, low power consumption and few pins are achieved.

The current CoWOS technology is divided into two categories: coWOS-S differs from CoWOS-L in that the conductive layer of CoWOS-S is a silicon interposer (silicon interposer), while the conductive layer of CoWOS-L is an interconnect metal layer. CoWOS-S has high cost and low yield, a deep trench capacitor (deep trench capacitor) of the CoWOS-L has small capacity, and the market lacks of a CoWOS technology with good overall performance, so an improved CoWOS technical scheme is urgently needed.

Disclosure of Invention

To at least partially solve the technical problems mentioned in the background, aspects of the present disclosure provide a die, a wafer, a device, a board having a CoWoS package structure, and a method of producing the die thereof.

In one aspect, the disclosure discloses a wafer with a CoWOS package structure, which includes a plurality of dies and a plurality of interposer units, wherein the interposer units are spliced according to a planar layout of the dies to form an interposer, and the dies are electrically interconnected through the interposer.

In another aspect, the present disclosure discloses an integrated circuit device including the above-mentioned wafer, and also discloses a board including the above-mentioned integrated circuit device.

In another aspect, the disclosure discloses a wafer for generating chips with CoWOS package structures. The wafer includes a plurality of dies and a plurality of interposer units, the interposer units are spliced according to a planar layout of the dies to form an interposer, and the dies are electrically interconnected by the interposer. The wafer includes a plurality of specific interposer units, a specific interposer unit being one of the plurality of interposer units.

In another aspect, the disclosure discloses a method of creating a wafer having a CoWOS package structure, the wafer including a plurality of chips. The method comprises the following steps: mass-producing a plurality of interposer units; splicing various interposer units according to the plane layout of the chips to form an interposer; bonding the plurality of chips and the interposer; and packaging the plurality of chips and the interposer to form the wafer.

The interposer is modularized to generate various interposer units, and appropriate interposer units are selected according to requirements to be spliced to form the interposer in the CoWOS technology. The disclosed technology has the advantages of controllable cost, good yield, large deep trench capacitance, and better overall performance than CoWOS-S and CoWOS-L.

Drawings

The foregoing and other objects, features and advantages of exemplary embodiments of the present disclosure will be readily understood by reading the following detailed description with reference to the accompanying drawings. Several embodiments of the present disclosure are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar or corresponding parts and in which:

fig. 1 is a block diagram illustrating a board card according to an embodiment of the present disclosure;

FIG. 2 is a block diagram illustrating an integrated circuit device of an embodiment of the present disclosure;

FIG. 3 is a schematic diagram showing the internal structure of a computing device of an embodiment of the present disclosure;

FIG. 4 is an internal block diagram illustrating a processor core of an embodiment of the present disclosure;

FIG. 5 is a layout diagram illustrating a package structure according to an embodiment of the present disclosure;

FIG. 6 is a layout diagram illustrating another package structure of an embodiment of the present disclosure;

FIG. 7 is a layout diagram illustrating another package structure of an embodiment of the present disclosure;

FIG. 8 is a method of creating a wafer with a CoWOS package structure illustrating another embodiment of the present disclosure;

FIG. 9 is a flow chart illustrating a method of fabricating a CoWOS structure with interposer elements on a wafer according to another embodiment of the disclosure;

FIG. 10 is a cross-sectional view illustrating a packaging process structure of a CoW according to an embodiment of the disclosure;

FIG. 11 is a cross-sectional view of a packaging process structure of CoW according to an embodiment of the disclosure; and

FIG. 12 is a cross-sectional view of a CoWOS package process structure according to an embodiment of the disclosure.

Detailed Description

The technical solutions in the embodiments of the present disclosure will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present disclosure, and it is to be understood that the described embodiments are only a part of the embodiments of the present disclosure, and not all of the embodiments. All other embodiments, which can be derived by one skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the scope of protection of the present disclosure.

It should be understood that the terms "first," "second," "third," and "fourth," etc. in the claims, description, and drawings of the present disclosure are used to distinguish between different objects and are not used to describe a particular order. The terms "comprises" and "comprising," when used in the specification and claims of this disclosure, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It is also to be understood that the terminology used in the description of the disclosure herein is for the purpose of describing particular embodiments only, and is not intended to be limiting of the disclosure. As used in the specification and claims of this disclosure, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should be further understood that the term "and/or" as used in the specification and claims of this disclosure refers to any and all possible combinations of one or more of the associated listed items and includes such combinations.

As used in this specification and claims, the term "if" may be interpreted contextually as "when", "upon" or "in response to a determination" or "in response to a detection".

Specific embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

Today, semiconductor processing begins with a complete wafer (wafer) consisting of a circular thin sheet of pure silicon, typically divided into 6 inch, 8 inch, 12 inch, etc., which is cut into individual pieces called dice (die). Each die has a chip (chip) mounted thereon and wiring is routed to perform a specific electrical function. The chips are then packaged into a pellet, the purpose of which is to mount, secure, seal, protect the chips and enhance the thermal performance of the chip, and the chip contacts are wired to the leads of the package housing, thereby completing a chip package.

One embodiment of the present disclosure is a CoWOS package structure formed on a wafer, in which the chip mainly includes a memory and a system on chip, but the present disclosure is not limited to only packaging the aforementioned devices.

The memory is used for temporarily storing operation data required by the system on chip and data exchanged with the external memory. In this embodiment, the memory may be a High Bandwidth Memory (HBM), which is a high performance DRAM manufactured based on a 3D stack process and is suitable for applications requiring high memory bandwidth, such as a graphics processor, and an online switching and forwarding device (e.g., a router and a switch).

A system on chip (SoC) refers to a technology of grouping all or part of necessary electronic circuits by integrating a complete system on a single chip. In this embodiment, the system-on-chip is mounted on a board. Fig. 1 shows a schematic structural diagram of a board card 10 according to an embodiment of the disclosure. As shown in fig. 1, the board 10 includes a combination processing device 101, which is an artificial intelligence arithmetic unit for supporting various deep learning and machine learning algorithms, and meeting the intelligent processing requirements in the fields of computer vision, speech, natural language processing, data mining, and the like under complex scenes. Especially, deep learning technology is applied to the cloud intelligent field in a large amount, and one remarkable characteristic of cloud intelligent application is that the input data amount is large, and the requirements on the storage capacity and the computing capacity of a platform are high.

The combination processing device 101 is connected to an external device 103 through an external interface device 102. The external device 103 is, for example, a server, a computer, a camera, a display, a mouse, a keyboard, a network card, a wifi interface, or the like. The data to be processed may be transferred to the combined processing device 101 by the external device 103 through the external interface device 102. The calculation result of the combination processing device 101 can be transmitted back to the external device 103 via the external interface device 102. The external interface device 102 may have different interface forms, such as a PCIe interface, according to different application scenarios.

The board 10 also comprises an external memory 104 for storing data, which comprises one or more memory units 105. The external memory 104 is connected and data-transferred to the control device 106 and the combined processing apparatus 101 through a bus. The control device 106 in the board 10 is configured to regulate the state of the combined processing device 101. For this reason, in an application scenario, the control device 106 may include a single chip Microcomputer (MCU).

Fig. 2 is a schematic diagram showing the combined processing apparatus 101 of this embodiment. As shown in fig. 2, the combined processing device 101 includes a computing device 201, an interface device 202, a processing device 203, and a DRAM 204. In an application scenario, the computing device 201, the interface device 202, and the processing device 203 are integrated into the foregoing system on chip. In another application scenario, the computing device 201 itself is the aforementioned system on a chip.

The computing device 201 is configured to perform user-specified operations, mainly implemented as a single-core smart processor or a multi-core smart processor, to perform deep learning or machine learning computations, which may interact with the processing device 203 through the interface device 202 to collectively perform the user-specified operations.

The interface device 202 is used for transmitting data and control instructions between the computing device 201 and the processing device 203. For example, the computing device 201 may obtain input data from the processing device 203 via the interface device 202, and write to a storage device on the computing device 201. Further, the computing device 201 may obtain the control instruction from the processing device 203 via the interface device 202, and write the control instruction into the control cache on the computing device 201. Alternatively or optionally, the interface device 202 may also read data from a storage device of the computing device 201 and transmit the data to the processing device 203.

The processing device 203, as a general purpose processing device, performs basic control including, but not limited to, data transfer, starting and/or stopping of the computing device 201, and the like. Depending on the implementation, the processing device 203 may be one or more types of processors including but not limited to a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, etc., and the number may be determined according to actual needs. As previously mentioned, the computing device 201 of the present disclosure may be viewed as having a single core structure or an isomorphic multi-core structure only. However, when considered collectively, the computing device 201 and the processing device 203 are considered to form a heterogeneous multi-core structure.

The DRAM 204 is the aforementioned high bandwidth memory for storing data to be processed, and is typically 16G or larger in size for storing data of the computing device 201 and/or the processing device 203.

Fig. 3 shows an internal structural diagram of the computing apparatus 201. The computing device 201 is configured to process input data such as computer vision, voice, natural language, data mining, and the like, and the computing device 201 in the figure is designed in a multi-core hierarchical structure, and includes an external storage controller 301, a peripheral communication module 302, an on-chip interconnection module 303, a synchronization module 304, and a plurality of clusters 305.

There may be multiple external memory controllers 301, 2 shown by way of example in the figure, for accessing an external memory device, such as DRAM 204 in figure 2, to read data from or write data to off-chip in response to an access request issued by a processor core. The peripheral communication module 302 is used for receiving the control signal from the processing device 203 through the interface device 202 and starting the computing device 201 to execute the task. The on-chip interconnect module 303 connects the external memory controller 301, the peripheral communication module 302 and the plurality of clusters 305 for transmitting data and control signals between the respective modules. The synchronization module 304 is a global synchronization barrier controller (GBC) for coordinating the operation progress of the clusters and ensuring the synchronization of the information. The plurality of clusters 305 are the computing cores of the computing device 201, 4 are exemplarily shown in the figure, and as hardware advances, the computing device 201 of the present disclosure may further include 8, 16, 64, or even more clusters 305. The clusters 305 are used to efficiently execute deep learning algorithms.

Each cluster 305 includes multiple processor cores (IPU core) 306 and a memory core (MEM core) 307.

The processor cores 306 are exemplarily shown in 4 in the figure, and the present disclosure does not limit the number of the processor cores 306. The internal architecture is shown in fig. 4. Each processor core 306 includes three major modules: a control module 41, an arithmetic module 42 and a storage module 43.

The control module 41 is used for coordinating and controlling the operations of the operation module 42 and the storage module 43 to complete the deep learning task, and includes an Instruction Fetch Unit (IFU) 411 and an Instruction Decode Unit (IDU) 412. The instruction fetch unit 411 is used for obtaining an instruction from the processing device 203, and the instruction decoding unit 412 decodes the obtained instruction and sends the decoded result as control information to the operation module 42 and the storage module 43.

The operation module 42 includes a vector operation unit 421 and a matrix operation unit 422. The vector operation unit 421 is used for performing vector operation, and can support complex operations such as vector multiplication, addition, nonlinear transformation, etc.; the matrix operation unit 422 is responsible for the core calculation of the deep learning algorithm, namely matrix multiplication and convolution.

The storage module 43 is used to store or transport related data, and includes a neuron storage unit (neuron RAM, NRAM) 431, a weight storage unit (weight RAM, WRAM) 432, an input/output direct memory access (IODMA) 433, and a transport direct memory access (MVDMA) 434.NRAM 431 to store input, output data and intermediate results for computation by processor core 306; the WRAM 432 is used for storing the weight of the deep learning network; IODMA 433 controls access of NRAM 431/WRAM 432 and DRAM 204 through broadcast bus 309; the MVDMA 434 is used to control access of the NRAM 431/WRAM 432 and the SRAM 308.

Returning to FIG. 3, the storage core 307 is primarily used to store and communicate, i.e., store shared data or intermediate results among the processor cores 306, as well as perform communications between the clusters 305 and the DRAMs 204, communications among the clusters 305, communications among the processor cores 306, and the like. In other embodiments, storage core 307 has the capability of scalar operations to perform scalar operations.

The storage core 307 includes a shared memory unit (SRAM) 308, a broadcast bus 309, a Cluster Direct Memory Access (CDMA) 310, and a Global Direct Memory Access (GDMA) 311. The SRAM 308 plays a role of a high-performance data transfer station, data multiplexed among different processor cores 306 in the same cluster 305 do not need to be acquired from the DRAM 204 through the processor cores 306 respectively, the data are transferred among the processor cores 306 through the SRAM 308, and the storage core 307 only needs to rapidly distribute the multiplexed data from the SRAM 308 to the plurality of processor cores 306, so that the inter-core communication efficiency is improved, and the on-chip and off-chip input/output access is greatly reduced.

The broadcast bus 309, CDMA 310 and GDMA 311 are used to perform communication between the processor cores 306, communication between the cluster 305 and data transmission between the cluster 305 and the DRAM 204, respectively. As will be described separately below.

The broadcast bus 309 is used to accomplish high-speed communication among the processor cores 306 in the cluster 305, and the broadcast bus 309 of this embodiment supports inter-core communication modes including unicast, multicast and broadcast. Unicast refers to the transfer of data to a point (i.e., a single processor core to a single processor core), multicast refers to the communication of a copy of data from SRAM 308 to a specific number of processor cores 306, and broadcast refers to the communication of a copy of data from SRAM 308 to all processor cores 306, which is a special case of multicast.

CDMA 310 is used to control access to SRAM 308 between different clusters 305 within the same computing device 201. The GDMA 311 cooperates with the external memory controller 301 to control the access of the SRAM 308 of the cluster 305 to the DRAM 204 or to read data from the DRAM 204 into the SRAM 308.

Fig. 5 is a top view of a package structure according to this embodiment, the package structure is disposed in a molding compound (molding compound) region 50 of a chip, the molding compound region 50 includes a system region and a memory region, the system region is disposed in the center of the molding compound region 50 for placing 2 on-chip systems 501, and the memory regions are disposed on two sides of the system region for placing 8 memories 502. More specifically, the wafer of this embodiment includes a plurality of chips, where the chips refer to a system-on-chip 501 and a memory 502, the system-on-chip 501 is the aforementioned system-on-chip and may include only the computing device 201 or include the computing device 201, the interface device 202 and the processing device 203, and the memory 502 is a DRAM 204, and is averagely disposed in a storage area, and 4 memories 502 are disposed in each storage area.

The wafer of this embodiment further includes a plurality of interposer units that are tiled according to a planar layout of a plurality of dies to form a CoWoS structure interposer, the dies being electrically interconnected by the tiled interposer. As shown by the dashed lines in fig. 5, the interposer of this embodiment is spliced from 3 types of interposer units: a first interposer unit 503, a second interposer unit 504, and a third interposer unit 505. The first interposer unit 503 is used to connect the contacts of the 4 memories 502 in the left storage area to the interposer, the second interposer unit 504 is used to connect the contacts of the 2 systems-on-chip 501 in the system area to the interposer, and the third interposer unit 505 is used to connect the contacts of the 4 memories 502 in the right storage area to the interposer.

The first interposer unit 503, the second interposer unit 504, and the third interposer unit 505 each include redistribution layers. The rewiring layer is used for enabling the chip to be suitable for different packaging modes by enabling the circuit contact of the chip (namely the output/input end of the chip) to pass through a wafer-level metal wiring process and changing the contact position of the wafer-level metal wiring process. In short, a metal layer and a dielectric layer are deposited on a wafer and corresponding metal wiring patterns are formed for rearranging the output/input/output terminals of the chip for electrical signal conduction, so that the chip layout is more flexible. The metal layer and the dielectric layer are redistribution layers. When the redistribution layer is designed, through holes need to be added at the overlapping positions of two adjacent layers of criss-cross metal wiring with the same electrical characteristics to ensure the electrical connection between the upper layer and the lower layer, so that the electrical connection among a plurality of chips is realized by a three-dimensional conductive structure, and the layout area is further reduced.

The rewiring layer generates a wire layout according to the relative positions of the chips in the plane layout and the electrical function of the wafer, namely forming a metal layer and a dielectric layer. That is, the wire routing of the redistribution layer is specially designed, when the 3 interposer units are spliced together, according to the output/input/output terminals of the chips and the signal transmission relationship between the output/input/output terminals of the chips, the metal layer and the dielectric layer of the redistribution layer need to be deposited in a customized manner to form a corresponding metal wiring pattern, and the electrical conduction of the metal wiring pattern can realize the electrical function preset by the chip, for example, the redistribution layer between the system-on-chip 501 and the memory 502 needs to be designed in a customized manner, so that the data input terminal of the system-on-chip 501 can smoothly take out the data from the data output terminal of the memory 502 for operation, and the operation result is stored back to the memory 502 through the data output terminal of the system-on-chip 501 to the data input terminal of the memory 502.

The spacing between two adjacent interposer units is 20 to 70 microns. In this embodiment, the first interposer unit 503 and the second interposer unit 504 are spaced apart by 20 to 70 microns, and the second interposer unit 504 and the third interposer unit 505 are also spaced apart by 20 to 70 microns. Preferably, the interval between two adjacent interposer units is set to 20 μm.

Fig. 6 shows a layout top view of another embodiment. Unlike the previous embodiment, 12 memories 502 are placed in the storage area, and the left storage area and the right storage area each include 6 memories 502.

As shown by the dashed lines in fig. 6, the interposer of this embodiment is spliced from 3 interposer units: a first interposer unit 601, a second interposer unit 602, and a third interposer unit 603. The first interposer unit 601 is used to connect the contacts of the 6 memories 502 in the left storage area to the interposer, the second interposer unit 602 is used to connect the contacts of the 2 systems-on-chip 501 in the system area to the interposer, and the third interposer unit 603 is used to connect the contacts of the 6 memories 502 in the right storage area to the interposer.

The redistribution layers of the first interposer unit 601, the second interposer unit 602, and the third interposer unit 603 also generate the layout of the conductive lines according to the relative positions of the chips in the planar layout and the electrical functions of the chip, and when the 3 interposer units are spliced together, the electrical conduction of the 3 interposer units can achieve the electrical functions predetermined by the chip. In this embodiment, the interval between two adjacent interposer units is also 20 to 70 microns, and preferably the interval between two adjacent interposer units is set to 20 microns.

Fig. 7 is a layout top view of another embodiment, in which the layout of the system-on-chip 501 and the memory 502 is the same as the embodiment of fig. 5, except for the interposer unit.

As shown by the dashed lines in fig. 7, the interposer of this embodiment is spliced from 6 interposer units: first, second, third, fourth, fifth, and

sixth interposer units

701, 702, 703, 704, 705, and 706, respectively, connect the contacts of the upper die to the interposer. The redistribution layers of the interposer units also generate wire layouts according to the relative positions of the chips in the planar layout and the electrical functions of the chip, and when the 3 interposer units are spliced together, the electrical conduction of the 3 interposer units can realize the electrical functions preset by the chip. In this embodiment, the spacing between two adjacent interposer units is also 20 to 70 microns, and preferably the spacing between two adjacent interposer units is set to 20 microns.

The embodiments of fig. 5-7 illustrate the present disclosure forming an interposer in the CoWoS technology by modularizing the interposer to generate a plurality of interposer units, and then selecting appropriate interposer units for splicing as required. The embodiments of fig. 5 to 7 are only used to illustrate the interposer modularization, and the present disclosure does not limit the types of chips, the number and the layout positions of the system-on-chip 501 and the memory 502, and the selection and arrangement of the interposer units are related to the types, the number and the layout positions of the chips, so the present disclosure also does not limit the size, the number, the shape and the splicing manner of the interposer units. Similarly, the storage area and the system area in the foregoing embodiments are only for convenience of distinguishing the arrangement positions of the system-on-chip 501 and the memory 502, in practice, the layout of the chip does not necessarily need to define each area, and often a plurality of chips are mixedly arranged based on the consideration of signal transmission and area.

An advantage of the foregoing embodiments is that a particular interposer unit can be repeatedly generated on a wafer, i.e., the wafer includes a plurality of particular interposer units, where a particular interposer unit is one of the plurality of interposer units. More specifically, taking the embodiment of fig. 5 as an example, the same lot of wafers are only fabricated into the first interposer unit 503, another lot of wafers are only fabricated into the second interposer unit 504, and another lot of wafers are only fabricated into the third interposer unit 505, after these wafers are cut, a large number of the first interposer unit 503, the second interposer unit 504, and the third interposer unit 505 are generated, and then according to the planar layout of the chip on the wafer, each of the first interposer unit 503, the second interposer unit 504, and the third interposer unit 505 is selected to be spliced into an interposer suitable for the planar layout of the chip in fig. 5, so as to achieve the electrical function of the chip.

Fig. 8 illustrates another embodiment of a method of creating a wafer having a CoWoS package, i.e., the method of creating a wafer of the CoWoS package of fig. 5-7. In step 801, a plurality of interposer units are mass-produced, i.e., redistribution layers are generated in the interposer units according to the relative positions of the plurality of chips in the planar layout and the electrical functions of the wafer, and more specifically, metal layers and dielectric layers are deposited to generate the redistribution layers, and the metal layers and the dielectric layers are used to realize the electrical connections between the plurality of chips in a three-dimensional conductive structure. In step 802, a plurality of interposer units are assembled to form an interposer according to a planar layout of a plurality of chips on a wafer, wherein the interval between two adjacent interposer units is further set to be 20 to 70 microns, preferably 20 microns. In step 803, the plurality of dies and the interposer are bonded such that the contacts of the dies are connected to the redistribution layer of the interposer unit. In step 804, a plurality of dies and an interposer are packaged to form a wafer.

The interposer unit of the present disclosure is a chip architecture that is easily mixed with chips of different process nodes, such as the integration of the system on chip and the memory disclosed in the above embodiments, and the performance, power consumption, and size benefits are enormous.

Because only one type of interposer unit is fabricated on a single wafer, the interposer unit can be mass-produced, not only reducing the fabrication cost, but also improving the yield by simplifying the structure. Moreover, after the interposer is modularized, the planar layouts of different chips can be spliced by using the existing or standard interposer units, and the interposer does not need to be redesigned according to the planar layouts of the different chips, so that the cost benefit is further optimized. Finally, the interposer unit of this embodiment basically adopts the interposer structure of CoWOS-S, and thus has the same large deep trench capacitance as CoWOS-S, and the larger the capacitance, the more contributes to stable supply of power to the chip. In summary, the overall performance of the technical solution of the present disclosure is outstanding.

In addition to the system-on-chip 501 and the memory 502, the chips of the present disclosure may include various integrated circuits, such as various passive and active microelectronic devices, such as resistors, other capacitor types (e.g., MIMCAP), inductors, diodes, metal Oxide Semiconductor Field Effect Transistors (MOSFET), complementary Metal Oxide Semiconductor (CMOS) transistors, bipolar Junction Transistors (BJT), laterally Diffused Metal Oxide Semiconductor (LDMOS) transistors, high power metal oxide semiconductor transistors, or other types of transistors, and the like.

Another embodiment of the disclosure is a method of fabricating a CoWoS structure with interposer elements on a wafer. The method of this embodiment is shown in fig. 9, and fig. 10 is a cross-sectional view of the package structure at various steps of this embodiment.

In step 901, a plurality of wafer bumps and system on chip and memory are bonded on the interposer unit. Prior to this step, the appropriate interposer units have been spliced into an interposer based on the planar layout of the system-on-chip and memory, and the electrical functionality of the die. After this step is completed, the structure 10A shown in fig. 10 is formed on the glass 1001, wherein the various interposer units are spliced into the interposer 1002, and the system-on-chip 1003 and the memory 1004 are electrically bonded to the interposer 1002.

In step 902, an underfill is applied to the system area and the storage area. The underfill material may promote the effects of humidity protection, thermal shock, and various mechanical impacts, which function to provide higher reliability and longer life cycle. After this step is completed, a structure 10B as shown in fig. 10 is formed on the glass 1001, wherein the underfill 1005 protects the contacts of the system-on-chip 1003 and the memory 1004.

In step 903, the system on chip and the memory are encapsulated to form a CoW structure. That is, the soc 1003 and the memory 1004 are encapsulated, and a structure 10C as shown in fig. 11 is formed on the glass 1001, wherein the encapsulating plastic 1006 encapsulates the soc 1003 and the memory 1004, and plays a role in mounting, fixing, sealing, protecting and enhancing the electrothermal performance. Thus, the CoW structure is realized.

In step 904, the glass bond (CoW) structure is formed. The glass 1001 is removed, the whole CoW structure is turned over so that the system on chip 1003 and the memory 1004 face down, and then the packaging plastic 1006 and the glass 1007 are bonded by mechanical or chemical methods to form a laminated material, which can be generally used as the bonding method: anodic bonding, adhesive interlayer method, silicon (or glass) surface coating bonding method, and the like. After this step is completed, the structure 10D is formed as shown in fig. 11.

In step 905, the wafer is polished so that the surface of the other side of the through-silicon-via is flush with the surface of the wafer. As shown in structure 10E of fig. 11, this embodiment utilizes chemical mechanical polishing to polish the surface of the interposer 1002 flat and to make all the surfaces of the through-silicon vias 1008 flush with the surface of the interposer 1002, i.e., the surfaces of the through-silicon vias 1008 are exposed.

In step 906, a plurality of wafer bumps are formed on the surface of interposer 1002 connecting the other side of the silicon vias. As shown in structure 10F of fig. 12, a wafer bump 1009 is formed at the opening of each through silicon via 1008 using a C4 process.

In step 907, the wafer bumps are soldered to the substrate. As shown in structure 10G of fig. 12, the glass 1007 is removed, the CoW structure is turned upside down so that the molding compound 1006 faces upward, the molding compound 1006 is polished so that the surface of the system on chip 1003 or the memory 1004 is exposed to air to facilitate heat dissipation, and the wafer bumps 1009 are soldered to the substrate 1010. The pitch of the two wafer bumps 1009 is 60 microns, and the center distance is 130, 150 or 180 microns. This completes the CoWoS package structure of this embodiment.

The disclosure is not limited to the way of manufacturing the CoWoS package structure with the interposer unit, and other processes can be used to manufacture the CoWoS package structure besides the process shown in fig. 9, such as first implementing the interposer, the wafer bump, the substrate, and other structures, then bonding the system on chip and the memory, and finally filling the underfill and the system on chip and the memory. This procedure is well known to those skilled in the art and will not be described in detail.

The interposer is modularized to generate a plurality of interposer units, and then appropriate interposer units are selected and spliced according to requirements to form the interposer in the CoWOS technology.

The foregoing may be better understood in light of the following clauses:

clause A1, a wafer having a CoWoS package structure, includes a plurality of dies and a plurality of interposer units that are tiled according to a planar layout of the dies to form an interposer, through which the dies are electrically interconnected.

Clause A2, the wafer of clause A1, further comprising a molding compound region, the molding compound region comprising a system region and a storage region.

Clause A3, the wafer of clause A2, wherein the plurality of chips comprises a system-on-chip.

Clause A4, the wafer of clause A3, wherein the system-on-chip is placed in the system area.

Clause A5, the wafer of clause A2, wherein the plurality of chips comprise memory.

Clause A6, the die of clause A5, wherein the memory is high bandwidth memory.

Clause A7, the wafer of clause A5 or 6, wherein the memory is located in the storage area.

Clause A8, the die of clause A1, wherein the interposer unit includes a redistribution layer that generates a wire layout according to the relative positions of the plurality of dies in the planar layout and the electrical function of the die.

Clause A9, the wafer of clause A8, wherein the redistribution layer comprises a metal layer and a dielectric layer, the metal layer and the dielectric layer electrically connecting the plurality of chips with each other in a three-dimensional conductive structure.

Clause a10, the wafer of clause A1, wherein the spacing between two adjacent interposer units is 20 to 70 microns.

Clause a11, the wafer of clause A1, wherein the plurality of interposer units are chip architectures.

Clause a12, an integrated circuit device, comprising a wafer according to any one of clauses A1-11.

Clause a13, a board comprising the integrated circuit device of clause a 12.

Clause a14, a wafer for generating a die having a CoWoS package structure, the die including a plurality of dies and a plurality of interposer units, the plurality of interposer units being tiled according to a planar layout of the plurality of dies to form an interposer, the plurality of dies being electrically interconnected by the interposer, the wafer including a plurality of specific interposer units, the specific interposer unit being one of the plurality of interposer units.

Clause a15, the wafer of clause a14, wherein the particular interposer unit includes a redistribution layer that generates a wire layout according to the relative positions of the plurality of dies in the planar layout and the electrical function of the dies.

Clause a16 and the wafer according to clause a15, wherein the redistribution layer includes a metal layer and a dielectric layer, and the metal layer and the dielectric layer implement the electrical connection between the plurality of chips in a three-dimensional conductive structure.

Clause a17, the wafer of clause a14, wherein the plurality of interposer units are die structures.

Clause a18, a method of generating a wafer having a CoWoS package structure, the wafer comprising a plurality of chips, the method comprising: mass-producing a plurality of interposer units; splicing the multiple interposer units to form an interposer according to the planar layout of the multiple chips; bonding the plurality of dies to the interposer; and packaging the plurality of dies and the interposer to form the die.

Clause a19, the method of clause a18, wherein the step of mass producing comprises: and generating a redistribution layer in the interposer unit according to the relative positions of the chips in the planar layout and the electrical functions of the wafer.

Clause a20, the method of clause a19, wherein the step of generating a redistribution layer comprises: depositing a metal layer and a dielectric layer; the metal layer and the dielectric layer are used for electrically connecting the chips in a three-dimensional conduction structure.

Clause a21, the method of clause a18, wherein the splicing step comprises: the spacing between adjacent interposer units is set to be 20 to 70 microns.

Clause a22, the method of clause a18, wherein the plurality of interposer units are core die architectures.

The foregoing detailed description of the disclosed embodiments has been presented to enable one of ordinary skill in the art to make and use the principles and implementations of the present disclosure; in addition, the disclosure should not be construed as limited to the particular embodiments set forth herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A wafer with a CoWOS packaging structure comprises a plurality of chips and a plurality of interposer units, wherein the interposer units are spliced according to the plane layout of the chips to form an interposer, and the chips are electrically interconnected through the interposer.

2. The wafer of claim 1, further comprising a molding compound region, the molding compound region comprising a system region and a memory region.

3. The wafer of claim 2, wherein the plurality of chips comprise a system on a chip.

4. The wafer of claim 3, wherein the system-on-chip is placed in the system area.

5. The wafer of claim 2, wherein the plurality of chips comprise memory.

6. The die of claim 5, wherein the memory is a high bandwidth memory.

7. The wafer of claim 5 or 6, wherein the memory is placed in the storage area.

8. The die of claim 1, wherein the interposer unit includes a redistribution layer that generates a wire layout according to relative positions of the plurality of dies in the planar layout and electrical functionality of the die.

9. The wafer of claim 8, wherein the redistribution layer comprises a metal layer and a dielectric layer, the metal layer and the dielectric layer enabling electrical connection between the plurality of chips in a three-dimensional conductive structure.

10. The wafer of claim 1, wherein the spacing between two adjacent interposer units is 20 to 70 microns.

11. The wafer of claim 1, wherein the plurality of interposer units are die architectures.

12. An integrated circuit device comprising a wafer according to any one of claims 1-11.

13. A board card comprising the integrated circuit device of claim 12.

14. A wafer for generating a chip with a CoWOS package structure, the chip comprising a plurality of dies and a plurality of interposer units, the plurality of interposer units being tiled according to a planar layout of the plurality of dies to form an interposer, the plurality of dies being electrically interconnected by the interposer, the wafer comprising a plurality of specific interposer units, the specific interposer unit being one of the plurality of interposer units.

15. The wafer of claim 14, wherein the particular interposer unit includes a redistribution layer that generates a wire layout based on relative positions of the plurality of dies in the planar layout and electrical functionality of the dies.

16. The wafer of claim 15, wherein the redistribution layer comprises a metal layer and a dielectric layer, and the metal layer and the dielectric layer enable electrical connection between the plurality of chips in a three-dimensional conductive structure.

17. The wafer of claim 14, wherein the plurality of interposer units are die structures.

18. A method of creating a wafer having a CoWoS package structure, the wafer comprising a plurality of chips, the method comprising:

mass-producing a plurality of interposer units;

splicing the multiple interposer units to form an interposer according to the planar layout of the multiple chips;

bonding the plurality of dies to the interposer; and

packaging the plurality of dies with the interposer to form the die.

19. The method of claim 18, wherein the step of mass producing comprises:

and generating a redistribution layer in the interposer unit according to the relative positions of the chips in the planar layout and the electrical functions of the wafer.

20. The method of claim 19, wherein the step of generating a redistribution layer comprises:

depositing a metal layer and a dielectric layer;

the metal layer and the dielectric layer are used for electrically connecting the plurality of chips by a three-dimensional conduction structure.

21. The method of claim 18, wherein the splicing step comprises:

the interval between two adjacent interposer units is set to be 20 to 70 μm.

22. The method of claim 18, wherein the plurality of interposer units are core die architectures.