CN115966517A - Back-to-back stacking process, medium and computer equipment - Google Patents

Abstract

The invention relates to a back-to-back stacking process, a computer readable storage medium, a computer program product and a computer device, forming a circuit on a logic side of a first wafer; turning over the first wafer; bonding a second wafer on the logic side; exposing the first through-silicon-via to an opposite side relative to the logic side; cutting the first wafer into a plurality of first crystal grains; turning over the first crystal grain; and attaching the opposite side of the first crystal grain and the opposite side of the second crystal grain to ensure that the first through silicon via is electrically communicated with the second through silicon via of the second crystal grain.

Description

Back-to-back stacking process, medium and computer equipment

Technical Field

The present invention relates generally to the field of semiconductors. More particularly, the present invention relates to a back-to-back stacking process method, a computer readable storage medium, a computer program product and a computer device.

Background

Since the dada era, the system-on-chip combined with the artificial intelligence technology needs to cope with more and more complex environments, forcing the system-on-chip to develop more functions, and the chip design has approached the maximum mask size at present. Therefore, developers try to divide the system-on-chip into multi-chip modules, and the modules are vertically stacked to solve the problem of limited chip area.

CoWOS (chip on wafer on substrate) is an integrated manufacturing technique, in which a chip is first connected to a silicon wafer (wafer) by a packaging process of CoW (chip on wafer), and then the CoW chip is connected to a substrate (substrate) to be integrated into CoWOS. By the technology, a plurality of crystal grains can be vertically stacked and packaged together, and the technical effects of small packaging volume, low power consumption and few pins are achieved.

As semiconductor manufacturing processes progress in the vertical direction, the conventional die stacking method is limited, so that the vertical stacking efficiency of the die is affected. Therefore, various technical solutions for die stacking are urgently needed.

Disclosure of Invention

To at least partially solve the technical problems mentioned in the background, the present invention provides a back-to-back stacking process, a computer readable storage medium, a computer program product and a computer device.

In one aspect, the present invention discloses a method for manufacturing a back-to-back stack, comprising: forming a circuit on the logic side of the first wafer; turning over the first wafer; bonding a second wafer on the logic side; exposing the first through-silicon-via to an opposite side relative to the logic side; cutting the first wafer into a plurality of first crystal grains; turning over the first crystal grain; and attaching the opposite side of the first crystal grain and the opposite side of the second crystal grain to ensure that the first through silicon via is electrically communicated with the second through silicon via of the second crystal grain.

In another aspect, the present invention discloses a computer readable storage medium having stored thereon computer program code for a back-to-back stacking process method, the computer program code, when executed by a processing device, performing the process method.

In another aspect, the present invention discloses a computer program product comprising a computer program for a back-to-back stacking process, wherein the computer program is executed by a processor to implement the steps of the method according to the aforementioned embodiments.

In another aspect, the present invention discloses a computer device, which includes a memory, a processor and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the methods of the foregoing embodiments.

The invention provides a crystal grain back-to-back stacking scheme, so that when a plurality of crystal grains are stacked, the crystal grains of the same crystal grain group can be attached face to face, the transmission path among the crystal grains in the same crystal grain group is greatly shortened, and the transmission efficiency in the crystal grain group is improved.

Drawings

The above and other objects, features and advantages of exemplary embodiments of the present invention will become readily apparent from the following detailed description read in conjunction with the accompanying drawings. In the drawings, several embodiments of the invention are shown by way of example and not limitation, and like or corresponding reference numerals indicate like or corresponding parts. Wherein:

FIG. 1 illustrates a top layout view of a package structure including a die-to-die interface;

FIG. 2 shows a cross-sectional view of the package structure of FIG. 1 along the direction of the dashed line;

fig. 3 is a structural diagram showing a board card of the embodiment of the present invention;

FIG. 4 is a block diagram illustrating an integrated circuit device of an embodiment of the invention;

FIG. 5 is a schematic diagram showing longitudinal stacking of an embodiment of the present invention;

FIG. 6 is a cross-sectional view showing the structure of FIG. 5;

FIG. 7 is a flow chart illustrating an implementation of an embodiment of the present invention for back-to-back stacking;

fig. 8 is a sectional view showing step 701;

FIG. 9 is a cross-sectional view illustrating step 704;

FIG. 10 is a cross-sectional view showing step 705;

FIG. 11 is a cross-sectional view showing step 705;

FIG. 12 is a cross-sectional view showing step 705;

FIG. 13 is a cross-sectional view showing step 705;

FIG. 14 is a cross-sectional view showing step 706;

FIG. 15 is a cross-sectional view showing step 707;

FIG. 16 is a cross-sectional view illustrating step 708;

fig. 17 is a sectional view showing step 709; and

fig. 18 is a sectional view showing step 711.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It should be understood that the terms "first", "second", "third" and "fourth", etc. in the claims, the description and the drawings of the present invention are used for distinguishing different objects and are not used for describing a particular order. The terms "comprises" and "comprising," when used in the specification and claims of this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It is also to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the specification and claims of this application, the singular form of "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should be further understood that the term "and/or" as used in the specification and claims of this application refers to any and all possible combinations of one or more of the associated listed items and includes such combinations.

As used in this specification and claims, the term "if" may be interpreted contextually as "when", "upon" or "in response to a determination" or "in response to a detection".

The following detailed description of the embodiments of the invention refers to the accompanying drawings.

The die-to-die interface is just like any other chip-to-chip interface, a data link channel is established between two dies. The die-to-die interface is logically divided into a physical layer, a link layer, and a transaction layer, and provides a standardized parallel interface to connect to internal interconnect structures.

Fig. 1 is a top view of a package structure including a die-to-die interface, the package structure being disposed in a molding compound (molding compound) area 10 of a die, the molding compound area 10 including a system area and a memory area, the exemplary system area being located in the center of the molding compound area 10 for placing 2 on-chip systems 101, and the memory area being located on each side of the system area for placing 8 off-chip memories 102.

The system area further comprises a die-to-die area 103, a physical area 104 and an input/output area 105. The die generates a transceiver circuit for the die area 103 for data sharing between the two soc 101; the physical area 104 is generated with physical access circuitry for accessing the off-chip memory 102; the input/output area 105 is formed with input/output circuits for interfacing the system-on-chip 101.

The system area also has a memory 106 as a temporary storage space for the system-on-chip 101, which has a smaller capacity than the off-chip memory 102 but a higher data transfer rate than the off-chip memory 102.

Fig. 2 shows a cross-sectional view of the package structure of fig. 1 along the direction of the dashed line. As shown, the system area is divided into upper and lower 2 layers, the upper layer is the system-on-chip 101, and the lower layer is the die-to-die 103 transceiver circuit, the memory 106, and the i/o 105 input/output circuit. The package structure further includes an interposer 121 and a substrate 122, wherein the interposer 121 is disposed on the substrate 122. When the 2 soc 101 performs data transmission, the path is the sending soc 101 → the sending-side die-to-die area 103 transceiver → the interposer 121 → the receiving-side die-to-die area 103 transceiver → the receiving-side soc 101, so as to achieve the technical effects of low delay and low power consumption of the die to the die port.

Fig. 3 shows a schematic structural diagram of a board card 30 according to an embodiment of the present invention. As shown in fig. 1, the board 30 includes a chip 301, which is a system-level chip integrated with one or more combined processing devices, and the combined processing device is an artificial intelligence arithmetic unit, which is used to support various deep learning and machine learning algorithms, and meet the intelligent processing requirements in the fields of computer vision, speech, natural language processing, data mining, and the like under complex scenes. Especially, the deep learning technology is widely applied to the field of cloud intelligence, and one remarkable characteristic of the cloud intelligence application is that the input data size is large, and the requirements on the storage capacity and the computing capacity of the platform are high, so that the board card 30 of the embodiment is suitable for the cloud intelligence application and has huge off-chip storage, on-chip storage and strong computing capacity.

The chip 301 is connected to an external device 303 through an external interface 302. The external device 303 is, for example, a server, a computer, a camera, a display, a mouse, a keyboard, a network card, a wifi interface, or the like. The data to be processed may be transferred by the external device 303 to the chip 301 through the external interface means 302. The results of the calculations of the chip 301 may be communicated back to the external device 303 via the external interface means 302. The external interface device 302 may have different interface forms, such as PCIe interface, according to different application scenarios.

In more detail, the chip 301 comprises computing means and processing means. The computing device is configured to perform user-specified operations, primarily implemented as a single-core smart processor or a multi-core smart processor, to perform deep-learning or machine-learning computations. The processing device, as a general purpose processing device, performs basic control including, but not limited to, data transfer, starting and/or stopping of a computing device, and the like. Depending on the implementation, the processing device may be one or more types of Central Processing Unit (CPU), graphics Processing Unit (GPU) or other general purpose and/or special purpose processor, including but not limited to a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware components, etc., and the number thereof may be determined according to actual needs. As previously mentioned, the computing device of this embodiment may be considered to have a single core structure or a homogeneous multi-core structure only. However, when considered together, computing devices and processing device integration are considered to form heterogeneous multi-core structures.

The card 30 also includes a memory device 304 for storing data, which includes one or more memory cells 305. The memory device 304 is connected and data-transferred to the control device 306 and the chip 301 through a bus. The control device 306 in the board 30 is configured to regulate the state of the chip 301. For this reason, in an application scenario, the control device 306 may include a single chip Microcomputer (MCU).

Fig. 4 shows the structure of the combined processing device in the board 30. The combined processing device 40 comprises a computing device 401, an interface device 402, a processing device 403 and an off-chip memory 404.

The computing device 401 is configured to perform user-specified operations, mainly implemented as a single-core smart processor or a multi-core smart processor, to perform deep learning or machine learning computations, which may interact with the processing device 403 through the interface device 402 to collectively perform the user-specified operations.

The interface device 402 is connected to the bus for connection with other devices, such as the control device 306, the external interface device 302, etc. of fig. 3.

The processing device 403, as a general purpose processing device, performs basic control including, but not limited to, data transfer, and turning on and/or off of the computing device 401. Depending on the implementation, the processing device 403 may be one or more types of processors including but not limited to a digital signal processor, an application specific integrated circuit, a field programmable gate array or other programmable logic device, a discrete gate or transistor logic device, discrete hardware components, etc., of a central processing unit, a graphics processor, or other general purpose and/or special purpose processors, and the number thereof may be determined according to actual needs. As previously mentioned, the computing device 401 of this embodiment may be viewed as having a single core structure or an isomorphic multi-core structure only. However, when considered collectively, the computing device 401 and the processing device 403 are considered to form a heterogeneous multi-core structure.

The off-chip memory 404 is used to store data to be processed, and is a DDR memory, which is typically 8G or larger in size and is used to store data of the computing device 401 and/or the processing device 403.

Fig. 5 shows a schematic view of a longitudinal stack of an embodiment of the invention. This embodiment is a multi-core chip including a first chip group including a first core layer 51 and a first memory layer 52, and a second chip group including a second core layer 53 and a second memory layer 54, in which actually the first core layer 51, the first memory layer 52, the second core layer 53, and the second memory layer 54 are vertically stacked in sequence, and the layers in fig. 5 are visually shown in this way for the sake of illustration only for convenience of separation.

The first core layer 51 implements the function of a processor core, and includes a first operation region 511, the first operation region 511 is fully distributed on a logic layer of the first core layer 51, i.e. a top side of the first core layer 51 in the figure, the first core layer 51 further includes a first die-to-die region 512 and a first through silicon via 513 in a special area, and a first operation circuit is generated in the first operation region 511 to implement the function of the computing device 401; the first die-to-die area 512 generates a first transceiver circuit for use as a die-to-die interface of the first arithmetic circuit; the first through-silicon-vias 513 are used to electrically interconnect the stacked chips in the three-dimensional integrated circuit.

The first memory layer 52 implements an on-chip memory function, and includes a first memory area 521, a first input/output area 522, a first physical area 523, and a second through silicon via 524. The first memory area 521 is generated with a storage unit for temporarily storing the operation result of the first operation circuit. The first input/output area 522 is formed with a first input/output circuit, which is used as an interface for the first core layer 51 and the first memory layer 52 to communicate with each other, i.e. to implement the function of the interface device 402. The second physical region 523 is configured with a first physical access circuit for accessing the off-chip memory 404. The second through-silicon-vias 524 extend through the entire first memory layer 52, illustratively shown on only one side, for electrically connecting particular devices.

The second core layer 53 implements the function of the processor core, and includes a second operation region 531, the second operation region 531 is fully distributed on the logic layer of the second core layer 53, i.e. the top side of the second core layer 53 in the figure, the second core layer 53 further includes a second die pair die region 532 and a third through silicon via 533 in a special area, and the second operation region 531 generates a second operation circuit to implement the function of the processing device 403; a second die-to-die area 532 is generated with a second transceiver circuit for use as a die-to-die interface for a second operational circuit; the third through-silicon-via 533 is also used to electrically interconnect the stacked chips in the three-dimensional integrated circuit.

The second memory layer 54 implements the function of an on-chip memory, and includes a second memory region 541, a second input/output region 542, a second physical region 543, and a fourth through silicon via 544. The second memory region 541 generates a storage unit for temporarily storing the operation result of the second operation circuit. The second input/output area 542 generates a second input/output circuit for serving as an interface for external connection between the second core layer 53 and the second memory layer 54, i.e. for implementing the function of the interface device 402. The second physical region 543 generates a second physical access circuit for accessing the off-chip memory 404. The fourth through silicon vias 544 extend throughout the second memory layer 54, illustratively shown on only one side, for electrically connecting particular devices.

The through-silicon vias of each layer include a transceiver through-silicon via, an input/output through-silicon via, and a physical through-silicon via, respectively, if necessary. The transceiver through-silicon-vias are used to electrically connect the first transceiver circuit and the second transceiver circuit, the input/output through-silicon-vias are used to electrically conduct data of the input/output circuits, and the physical through-silicon-vias are used to electrically conduct operation results of the operation circuits to the off-chip memory 404.

When the computing device 401 wants to transmit data to the processing device 403, the data arrives at the processing device 403 through the following paths: the first operational circuit of the first operational area 511 → the first transceiver circuit of the first die-to-die area 512 → the transceiver through silicon via of the first through silicon via 513 → the transceiver through silicon via of the second through silicon via 524 → the second transceiver circuit of the second die-to-die area 532 → the second operational circuit of the second operational area 531; when the processing device 403 wants to transmit data to the computing device 401, the data arrives at the computing device 401 through the reverse path.

When the calculation result of the calculation device 401 needs to exchange data with other devices outside the chip through the interface device 402, the data reaches other devices outside the chip through the following paths: the first input-output circuit of the first input-output region 522 → the input-output through silicon via of the second through silicon via 524 → the input-output through silicon via of the second through silicon via 533 → the input-output through silicon via of the fourth through silicon via 544; when another device outside the chip wants to transmit data to the first memory area 521, the data reaches the first memory area 521 through the aforementioned reverse path. When the calculation result of the processing device 403 requires data exchange with other devices off-chip through the interface device 402, the data reaches other devices off-chip through the following paths: the input-output circuit of the second input-output region 542 → the input-output through silicon via of the fourth through silicon via 544; when other off-chip devices want to transmit data to the second memory region 541, the data reaches the second memory region 541 through the aforementioned reverse path.

When the data in the first memory area 521 is to be transmitted to the off-chip memory 404, the data reaches the off-chip memory 404 through the following paths: the first physical access circuit of the first physical region 523 → the physical through-silicon via of the second through-silicon via 524 → the physical through-silicon via of the second through-silicon via 533 → the physical through-silicon via of the fourth through-silicon via 544; when the off-chip memory 404 wants to transmit the input data to the first memory area 521 for processing by the computing device 401, the data reaches the first memory area 521 through the aforementioned reverse path. When data in the second memory region 541 is to be transferred to the off-chip memory 404, the data reaches the off-chip memory 404 through the following paths: second physical access circuit of the second physical zone 543 → physical through-silicon via of the fourth through-silicon via 544; when the off-chip memory 404 wants to transmit the input data to the second memory region 541 for processing by the processing device 403, the data reaches the second memory region 541 through the aforementioned reverse path.

Each layer may be divided into a logical side and an opposite side. The logic side is provided with logic circuits to implement a specific function, and the opposite side is the other side of the layer where no logic circuits are laid out. Fig. 6 shows a cross-sectional view of the structure of fig. 5. In this embodiment, the first core layer 51 is used in combination with the first memory layer 52, and the second core layer 53 is used in combination with the second memory layer 54, for transmission efficiency, the first core layer 51 and the first memory layer 52 are bonded face to face, that is, the logic side of the first core layer 51 generating the first operation region 511 is bonded with the logic side of the first memory layer 52 generating the first memory region 521, so that the transmission path between the first operation circuit and the first memory region 521 is the shortest. Similarly, the logic side of the second core layer 53 generating the second operation area 531 is attached to the logic side of the second memory layer 54 generating the first memory area 541, so that the transmission path between the second operation circuit and the second memory area 541 is also the shortest. In order to realize the shortest transmission path, the first die set and the second die set are bonded back to back, i.e., the opposite sides of the first memory layer 52 are bonded to the opposite sides of the second core layer 53.

By the arrangement shown in fig. 6, the first die-to-die region 512 and the second die-to-die region 532 are vertically stacked such that the die-to-die interface of the first core layer 51 and the die-to-die interface of the second core layer 53 are electrically connected directly to the second through-silicon-via 524 through the first through-silicon-via 513, without the need for transmission using the interposer 121 as shown in fig. 2.

In summary, the first die set of this embodiment includes a first die and a second die that are fabricated in a face-to-face process, the second die set of this embodiment includes a first die and a second die that are fabricated in a face-to-face process, and the first die set and the second die set are fabricated in a back-to-back process, wherein the first die may be a processor core or a memory, and the second die is another of the processor core and the memory and is used in combination with the processor core or the memory.

To achieve a face-to-face process for two dies in the same die group, a back-to-back process is required for the two die groups to cooperate, i.e., the opposite side of the first memory layer 52 is attached to the opposite side of the second core layer 53. FIG. 7 illustrates a method of fabricating a back-to-back stack in accordance with an embodiment of the present invention.

In step 701, circuitry is formed on the logic side of the first wafer. Each wafer may be divided into a logical side, which refers to the side where logic is created to perform a particular electrical function, and an opposite side, which is the side of the wafer where logic is not located. Since the logic circuit is formed by deposition, etching, etc. on top of the wafer, in this step, as shown in fig. 8, the logic side 802 of the first wafer 801 is above the first wafer 801 and the opposite side 803 is below the first wafer 801.

In this step, a front end of line (FEOL) 804 is formed on the logic side 802, a first through silicon via 805 is formed on the logic side 802, and a back end of line (BEOL) 806 is formed on the logic side 802, such that the first through silicon via 805 is electrically connected to the back end of line 806. The former process is to divide the area for preparing the transistor on the silicon substrate, and then to implant ions to realize the N-type and P-type areas and realize the N-type and/or P-type field effect transistor. The subsequent steps are layers of conductive metal lines which can connect the transistors on the substrate according to the design requirements to realize specific functions. After the preceding step and the subsequent step, a preceding step layer 804 and a subsequent step layer 806 are formed, respectively. The logic side circuit is mainly realized by the previous process layer 804, and the electrical connection of each element in the circuit is realized by the next process layer 806.

In step 702, the first wafer 801 is tested to eliminate defects. Wafer testing, also known as center testing, is intended to ensure that each die substantially meets the characteristics or design specifications of the circuit, typically including verification of voltage, current, timing, and electrical functions.

In step 703, the first wafer 801 is flipped. For those first wafers that are not rejected, they are flipped 180 degrees, and after inversion, as shown in fig. 9, the logic side 802 of the first wafer 801 is below and the opposite side 803 is above.

In step 704, a second wafer 901 is bonded on the logic side 802 to form the structure shown in fig. 9.

In step 705, a first through silicon via 805 is exposed at the opposite side 803. First, the opposite sides 803 are lapped (grind) and the lapped opposite sides 803 are Chemically Mechanically Polished (CMP) to form the structure shown in fig. 10. Next, the opposite side 803 is chemically and mechanically polished by plasma etching (plasma etch) so that the first through-silicon via 805 protrudes from the surface of the opposite side 803 to form the structure shown in fig. 11. A Low Temperature Chemical Vapor Deposition (LTCVD) of silicon dioxide is then performed on the plasma etched surface to form a silicon dioxide layer 1201 as shown in fig. 12. Finally, the surface after the low temperature chemical vapor deposition is polished chemically and mechanically, so that the silicon dioxide layer 1201 becomes flat and the first through silicon via 805 is exposed, i.e. the structure shown in fig. 13.

In step 706, the first wafer 801 is diced into a plurality of first dies. First, as shown in fig. 14, a first wafer 801 and a second wafer 901 are placed on a supporter (mount on frame) 1401, then a thimble 1402 is used to push the second wafer 901, and the first wafer 801 and the second wafer 901 are cut according to the size and position of the circuit, i.e. cut along the dotted line in the figure, and finally a plurality of first dies 1403 are generated.

In step 707, the first die 1403 is flipped 180 degrees to form the structure shown in fig. 15.

In step 708, the opposing sides of the first die and the opposing sides of the second die are bonded together such that the first through-silicon-via is in electrical communication with the second through-silicon-via of the second die. The second die can be realized based on the prior art process, and the embodiment does not limit the process of the second die. As shown in fig. 16, the opposite side 803 of the first die 1403 and the opposite side 1602 of the second die 1601 are attached such that the first through-silicon via 805 is in electrical communication with the second through-silicon via 1603 of the second die 1601.

Thus, a back-to-back structure is formed, that is, the opposite side 803 of the first die 1403 and the opposite side 1602 of the second die 1601 are attached to each other, so that the circuits on the logic sides are electrically connected to each other through the first through-silicon via 805 and the second through-silicon via 1603.

In step 709, a molding compound formation (molding compound formation) is used to mold the first die 1403, so as to form the structure shown in fig. 17. There are various molding packaging processes in the prior art, and an exemplary direct bonding type package may be used, in which a first die 1403 and a second die 1601 are directly bonded to a printed wiring board or a strip of plastic film covered with metal leads, and are covered with an organic resin that is dropped around the first die 1403 to form a package 1701.

In step 710, the molded first die is ground flat.

In step 711, the planarized first grains are chemically mechanically polished to form the structure shown in fig. 18. Thus, the whole back-to-back stacking process is completed.

Another embodiment of the present invention is a computer readable storage medium having stored thereon computer program code for a back-to-back stacking process method, which when executed by a processor, performs the method of the embodiments as described above. In some implementation scenarios, the integrated units may be implemented in the form of software program modules. If implemented in the form of software program modules and sold or used as a stand-alone product, the integrated units may be stored in a computer readable memory. In this regard, when aspects of the present disclosure are embodied in the form of a software product (e.g., a computer-readable storage medium), the software product may be stored in a memory, which may include instructions for causing a computer device (e.g., a personal computer, a server, or a network device, etc.) to perform some or all of the steps of the methods described in embodiments of the present disclosure. The aforementioned memory may include, but is not limited to, various media capable of storing program codes, such as a usb disk, a flash disk, a Read Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic disk, or an optical disk.

Another embodiment of the present invention is a computer program product comprising a computer program for a back-to-back stacking process, wherein the computer program is executed by a processor to implement the steps of the method according to the aforementioned embodiments.

Another embodiment of the present invention is a computer apparatus comprising a memory, a processor and a computer program stored on the memory, wherein the processor executes the computer program to implement the steps of the methods of the foregoing embodiments.

In order to realize that two crystal grains in the same crystal grain group can adopt a face-to-face process, and a back-to-back process is needed to be adopted for matching between the two crystal grain groups, the invention provides back-to-back lamination of adjacent crystal grain groups (adjacent crystal grains), so that the transmission path of the two crystal grains of the same crystal grain group to a crystal grain interface is greatly shortened. In the present process, the thickness of the logic side is only 0.3 micron, and the thickness of the adhesion layer is about 1 micron, and by the technical scheme of the back-to-back process of the present invention, the transmission path of two grains of the same grain group can be shortened to 1.6 microns, which is helpful for improving the transmission efficiency between cores.

According to different application scenarios, the electronic device or apparatus of the present invention may include a server, a cloud server, a server cluster, a data processing apparatus, a robot, a computer, a printer, a scanner, a tablet computer, an intelligent terminal, a PC device, an internet of things terminal, a mobile phone, a vehicle data recorder, a navigator, a sensor, a camera, a video camera, a projector, a watch, an earphone, a mobile storage, a wearable device, a visual terminal, an automatic driving terminal, a vehicle, a household appliance, and/or a medical device. The vehicle comprises an airplane, a ship and/or a vehicle; the household appliances comprise a television, an air conditioner, a microwave oven, a refrigerator, an electric cooker, a humidifier, a washing machine, an electric lamp, a gas stove and a range hood; the medical equipment comprises a nuclear magnetic resonance apparatus, a B-ultrasonic apparatus and/or an electrocardiograph. The electronic device or apparatus of the present invention can also be applied to the fields of the internet, the internet of things, data centers, energy, transportation, public management, manufacturing, education, power grid, telecommunications, finance, retail, construction sites, medical care, and the like. Furthermore, the electronic equipment or the device can be used in application scenes such as a cloud end, an edge end and a terminal which are related to artificial intelligence, big data and/or cloud computing. In one or more embodiments, the electronic device or apparatus with high computational power according to the present disclosure may be applied to a cloud device (e.g., a cloud server), and the electronic device or apparatus with low power consumption may be applied to a terminal device and/or an edge device (e.g., a smartphone or a camera). In one or more embodiments, the hardware information of the cloud device and the hardware information of the terminal device and/or the edge device are compatible with each other, so that appropriate hardware resources can be matched from the hardware resources of the cloud device according to the hardware information of the terminal device and/or the edge device to simulate the hardware resources of the terminal device and/or the edge device, so as to complete unified management, scheduling and cooperative work of end-cloud integration or cloud-edge-end integration.

It is noted that for the sake of simplicity, the present invention sets forth some methods and embodiments thereof as a series of acts or combinations thereof, but those skilled in the art will appreciate that the inventive arrangements are not limited by the order of acts described. Accordingly, persons skilled in the art may appreciate that certain steps may be performed in other sequences or simultaneously, in accordance with the disclosure or teachings of the invention. Further, those skilled in the art will appreciate that the described embodiments of the invention are subject to additional alternative embodiments in which acts or modules are involved, which may not be necessary to practice one or more aspects of the invention. In addition, the description of some embodiments of the present invention is also focused on different schemes. In view of this, those skilled in the art will understand that portions of the present invention that are not described in detail in one embodiment may also refer to related descriptions of other embodiments.

In particular implementations, based on the disclosure and teachings of the present invention, one of ordinary skill in the art will appreciate that the several embodiments disclosed herein may be practiced in other ways than as specifically disclosed herein. For example, as for the units in the foregoing embodiments of the electronic device or apparatus, the units are split based on the logic function, and there may be another splitting manner in the actual implementation. Also for example, multiple units or components may be combined or integrated with another system or some features or functions in a unit or component may be selectively disabled. The connections discussed above in connection with the figures may be direct or indirect couplings between the units or components in terms of connectivity between the different units or components. In some scenarios, the aforementioned direct or indirect coupling involves a communication connection utilizing an interface, where the communication interface may support electrical, optical, acoustic, magnetic, or other forms of signal transmission.

In the present invention, units described as separate parts may or may not be physically separate, and parts shown as units may or may not be physical units. The aforementioned components or units may be co-located or distributed across multiple network elements. In addition, according to actual needs, part or all of the units can be selected to achieve the purpose of the scheme of the embodiment of the invention. In addition, in some scenarios, multiple units in an embodiment of the present invention may be integrated into one unit or each unit may exist physically separately.

In other implementation scenarios, the integrated unit may also be implemented in hardware, that is, a specific hardware circuit, which may include a digital circuit and/or an analog circuit, etc. The physical implementation of the hardware structure of the circuit may include, but is not limited to, physical devices, which may include, but are not limited to, transistors or memristors and like devices. In this regard, the various devices described herein (e.g., computing devices or other processing devices) may be implemented by suitable hardware processors, such as central processing units, GPUs, FPGAs, DSPs, ASICs, and the like. Further, the aforementioned storage unit or storage device may be any suitable storage medium (including magnetic storage medium or magneto-optical storage medium, etc.), and may be, for example, a variable Resistive Memory (RRAM), a Dynamic Random Access Memory (DRAM), a Static Random Access Memory (SRAM), an Enhanced Dynamic Random Access Memory (EDRAM), a High Bandwidth Memory (HBM), a Hybrid Memory Cube (HMC), a ROM, a RAM, or the like.

The foregoing may be better understood in light of the following clauses:

clause a1. A method of fabricating a back-to-back stack, including: forming a circuit on the logic side of the first wafer; turning over the first wafer; bonding a second wafer on the logic side; exposing the first through-silicon-via to an opposite side relative to the logic side; cutting the first wafer into a plurality of first crystal grains; turning over the first crystal grains; and attaching the opposite side of the first crystal grain and the opposite side of the second crystal grain to ensure that the first through silicon via is electrically communicated with the second through silicon via of the second crystal grain.

Clause a2. The fabrication method according to clause A1, wherein the step of forming a circuit comprises: forming a front process layer on the logic side; forming a first through silicon via on the logic side; and forming a subsequent process layer on the logic side; the first through silicon via is electrically connected with the next process layer.

Clause a3. The manufacturing process according to clause A1, further comprising: testing the first wafer to eliminate defective products; and the step of turning over the first wafer only turns over the first wafer which is not eliminated.

Clause a4. The method of manufacturing according to clause A1, wherein the exposing step comprises: grinding the opposite sides of the first wafer; and chemically and mechanically polishing the opposite side of the lapped first wafer.

Clause a5. The manufacturing process according to clause A4, wherein the exposing step further comprises: and plasma etching the opposite side of the first wafer after chemical mechanical polishing to enable the first through silicon via to protrude out of the surface of the opposite side of the first wafer.

The process method of clause A5, wherein the exposing step further comprises: depositing silicon dioxide on the surface after plasma etching by using low-temperature chemical vapor deposition; and chemically and mechanically polishing the surface after the low-temperature chemical vapor deposition to expose the first through-silicon-via.

Clause A7. the process method of clause A1, wherein the cutting step comprises: placing the first wafer on a support; abutting against the second wafer by using a thimble; and cutting the first wafer according to the size and the position of the circuit.

Clause A8. the process of clause A1, further comprising: and plastically packaging the first crystal grains by adopting a molding packaging process.

Clause A9. the process of clause A8, further comprising: grinding the first crystal grains after plastic packaging; and chemically and mechanically polishing the flattened first crystal grains.

Clause a10. A computer readable storage medium having stored thereon computer program code of the back-to-back stacking process method, the computer program code, when executed by a processing device, performing the process method of any one of clauses A1 to 9.

Clause a11. A computer program product comprising a computer program for a back-to-back stacking process, wherein the computer program when executed by a processor implements the steps of the method of any of clauses A1 to 9.

Clause a12. A computer device comprising a memory, a processor and a computer program stored on the memory, wherein the processor executes the computer program to implement the steps of the method of any one of clauses A1 to 9.

The above embodiments of the present invention are described in detail, and the principle and the implementation of the present invention are explained by applying specific embodiments, and the above description of the embodiments is only used to help understanding the method of the present invention and the core idea thereof; meanwhile, for a person skilled in the art, according to the idea of the present invention, the specific embodiments and the application range may be changed, and in summary, the content of the present specification should not be construed as a limitation to the present invention.

Claims (12)

1. A method of fabricating a back-to-back stack, comprising:

forming a circuit on the logic side of the first wafer;

turning over the first wafer;

bonding a second wafer on the logic side;

exposing the first through-silicon-via to an opposite side relative to the logic side;

cutting the first wafer into a plurality of first crystal grains;

turning over the first crystal grain; and

and attaching the opposite sides of the first crystal grain and the second crystal grain to ensure that the first through silicon via is electrically communicated with the second through silicon via of the second crystal grain.

2. The process of claim 1, wherein said step of forming a circuit comprises:

forming a front process layer on the logic side;

forming a first through silicon via on the logic side; and

forming a next process layer on the logic side;

the first through silicon via is electrically connected with the subsequent process layer.

3. The process method of claim 1, further comprising:

testing the first wafer to eliminate defective products;

and the step of turning over the first wafer only turns over the first wafer which is not eliminated.

4. The process method of claim 1, wherein said exposing step comprises:

grinding the opposite sides of the first wafer; and

and chemically and mechanically polishing the opposite side of the ground first wafer.

5. The process method of claim 4, wherein said exposing step further comprises:

and plasma etching the opposite side of the first wafer after chemical mechanical polishing to enable the first through silicon via to protrude out of the surface of the opposite side of the first wafer.

6. The process of claim 5, wherein said exposing step further comprises:

depositing silicon dioxide on the surface after plasma etching by using low-temperature chemical vapor deposition; and

and chemically and mechanically polishing the surface after the low-temperature chemical vapor deposition to expose the first through silicon via.

7. The process method of claim 1, wherein said cutting step comprises:

placing the first wafer on a support;

pushing the second wafer by using a thimble; and

and cutting the first wafer according to the size and the position of the circuit.

8. The manufacturing method of claim 1, further comprising:

and plastically packaging the first crystal grains by adopting a molding packaging process.

9. The manufacturing method of claim 8, further comprising:

grinding the first crystal grains after plastic packaging; and

and chemically and mechanically polishing the flattened first crystal grains.

10. A computer readable storage medium having stored thereon computer program code for a back-to-back stacking process method, the computer program code when executed by a processing device performing the process method of any of claims 1-9.

11. A computer program product comprising a computer program for a back-to-back stacking process, wherein the computer program when executed by a processor implements the steps of the method of any of claims 1 to 9.

12. A computer arrangement comprising a memory, a processor and a computer program stored on the memory, wherein the processor executes the computer program to perform the steps of the method of any of claims 1 to 9.

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