CN115374733A - Method and system for analyzing simulation signal - Google Patents

Abstract

The invention provides a method and a system for analyzing simulation signals, wherein the method comprises the following steps: inputting a signal to be sampled, sampling conditions and an inspection file; judging whether a target sampling signal can be found or not, and generating a signal sampling list by using the found target sampling signal; starting simulation signal analysis, and collecting signals in a signal sampling list according to sampling conditions; and checking the sampling result and outputting the sampling result. The simulation signal analysis method, the simulation signal analysis system, the storage medium and the simulation signal analysis equipment are independent of a verification environment, so that the simulation analysis time in the front-end verification process of the chip can be effectively accelerated, and the verification period is shortened.

Description

Method and system for analyzing simulation signal

Technical Field

The invention relates to the technical field of electronics, in particular to a method, a system, a storage medium and equipment for simulating signal analysis.

Background

With the rapid development of large-scale integrated circuits, the complexity of each module of the chip and the whole SOC (system on chip) is gradually increased, which is a more serious challenge for the chip design and verification personnel. After a chip designer writes corresponding design codes according to the architecture of the whole chip, in order to ensure the completeness and reliability of chip design, chip verification personnel need to use various methods to carry out testing, and nowadays when each module of the chip is more and more complicated, signal analysis required in the testing process is more and more complicated.

Conventional signal analysis generally adds relevant signal check directly in test cases or performs assertion check using SVAs (systematic verilog Assertions, language Assertions for hardware design and verification), and when a large amount of signal analysis is encountered, a mode of directly viewing waveforms through VCS (compiled verilog simulator) simulation may be used. The methods have certain disadvantages, although a certain signal can be accurately analyzed by adding inspection or using SVA assertion form inspection in a test case, the signals in a large batch are difficult to cover, both the inspection and the inspection depend on a simulation environment, and if the related inspection needs to be changed, recompilation can be performed to take effect, so that the inspection efficiency of a verifier is reduced; if the VCS waveform is directly checked, although all the required signals can be analyzed at the same time, it is difficult to ensure the correctness of the check due to the visual check.

Therefore, in order to solve the above problems, a novel method and platform for analyzing an emulation signal are needed, which are expected to be independent of the verification environment, and can effectively accelerate the time for analyzing the emulation signal during the front-end verification process of the chip, and shorten the verification period.

Disclosure of Invention

In view of the above, the present invention is directed to an improved method, system, storage medium and device for analyzing an emulated signal, which are independent of a verification environment, and can effectively accelerate the time for analyzing the emulated signal during the front-end verification of a chip, and shorten the verification period.

In view of the above objects, in one aspect, the present invention provides a method for simulation signal analysis, the method comprising:

inputting a signal to be sampled, sampling conditions and an inspection file;

judging whether a target sampling signal can be found or not, and generating a signal sampling list by using the found target sampling signal;

starting simulation signal analysis, and acquiring signals in the signal sampling list according to the sampling conditions; and

and checking the sampling result and outputting the sampling result.

In some embodiments of the method of simulating signal analysis according to the present invention, in the input signal to be sampled, the first parameter is used to specify whether the signal to be sampled is a range signal or a specific signal.

In some embodiments of the method of simulating signal analysis according to the present invention, in case the first parameter is a range signal, the subsequent parameter is an absolute path of the signal to be sampled in a verification environment, and in case the first parameter is a specific signal, the subsequent parameter is a set of signals to be sampled specified according to actual requirements.

In some embodiments of the method of simulating signal analysis according to the invention, in case the first parameter is a range signal,

all signals of the sampling target module are added with an all parameter;

checking input excitation information, and adding an "-input" parameter;

viewing output information, and adding an "-output" parameter;

if the current storage information is checked, adding a memory parameter; and is

Looking at the registry type signal adds the "-reg" parameter.

In some embodiments of the method of simulating signal analysis according to the invention, the sampling conditions comprise:

sampling along with the rising edge of the clock signal, and monitoring the signal change in real time in the whole test case simulation process;

sampling when the reset signal is released, and checking whether the reset value of the signal is correct or not; and

sampling is only performed when a specific signal changes, and whether the excitation condition of the specific signal is in accordance with expectation under the test case is checked.

In some embodiments of the method of simulating signal analysis according to the invention, the check file comprises:

a common rule followed by all signals to be sampled; and

the particular rules to which a particular signal complies.

In some embodiments of the method of simulating signal analysis according to the invention, the sampling result is output in the form of a graphical interface.

In another aspect of the present invention, there is also provided a system for simulating signal analysis, including:

the input module inputs a signal to be sampled, a sampling condition and an inspection file;

the sampling list generation module judges whether a target sampling signal can be found or not and generates a signal sampling list by using the found target sampling signal;

the sampling analysis module starts simulation signal analysis and collects signals in the signal sampling list according to the sampling conditions; and

and the output module checks the sampling result and outputs the sampling result.

In some embodiments of the system for simulating signal analysis according to the present invention, in the signal to be sampled input by the input module, the first parameter is used to specify that the signal to be sampled is a range signal or a specific signal.

In some embodiments of the system for simulating signal analysis according to the invention, in the signal to be sampled input by the input module,

in case the first parameter is a range signal, the subsequent parameter is an absolute path of the signal to be sampled in a verification environment, and

and under the condition that the first parameter is a specific signal, the subsequent parameters are a signal set to be sampled, which is specified according to actual requirements.

In some embodiments of the system for simulating signal analysis according to the present invention, in case the first parameter in the signal to be sampled input by the input module is a range signal,

all signals of the sampling target module are added with an all parameter;

checking input excitation information, and adding an "-input" parameter;

viewing the output information, and adding an "-output" parameter;

adding a "-memory" parameter when checking the current storage information; and is provided with

Looking at the registry type signal adds the "-reg" parameter.

In some embodiments of the system for simulating signal analysis according to the invention, the sampling conditions input by the input module comprise:

sampling along with the rising edge of the clock signal, and monitoring the signal change in real time in the whole test case simulation process;

sampling when the reset signal is released, and checking whether the reset value of the signal is correct or not; and

sampling is only performed when a specific signal changes, and whether the excitation condition of the specific signal is in accordance with expectation under the test case is checked.

In some embodiments of the system for simulating signal analysis according to the invention, the check file input by the input module comprises:

a common rule to which all signals to be sampled adhere; and

the particular rules to which a particular signal complies.

In some embodiments of the system for simulating signal analysis according to the invention, the output module outputs the sampling result in the form of a graphical interface.

In yet another aspect of the present invention, there is also provided a computer readable storage medium storing computer program instructions which, when executed, implement any one of the above methods for simulated signal analysis according to the present invention.

In a further aspect of the present invention, there is also provided a computer device comprising a memory and a processor, the memory having stored therein a computer program which, when executed by the processor, performs any of the above methods of simulated signal analysis according to the present invention.

The invention has at least the following beneficial technical effects: the invention provides a novel, flexible and configurable method, a system, a storage medium and equipment for analyzing simulation signals, which are independent of a TB (Test Bench) platform for chip verification, automatically sample target signals along with the simulation operation of Test cases, can analyze and check the signals according to specified check files and finally output the signals on a graphical interface. The method can effectively shorten the chip verification period, is more convenient and effective to check large-batch signals compared with the traditional signal analysis mode, can add and delete check items at any time without recompilation due to the characteristic of being independent of the verification environment, reduces the verification time, shows sampling results and check results in a graphical interface mode, is more visual than the traditional check mode, and is convenient to check. In conclusion, the method, the system, the storage medium and the device for analyzing the simulation signal can effectively improve the completeness and the reliability of chip design and shorten the verification period.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained according to the drawings without creative efforts.

In the figure:

FIG. 1 shows a schematic block diagram of one embodiment of a method of simulating signal analysis in accordance with the present invention;

FIG. 2 shows a flow diagram of an embodiment of a method of simulating signal analysis according to the invention;

FIG. 3 illustrates one example of a signal to be sampled in a method of simulating signal analysis according to the present invention;

FIG. 4 illustrates one example of sampling conditions in a method of simulating signal analysis according to the present invention;

FIG. 5 illustrates one example of an inspection file in a method of simulating signal analysis according to the present invention;

FIG. 6 shows an example of a display of inspection results in a method of simulated signal analysis according to the invention;

fig. 7 shows an example of a display of a sampling result in the method of simulated signal analysis according to the present invention, in which fig. 7 (a) shows an output format after the simulation ends when sampling is performed according to a clock rising edge, fig. 7 (b) shows an output format after the simulation ends when sampling is released according to a reset signal, and fig. 7 (c), an output format when sampling is performed directly according to a change of a signal;

FIG. 8 shows a schematic block diagram of one embodiment of a system for simulated signal analysis in accordance with the present invention;

FIG. 9 shows a schematic diagram of an embodiment of a computer readable storage medium embodying a method of simulated signal analysis in accordance with the present invention;

fig. 10 shows a hardware configuration diagram of an embodiment of a computer device implementing the method of simulating signal analysis according to the invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.

It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two non-identical entities with the same name or different parameters, and it should be understood that "first" and "second" are only used for convenience of description and should not be construed as limiting the embodiments of the present invention. Furthermore, the terms "comprises" and "comprising," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements does not include all of the other steps or elements inherent in the list.

The inventor finds many problems encountered in the conventional simulation analysis of chip module signals, and the patent provides a novel configurable simulation signal analysis method and platform. The method is independent of a TB verification platform set up by chip verification personnel, and with the simulation operation of the test case, the check items can be added and deleted at any time after the compilation is finished without recompilation. The method and the device automatically sample and record signals according to the signal sampling conditions provided by a user, a list of signals to be analyzed and other information. After the test case simulation is finished, the correctness of the sampled signal value can be checked according to a signal check file provided by a user. And finally, informing the user of the sampling signal and the checking result in a waveform mode so as to facilitate checking.

To solve the problems in the prior art, a first aspect of the present invention provides a method for analyzing a simulation signal. Fig. 1 shows a schematic block diagram of an embodiment of a method of simulating signal analysis according to the present invention. In the embodiment shown in fig. 1, the method comprises the steps of:

step S10: inputting a signal to be sampled, sampling conditions and an inspection file;

step S20: judging whether a target sampling signal can be found or not, and generating a signal sampling list by using the found target sampling signal;

step S30: starting simulation signal analysis, and collecting signals in a signal sampling list according to sampling conditions;

step S40: and checking the sampling result and outputting the sampling result.

Meanwhile, fig. 2 shows a flowchart of an embodiment of the above-described method of simulation signal analysis according to the present invention.

After a verification platform (TB) is built by a verification person at the front end of the chip, a signal to be sampled, a signal sampling condition and an inspection file need to be input according to a specified mode. The sampling signal may be all signals inside a certain module or only a boundary signal, or a certain type of signal may be selected according to signal characteristics, or of course, a certain determination signal may be selected according to requirements of practical applications, and the configuration is flexible. Then, it is determined whether the target sampling signal can be found, and when the target sampling signal can be found, a signal sampling list is generated using the found target sampling signal. In addition, when the target sampling signal cannot be found, the flow returns to the starting point.

And under the condition that the signal sampling list is generated, starting simulation signal analysis, and acquiring signals in the signal sampling list according to sampling conditions. The sampling conditions also need to be flexibly configured according to actual requirements in the actual using process.

And finally, checking the sampling result, outputting the sampling result and ending the process.

In some embodiments of the method 100 of simulating signal analysis according to the present invention, in the input signal to be sampled, the first parameter is used to specify whether the signal to be sampled is a range signal or a specific signal.

Fig. 3 shows an example of a signal to be sampled in a method of simulating signal analysis according to the invention. As shown in fig. 3, the first parameter in the input signal to be sampled is the range signal "-scope" or the specific signal "-signal".

In some embodiments of the method 100 of simulating signal analysis according to the invention, in case the first parameter is a range signal, the subsequent parameter is an absolute path of the signal to be sampled in the verification environment; and when the first parameter is a specific signal, the subsequent parameters are a set of signals to be sampled specified according to actual requirements.

As shown in fig. 3, after "-signal" it is necessary to give an absolute path of a certain signal in the built verification environment, such as xx signal; after "-scope" the set of signals to be sampled can be specified according to the actual requirements.

In some embodiments of a method 100 of simulating signal analysis according to the present invention, as shown in fig. 3, where the first parameter is a range signal,

all signals of the sampling target module are added with an all parameter;

checking input excitation information, and adding an "-input" parameter;

viewing output information, and adding an "-output" parameter;

adding a "-memory" parameter when checking the current storage information; and is

Looking at the registry type signal adds the "-reg" parameter.

The input mode of the scoped signal is consistent with the current design and verification environment, and the types of signals included in systemveilog can be supported, which is not listed here. Meanwhile, the signal to be sampled is input in a range, so that the defect that the traditional mode cannot finish large-batch signal analysis can be avoided, and the sampling of a single signal is compatible on the basis, so that a more flexible and changeable signal analysis platform is realized.

In some embodiments of the method 100 of simulating signal analysis according to the invention, the sampling conditions comprise:

sampling along with the rising edge of the clock signal, and monitoring the signal change in real time in the whole test case simulation process;

sampling when the reset signal is released, and checking whether the reset value of the signal is correct or not;

sampling is only performed when a specific signal changes, and whether the excitation condition of the specific signal is in accordance with expectation under the test case is checked.

Fig. 4 shows an example of sampling conditions in a method of simulating signal analysis according to the invention. The signal sampling conditions are also flexibly configured according to actual requirements, and a few common sampling conditions are listed in the text (see fig. 4):

1) Checking whether the sampling signal has an X state or not;

2) Sampling a boundary signal reset initial value of a certain module, and checking whether the reset initial value is correct or not;

3) And sampling the signal change in the whole simulation process, and checking whether the value change of the signal under a certain excitation is correct or not.

It is noted that the signals to be sampled are shown separately from the signal sampling conditions at the time of enumeration here. However, in practical use, the signals need to be input together, because each group of signals to be sampled needs to provide corresponding signal sampling conditions according to requirements.

In some embodiments of the method 100 of simulating signal analysis according to the invention, examining the file comprises: a common rule followed by all signals to be sampled; and the particular rules to which particular signals adhere.

Fig. 5 shows an example of an examination file in the method of simulating signal analysis according to the invention. The required examination files in the method are divided into two configurations, a common rule for all signals and a specific rule for a certain signal or a certain type of signals.

As shown in fig. 5, "-common" is a common rule, as shown in the figure, that is generally used to check whether the signal has an X state; "signal" is a specific rule that can be used to check whether a signal has reached a certain value, such as sampled signal xx, if value 1234 occurs during sampling, the check is passed, otherwise the corresponding error is reported in the output file.

In some embodiments of the method 100 of simulating signal analysis according to the present invention, the sampling results are output in a graphical interface.

The output result can be divided into two parts, one is the display of the inspection result, and the other is the display of the sampling result, and the two can be shown in a graphical mode, so that the user can conveniently check the result.

Fig. 6 shows an example of a display of the examination result in the method of simulated signal analysis according to the invention. As shown in fig. 6, the main interface will list the inspection result of each signal individually, and after selecting a certain signal, the sampling result of the signal can be viewed.

Fig. 7 shows an example of a display of sampling results in a method of simulating signal analysis according to the invention.

Specifically, fig. 7 (a) shows the output format after the simulation is finished when sampling is performed according to the rising edge of the clock, wherein the xx signal is sampled to the value 1234 at the rising edge of clk (clock) and then sampled to X again, and an error of the X state appears on the output report of the xx signal.

Fig. 7 (b) shows an output format after the end of the simulation when the sampling is released according to the reset signal, in which the reset value of the aa signal is 0 and the reset value of the bb signal is 1 after the release of the reset signal reset.

Fig. 7 (c) shows the output format when sampling is directly performed according to the change of the signal, regardless of the relationship between the signal to be sampled and the rest of the signals, and the output result only shows the process of changing the value of the signal.

According to the method 100 for analyzing the simulation signal, a verification person at the front end of the chip needs to provide a signal to be sampled, a signal sampling condition and an inspection file according to a specified mode after the verification person builds a verification platform. The sampling signal may be all signals inside a certain module or only a boundary signal, or a certain type of signal may be selected according to the signal characteristics, or of course, a certain signal may also be selected according to the own requirements, the configuration is flexible, and the sampling condition also needs to be flexibly configured according to the actual requirements in the actual use process. In addition, the required inspection files in the method are divided into two configurations of common inspection of all signals and specific inspection of a certain signal or a certain type of signals. The output result can be divided into two parts, one is that the inspection result shows, and two are that the sampling result shows, and the both can show with the mode of graphics, and the user of being convenient for looks over.

The invention provides a novel, flexible and configurable simulation signal analysis method, a chip verifier only needs to provide information such as a signal to be analyzed, a sampling condition, relevant inspection and the like according to a specified mode, simulation signal analysis of a chip module can be completed, and an analysis result and a sampling result are finally displayed on a graphical interface. The sampling and analysis of the signals can be completed outside the verification TB environment through the provided information such as the signals to be analyzed, the sampling conditions, the related checks and the like. A good solution is provided for the analysis of a large number of signals, the signals can be divided according to categories, and the required signal analysis requirements can be met. And the analysis result of each signal is displayed item by item through a graphical interface, and meanwhile, the sampling graph is hidden behind the analysis result, so that the analysis result is convenient for a user to check.

In a second aspect of the present invention, a system 20 for simulating signal analysis is also provided. Fig. 8 shows a schematic block diagram of an embodiment of a system for simulated signal analysis according to the present invention. As shown in fig. 8, the system includes the following modules:

an input module 21, wherein the input module 21 inputs a signal to be sampled, a sampling condition and an inspection file;

a sampling list generating module 22, wherein the sampling list generating module 22 judges whether the target sampling signal can be found, and generates a signal sampling list by using the found target sampling signal;

the sampling analysis module 23, the sampling analysis module 23 starts the simulation signal analysis, and collects the signals in the signal sampling list according to the sampling conditions;

and an output module 24, wherein the output module 24 checks the sampling result and outputs the sampling result.

In some embodiments of the system 200 for simulating signal analysis according to the present invention, the first parameter is used to specify that the signal to be sampled is a range signal or a specific signal among the signals to be sampled input by the input module 21.

In some embodiments of the system 200 for simulating signal analysis according to the present invention, in the signal to be sampled input by the input module 21, in the case that the first parameter is a range signal, the subsequent parameter is an absolute path of the signal to be sampled in the verification environment; and when the first parameter is a specific signal, the subsequent parameters are a set of signals to be sampled specified according to actual requirements.

In some embodiments of the system 200 for simulated signal analysis according to the present invention, in the case that the first parameter in the signal to be sampled input by the input module 21 is a range signal, all signals of the sampling target module are added with an "-all" parameter; checking input excitation information, and adding an "-input" parameter; viewing output information, and adding an "-output" parameter; adding a "-memory" parameter when checking the current storage information; and looking at the registry type signal adds the "-reg" parameter.

In some embodiments of the system 200 for simulating signal analysis according to the present invention, the sampling conditions input by the input module 21 include: sampling along with the rising edge of the clock signal, and monitoring the signal change in real time in the whole test case simulation process; sampling when the reset signal is released, and checking whether the reset value of the signal is correct or not; sampling is only performed when a specific signal changes, and whether the excitation condition of the specific signal is in accordance with expectation under the test case is checked.

In some embodiments of the system 200 for simulated signal analysis according to the present invention, the check file input by the input module 21 comprises: a common rule followed by all signals to be sampled; and the particular rules to which particular signals adhere.

In some embodiments of a system 200 for simulating signal analysis according to the present invention, the output module 24 outputs the sampling results in a graphical interface.

In a third aspect of the embodiment of the present invention, a computer-readable storage medium is further provided, and fig. 9 is a schematic diagram of the computer-readable storage medium illustrating a method for simulating signal analysis according to the embodiment of the present invention. As shown in fig. 9, the computer-readable storage medium 300 stores computer program instructions 310, the computer program instructions 310 being executable by a processor. The computer program instructions 310, when executed, implement the method of any of the embodiments described above.

It is to be understood that all embodiments, features and advantages as set forth above for the method of simulated signal analysis according to the invention apply equally to the system and the storage medium of simulated signal analysis according to the invention without conflicting with each other.

In a fourth aspect of the embodiments of the present invention, there is further provided a computer device 400, including a memory 420 and a processor 410, where the memory stores therein a computer program, and the computer program, when executed by the processor, implements the method of any one of the above embodiments.

Fig. 10 is a schematic hardware configuration diagram of an embodiment of a computer device for executing the method for analyzing the simulation signal according to the present invention. Taking the computer device 400 shown in fig. 10 as an example, the computer device includes a processor 410 and a memory 420, and may further include: an input device 430 and an output device 440. The processor 410, the memory 420, the input device 430, and the output device 440 may be connected by a bus or other means, such as the bus connection shown in fig. 10. Input device 430 may receive input numeric or character information and generate a signal input related to the analysis of the simulated signal. The output device 440 may include a display device such as a display screen.

The memory 420 is used as a non-volatile computer-readable storage medium, and can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as program instructions/modules corresponding to the resource monitoring method in the embodiments of the present application. The memory 420 may include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data area may store data created by use of the resource monitoring method, and the like. Further, the memory 420 may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid state storage device. In some embodiments, memory 420 may optionally include memory located remotely from processor 410, which may be connected to local modules via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

The processor 410 executes various functional applications of the server and data processing by executing nonvolatile software programs, instructions and modules stored in the memory 420, that is, implements the resource monitoring method of the above-described method embodiment.

Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosed embodiments of the present invention.

Finally, it should be noted that the computer-readable storage medium (e.g., memory) herein can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory. By way of example, and not limitation, nonvolatile memory can include Read Only Memory (ROM), programmable ROM (PROM), electrically Programmable ROM (EPROM), electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM), which can act as external cache memory. By way of example and not limitation, RAM may be available in a variety of forms such as synchronous RAM (DRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchlink DRAM (SLDRAM), and Direct Rambus RAM (DRRAM). The storage devices of the disclosed aspects are intended to comprise, without being limited to, these and other suitable types of memory.

The various illustrative logical blocks, modules, and circuits described in connection with the disclosure herein may be implemented or performed with the following components designed to perform the functions herein: a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination of these components. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP, and/or any other such configuration.

The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.

It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items. The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.

Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.

Claims (10)

1. A method of simulated signal analysis, comprising the steps of:

inputting a signal to be sampled, sampling conditions and an inspection file;

judging whether a target sampling signal can be found or not, and generating a signal sampling list by using the found target sampling signal;

starting simulation signal analysis, and acquiring signals in the signal sampling list according to the sampling conditions; and

and checking the sampling result and outputting the sampling result.

2. The method of claim 1, wherein the first parameter is used to specify that the signal to be sampled is a range signal or a specific signal in the input signal to be sampled.

3. The method of claim 2,

in the case where the first parameter is a range signal, the subsequent parameter is an absolute path of the signal to be sampled in a verification environment, and

and under the condition that the first parameter is a specific signal, the subsequent parameters are a signal set to be sampled, which is specified according to actual requirements.

4. The method of claim 2, wherein, in the case where the first parameter is a range signal,

all signals of the sampling target module are added with an all parameter;

checking input excitation information, and adding an "-input" parameter;

viewing output information, and adding an "-output" parameter;

adding a "-memory" parameter when checking the current storage information; and is

Looking at the registry type signal adds the "-reg" parameter.

5. The method of claim 1, wherein the sampling conditions comprise:

sampling along with the rising edge of the clock signal, and monitoring the signal change in real time in the whole test case simulation process;

sampling when the reset signal is released, and checking whether the reset value of the signal is correct or not; and

sampling is only performed when a specific signal changes, and whether the excitation condition of the specific signal is in accordance with expectation under the test case is checked.

6. The method of claim 1, wherein the checking the file comprises:

a common rule followed by all signals to be sampled; and

the particular signal complies with the particular rules.

7. A system for simulating signal analysis, comprising:

the input module inputs a signal to be sampled, a sampling condition and an inspection file;

the sampling list generation module judges whether a target sampling signal can be found or not and generates a signal sampling list by using the found target sampling signal;

the sampling analysis module starts simulation signal analysis and collects signals in the signal sampling list according to the sampling conditions; and

and the output module checks the sampling result and outputs the sampling result.

8. The system of claim 7, wherein the first parameter is used to specify that the signal to be sampled is a range signal or a specific signal in the signal to be sampled input by the input module.

9. The system of claim 8, wherein, in the signal to be sampled input by the input module,

in the case where the first parameter is a range signal, the subsequent parameter is an absolute path of the signal to be sampled in a verification environment, and

and under the condition that the first parameter is a specific signal, the subsequent parameters are a signal set to be sampled, which is specified according to actual requirements.

10. The system of claim 7, wherein the sampling conditions input by the input module comprise:

sampling along with the rising edge of the clock signal, and monitoring the signal change in real time in the whole test case simulation process;

sampling when the reset signal is released, and checking whether the reset value of the signal is correct or not; and

sampling is only performed when a specific signal changes, and whether the excitation condition of the specific signal is in accordance with expectation under the test case is checked.

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