CN114662427A

CN114662427A - Debugging method and device for logic system design

Info

Publication number: CN114662427A
Application number: CN202210220089.7A
Authority: CN
Inventors: 黄世杰
Original assignee: Xinhuazhang Technology Co ltd
Current assignee: Xinhuazhang Technology Co ltd
Priority date: 2022-03-08
Filing date: 2022-03-08
Publication date: 2022-06-24
Anticipated expiration: 2042-03-08
Also published as: CN114662427B

Abstract

The present disclosure provides a debugging method and apparatus for logic system design. The method comprises the following steps: reading a first log file obtained by simulating the logic system design at a first configuration, the first log file comprising first simulation information of a plurality of first simulation events, each of the first simulation events comprising at least one of a timing of the first simulation event, a plurality of signals in the first simulation event, or values of the plurality of signals at the timing; extracting first simulation information of the plurality of first simulation events; and generating a first oscillogram of a target signal in the plurality of signals according to the first simulation information, wherein the first log file is in a text format.

Description

Debugging method and device for logic system design

Technical Field

The present disclosure relates to the field of chip design technologies, and in particular, to a method and an apparatus for debugging a logic system design.

Background

In the design of logic systems, the logic system design needs to be tested and verified. When a user verifies a logic system design, the logic system design always needs to be simulated by a simulation tool. The simulation tool uses a test platform (testbench) to verify the logic system design. Accordingly, the logic system Design being tested in the simulation tool may also be referred to as a Design Under Test (DUT).

In general, a test platform may apply stimuli to a DUT in accordance with predetermined test cases, read corresponding test results from the DUT, and generate log (log) files. The user can then determine whether the verification of the logic system design was successful based on the information in the log file.

Manually reviewing the log file is very time consuming.

Disclosure of Invention

In view of the above, the present disclosure provides a debugging method, device and storage medium for logic system design.

In a first aspect of the present disclosure, a method for debugging a logic system design is provided, including: reading a first log file obtained by simulating the logic system design at a first configuration, the first log file comprising first simulation information of a plurality of first simulation events, each of the first simulation events comprising at least one of a timing of the first simulation event, a plurality of signals in the first simulation event, or values of the plurality of signals at the timing; extracting first simulation information of the plurality of first simulation events; and generating a first waveform diagram of a target signal in the plurality of signals respectively according to the first simulation information, wherein the first log file is in a text format.

In a second aspect of the present disclosure, there is provided a debugging device for a logic system design, including: a memory storing a computer program; and a processor configured to execute the computer program to implement the method of the first aspect.

In a third aspect of the disclosure, a non-transitory computer-readable storage medium is provided, which stores a set of instructions of an electronic device for causing the electronic device to perform the method according to the first aspect.

The debugging method and the debugging device for the logic system design have the advantages that the log file is converted into the oscillogram from the text format, machine learning is carried out by utilizing the oscillogram, so that errors or abnormal points are preliminarily determined, and the burden of manually consulting the log file is reduced. As the processing of the machine learning on the graph becomes more mature, the existing machine learning algorithm can be fully utilized by converting the log file in the text format into the oscillogram, and the advantage of the machine learning on the graph processing is exerted. Meanwhile, since recording and reading the waveform file in the simulation process is a very time-consuming operation, and generating the waveform map from the log file may not require additional loading of the waveform file, an error or abnormal point may be quickly determined compared to recording and reading the waveform file.

On the other hand, in a test environment, not all signals can obtain a waveform diagram by loading waveforms, but simulation results of all signals can be printed in a log file. Based on the method provided by the present disclosure, a waveform diagram of the signal which cannot be obtained by loading the waveform can be generated.

Drawings

In order to more clearly illustrate the present disclosure or the technical solutions in the prior art, the drawings needed for the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only the present disclosure, and other drawings can be obtained by those skilled in the art without inventive efforts.

Fig. 1 illustrates a schematic structural diagram of an exemplary device provided in accordance with an embodiment of the present disclosure.

FIG. 2 shows a schematic diagram of an exemplary simulation tool and debugging tool in accordance with an embodiment of the present disclosure.

FIG. 3A illustrates a partial schematic of a first log file according to an embodiment of the disclosure.

Fig. 3B illustrates a schematic diagram of a waveform diagram corresponding to a target signal in a first log file according to an embodiment of the disclosure.

Fig. 4A illustrates a schematic diagram of training of a machine learning model according to an embodiment of the present disclosure.

FIG. 4B shows a schematic diagram of simulation results predicted using a machine learning model, according to an embodiment of the disclosure.

Fig. 4C shows a schematic diagram of clustering a plurality of waveform graphs according to an embodiment of the present disclosure.

Fig. 5A illustrates a flow diagram of an exemplary debugging method in accordance with an embodiment of the present disclosure.

Fig. 5B illustrates a flow diagram of yet another example debugging method in accordance with an embodiment of the present disclosure.

Detailed Description

For the purpose of promoting a better understanding of the objects, aspects and advantages of the present disclosure, reference is made to the following detailed description taken in conjunction with the accompanying drawings.

It is to be noted that technical or scientific terms used herein should have the ordinary meaning as understood by those of ordinary skill in the art to which this disclosure belongs, unless otherwise defined. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

Logic system designs (e.g., integrated circuit chip designs) require multiple verifications before being finalized for production. Verification of the logic system design may be accomplished by using one or more Field Programmable Gate Arrays (FPGAs) to simulate (emulate) the logic system design. The log file can be obtained by running the simulated logic design system on the FPGA so that a user can check the simulation result.

In the process of executing simulation, errors or exceptions inevitably occur, and at this time, a user is required to find the error or exception point from a log file obtained by simulation and then correspond to the error in the logic system design. As described above, the task of finding the outlier from the log file is often performed manually by the user, which is time-consuming and labor-consuming.

According to the debugging method and device for the logic system design, the log file is converted into the oscillogram from the text format, machine learning is carried out by using the oscillogram, so that errors or abnormal points are preliminarily determined, and the burden of manually consulting the log file is reduced. As the processing of the machine learning on the graph becomes more mature, the existing machine learning algorithm can be fully utilized by converting the log file in the text format into the oscillogram, and the advantage of the machine learning on the graph processing is exerted. Meanwhile, since recording and reading the waveform file in the simulation process is a very time-consuming operation, and generating the waveform map from the log file may not require additional loading of the waveform file, an error or abnormal point may be quickly determined compared to recording and reading the waveform file.

On the other hand, in a test environment, not all signals can obtain a waveform diagram by loading waveforms, but simulation results of all signals can be printed in a log file. The debugging method for the logic system design can generate the waveform diagram of the signal which cannot acquire the waveform diagram in a waveform loading mode.

In view of the foregoing problems, the present disclosure provides a debugging method and apparatus for logic system design.

Fig. 1 shows a schematic structural diagram of an exemplary device 100 according to an embodiment of the present disclosure.

The device 100 may be, for example, a host computer. The apparatus 100 may comprise: a processor 102, a memory 104, a network interface 106, a peripheral interface 108, and a bus 110. Wherein processor 102, memory 104, network interface 106, and peripheral interface 108 may be communicatively coupled to each other within device 100 via bus 110.

Processor 102 may be a Central Processing Unit (CPU), an image processor, a neural network processor, a microcontroller, a programmable logic device, a digital signal processor, an Application Specific Integrated Circuit (ASIC), or one or more Integrated circuits. The processor 102 may be used to perform functions related to the techniques described in this disclosure. In some embodiments, processor 102 may also include multiple processors integrated into a single logic component. As shown in FIG. 1, the processor 102 may include a plurality of processors 102a, 102b, and 102 c.

The memory 104 may be configured to store data (e.g., instruction sets, computer code, intermediate data, log files, etc.). For example, as shown in fig. 1, the stored data may include program instructions (e.g., for implementing techniques of this disclosure) as well as log files (e.g., memory 104 may store log files in text format resulting from the emulation). The processor 102 may also access stored program instructions and log files and execute the program instructions to operate on the log files. The memory 104 may include a non-transitory computer readable storage medium, such as a volatile memory device or a non-volatile memory device. In some embodiments, the memory 104 may include Random Access Memory (RAM), Read Only Memory (ROM), optical disks, magnetic disks, hard disks, Solid State Disks (SSDs), flash memory, memory sticks, and the like.

The network interface 106 may be configured to enable the apparatus 100 to communicate with one or more other external devices via a network. The network may be any wired or wireless network capable of transmitting and/or receiving data. For example, the network may be a wired network, a local wireless network (e.g., bluetooth, WiFi, Near Field Communication (NFC), etc.), a cellular network, the internet, or a combination of the above. It is to be understood that the type of network is not limited to the specific examples described above. In some embodiments, network interface 106 may include any combination of any number of Network Interface Controllers (NICs), radio frequency modules, transceivers, modems, routers, gateways, adapters, cellular network chips, and the like.

Peripheral interface 108 may be configured to connect apparatus 100 with one or more peripheral devices to enable input and output of information. For example, the peripheral devices may include input devices such as a keyboard, mouse, touch pad, touch screen, microphone, various sensors, and output devices such as a display, speaker, vibrator, indicator light.

The bus 110 may be configured to transfer information between various components of the device 100 (e.g., the processor 102, the memory 104, the network interface 106, and the peripheral interface 108), and may be, for example, an internal bus (e.g., a processor-memory bus), an external bus (a USB port, a PCI-E bus), etc.

In some embodiments, in addition to the processor 102, memory 104, network interface 106, peripheral interface 108, and bus 110 illustrated in fig. 1 and described above, the device 100 may include one or more other components necessary to achieve normal operation and/or one or more other components necessary to achieve the solutions of the embodiments of the present disclosure. In some embodiments, device 100 may not include one or more of the components shown in fig. 1.

It should be noted that although the above-mentioned constituent architecture of the device 100 only shows the processor 102, the memory 104, the network interface 106, the peripheral interface 108 and the bus 110, in a specific implementation process, the constituent architecture of the device 100 may also include other components necessary for normal operation. In addition, those skilled in the art will appreciate that the above-described constituent architecture of the apparatus 100 may only include the components necessary to implement the embodiments of the present disclosure, and not necessarily all of the components shown in the figures.

FIG. 2 shows a schematic diagram of an exemplary simulation tool 202 and debugging tool 200, according to an embodiment of the present disclosure. Simulation tool 202 and debugging tool 200 may be computer programs running on device 100.

In the field of chip design, a design may be simulated using a simulation tool. The simulation tool may be, for example, a GalaxSim simulation tool available from Chihua chapter science and technology, Inc. The example simulation tool 202 shown in FIG. 2 may include a compiler 120 and a simulator 220. Compiler 120 may compile logic system design 210 into object code 204 and simulator 220 may simulate from object code 204 and output simulation result 206. For example, the simulation tool 202 may output the simulation results 206 (e.g., a log file resulting from the simulation) onto an output device (e.g., displayed on a display) via the peripheral interface 108 of FIG. 1.

The debug tool 200 may also read the simulation results 206. For example, debug tool 200 may read simulation results 206 stored in the form of a log file for debugging. Debug tool 200 can also read a description of logic system design 210 (typically SystemVerilog and Verilog code) and display (e.g., via the output device of FIG. 1) to a user. The debugging tool 200 may also generate various graphical interfaces to facilitate the debugging work of the user. The user may issue a debug command 208 to the debug tool 200 (e.g., run the verification system 210 to a certain point), which the debug tool 200 then applies to the simulation tool 202 to execute accordingly.

It will be appreciated that in addition to interfacing with a software simulation tool (e.g., Galaxsim), the debug tool 200 may also interface with a hardware simulation tool (emulator) for debugging.

FIG. 3A illustrates a partially schematic diagram of a first log file 300 according to an embodiment of the disclosure. It will be appreciated that the first log file 300 shown in FIG. 3A includes only a portion of the simulation information for clarity of presentation.

In some embodiments, a user may utilize simulation tool 202 to perform a simulation operation on a logic system design in a first configuration. The simulation of the logic system design may be performed in different configurations. Configurations (e.g., first configurations) in the present disclosure may include environmental parameters, descriptions of logic system designs, or configurations and parameters of simulation tools, among others. After the simulation is complete, the simulation tool 202 may output the first log file 300 as the simulation results 206. The first log file 300 may be stored in a text format in the memory 104 of the device 100 for reading and further processing by the commissioning tool 200.

As shown in FIG. 3A, the first log file 300 may include first simulation information (e.g., simulation information 301) for a plurality of first simulation events (e.g., simulation events 310 and 320). The first simulation information may include a timing of the first simulation event (e.g., "begin _ time" in simulation event 310), a plurality of signals in the first simulation event (e.g., "a" and "b" in simulation event 310), or values of the plurality of signals at the respective timings (e.g., "value" in simulation event 310), and so on.

Accordingly, the debugging tool 200 can extract the above-mentioned simulation information of a plurality of simulation events from the read first log file 300.

In some embodiments, the simulation event 310 includes multiple signals, one of which may be selected by the user as the target signal (e.g., signal "a").

FIG. 3B shows a schematic diagram of a waveform diagram 302 corresponding to a target signal "a" in a first log file 300, according to an embodiment of the disclosure.

In some embodiments, debugging tool 200 may read emulation information related to target signal "a" in the plurality of emulation events (e.g., "begin _ time", "value" of the target signal in each emulation event) from first log file 300 and draw a waveform map according to the emulation information. For example, the debugging tool 200 may have the horizontal axis of the timing "begin _ time" and the vertical axis of the Value "of the target signal" a "at the corresponding timing, thereby generating the waveform diagram. The horizontal axis of the waveform chart represents time, and the vertical axis represents numerical values. The waveform diagram corresponds to the simulation result in which the target signal "a" in the first log file 300 is run in time series.

In some embodiments, the debug tool 200 can generate the waveform map directly from the first log file 300. In some embodiments, the debugging tool 200 may store simulation information related to the target signal "a" as waveform data in a specific waveform data format as a waveform file. When it is desired to generate a waveform map, the debugging tool 200 can read the waveform file and generate the waveform map according to the waveform data in the waveform file.

In this way, the debugging tool 200 can generate a waveform diagram of the target signal "a" in the first configuration according to the first log file 300.

It is understood that the debugging tool 200 can also generate a plurality of waveform diagrams of other signals in the first configuration according to the first log file 300.

In some embodiments, the user may also utilize simulation tool 202 to perform simulation operations on the logic system design in the second configuration. After the simulation is complete, the simulation tool 202 may output a second log file as the simulation result 206. The simulation event of the second log file includes the same target signal "a" as in the first log file 300. Debug tool 200 may read the second log file, extract emulation information related to target signal "a" (e.g., "begin _ time", "value" of target signal "a" in each emulation event) from the plurality of emulation events, and draw the second waveform map according to the emulation information.

It is to be appreciated that the above-described reading of the first log file and the second log file by the debugging tool 200 to generate the waveform map is merely an example. The debug tool 200 may also read the log file in other configurations to generate a plurality of waveform maps corresponding to the plurality of signals in the log file.

Fig. 4A shows a schematic diagram of training 400 of a machine learning model according to an embodiment of the present disclosure.

As described above, the debug tool 200 can generate a plurality of waveform maps corresponding to a plurality of signals in the log file. In some embodiments, a user may generate multiple oscillograms for multiple signals from historical debug data and log files. Still further, the debugging tool 200 may determine a simulation result (e.g., simulation success or simulation failure) for each simulation event from the historical debugging data and use the simulation results and corresponding oscillograms for training of the machine learning model.

In some embodiments, the debugging tool 200 may generate a waveform map (e.g., the waveform map 302 generated in fig. 3B and further generated

waveform maps

408, 410, etc.) of the target signal (e.g., the signal "a") using the above-described method and receive simulation results (e.g., the simulation results 402, 404, and 406, etc.) corresponding to the waveform map from, for example, a user. The simulation results may include simulation success or simulation failure. In some embodiments, the results of the simulation that were successful in the simulation are used for training, along with the corresponding waveform map.

In some embodiments, the debugging tool 200 may train the machine learning model based on the generated oscillograms and the simulation results corresponding to the oscillograms, thereby obtaining the machine learning model 422 corresponding to the target signal (e.g., signal "a"). In some embodiments, the machine learning model 422 may be a common feature of the oscillogram that extracts the simulation results as success. If the new oscillogram features conform to the common features in the first machine learning model, determining the simulation result as successful; if the new oscillogram features do not conform to the common features in the first machine learning model, the simulation result is determined to be a failure.

It is to be understood that the waveform diagrams 302, 408 and 410 of the target signal and the simulation results 402, 404 and 406 corresponding to the waveform diagrams shown in the embodiments are merely examples. In practical implementation, the debugging tool 200 may also generate a large number of oscillograms and receive simulation results corresponding to the oscillograms for training the machine learning model corresponding to the target signal.

It is to be appreciated that the debugging tool 200 may also train machine learning models corresponding to other target signals.

Fig. 4B shows a schematic diagram of simulation results using machine learning model prediction 410, in accordance with an embodiment of the present disclosure.

In some embodiments, a user may utilize simulation tool 202 to perform simulation operations on a logic system design in a different configuration than the training phase of the machine learning model. After the simulation is complete, the simulation tool 202 may output a log file of the simulation. The simulation event of the log file includes the same target signal "a" as in the log file 300. The debug tool 200 may read the log file and generate the waveform map 412.

In some embodiments, the debugging tool 200 processes the waveform map 412 using a trained machine learning model 422 corresponding to the target signal "a" to obtain the predicted simulation result 408. In some embodiments, simulation results 408 may indicate that there is a failure event for waveform diagram 412. The machine learning model 422 may determine that a "graphic error" exists for a segment or a graphic in the waveform map 412 and further locate the timing of the graphic error. Thus, the user can find the failure event from a plurality of simulation events in the log file according to the given time sequence.

It will be appreciated that the debugging tool 200 may also process the oscillograms of other target signals using a trained plurality of machine learning models corresponding to the other target signals to determine if a failure event exists.

As described above, the debugging tool 200 can find a waveform diagram in which a failure event may exist using a machine learning model corresponding to a target signal. In general, a simulation of a logic system design may produce multiple oscillograms with failure events. Using machine learning models, the debugging tool 200 may identify a very large number of failure events. And some of these failure events may be caused by the same source of error (e.g., design error). Although the machine learning model trained in the embodiments of the present disclosure cannot accurately determine what error source is specific, failure events caused by the same error source may exhibit some of the same characteristics on the waveform map. It is difficult for a human to find these same features by observing multiple oscillograms, however, these same features can be obtained by processing the oscillograms through machine learning, so as to cluster multiple oscillograms with the same features, that is, cluster failure events caused by the same error source. In this way, the efficiency of debugging by a user (e.g., a verification engineer) may be improved.

Fig. 4C shows a schematic diagram of clustering 420 a plurality of waveform graphs, according to an embodiment of the disclosure. The debugging tool 200 may extract graphical features of multiple oscillograms for clustering 420. In some embodiments, the graphical features of the waveform map may be generated in the stage of prediction 410. In some embodiments, graphical features of the waveform map may be generated by the debug tool 200 from the waveform map otherwise.

There may be one or more of the extracted graphical features. The plurality of graphical features may form a feature vector for subsequent processing.

The debugging tool 200 may cluster 420 a plurality of oscillograms based on the graphical features. Clustering 420 may employ one or a combination of the following methods: k-means, mean shift clustering, density-based clustering methods, and the like. It is to be understood that the above clustering method is only exemplary, and those skilled in the art can select a suitable clustering method according to actual needs without being limited to the above examples.

As shown in fig. 4C, the plurality of waveforms may be clustered into at least one group (e.g., group 1, group 2, group 3, and group 4, with the waveforms within the group represented by small dots).

In this way, the embodiment of the present disclosure reduces the burden of manually referring to the log file by converting the log file from a text format to a waveform diagram and performing machine learning using the waveform diagram to preliminarily determine an error or an outlier. Meanwhile, the waveform diagram generated according to the log file can be used without additionally loading the waveform file, so that compared with the method of recording and reading the waveform file, an error or abnormal point can be quickly determined. Still further, some of these errors or outliers may be caused by the same error source and may exhibit some of the same characteristics on the waveform map. These same features may be obtained via machine learning processing of the oscillograms, thereby clustering multiple oscillograms having the same features, i.e., clustering failure events caused by the same error source. In this way, the efficiency of debugging by the user can be improved.

FIG. 5A illustrates a flow chart of a method 500 for debugging a logic system design in accordance with an embodiment of the disclosure. Method 500 may be performed by, for example, device 100 of fig. 1, and more specifically, by commissioning tool 200 running on device 100. The method 500 may include the following steps.

In step S501, the debugging tool 200 can read a first log file (e.g., the first log file 300 shown in fig. 3A). The first log file may be obtained by simulating a logic system design (e.g., logic system design 210 in FIG. 2) in a first configuration. As described above, the configuration (e.g., the first configuration) in the present disclosure may include an environmental parameter, a description of a logic system design, or a configuration and a parameter of a simulation tool, etc. The first log file includes first simulation information (e.g., simulation information 301 in FIG. 3A) for a plurality of first simulation events (e.g., simulation events 310 and 320 in FIG. 3A). Each first simulation event may include at least one of a timing of the first simulation event (e.g., "begin _ time" in simulation events 310 in FIG. 3A), a plurality of signals in the first simulation event (e.g., "a" and "b" in simulation events 310 in FIG. 3A), or a Value of the plurality of signals at the corresponding timing (e.g., "Value" in simulation events 310 in FIG. 3A). The debugging tool 200 may instruct the simulation tool 202 to simulate the design and obtain simulation results (e.g., the first log file 300, etc.).

Wherein the first log file is stored in a memory (e.g., memory 104 of fig. 1) in a textual format.

In step S502, the debugging tool 200 may extract the first simulation information from the read first log file. The first simulation information may include, for example, corresponding values of the target signal at a plurality of timings.

In step S503, the debugging tool 200 may generate a waveform diagram (e.g., the waveform diagram 302 of fig. 3B) of a target signal (e.g., the signal "a" in fig. 3A) in the plurality of signals, respectively, according to the first simulation information (e.g., the simulation information 301).

In some embodiments, the debug tool 200 may generate a waveform diagram (e.g., the waveform diagram 302 shown in FIG. 3B) with the time sequence (e.g., "begin _ time" in the simulation event 310 in FIG. 3A) as the horizontal axis and the Value of the corresponding time sequence (e.g., "Value" in the simulation event 310 in FIG. 3A) as the vertical axis. In some embodiments, the waveform map may be stored in the form of waveform data.

In some embodiments, the waveform map may be stored in a waveform database.

In step S504, the debugging tool 200 may read a second log file obtained by simulating the logic system design in the second configuration. It will be appreciated that the second configuration is different from the first configuration. A second waveform map of the target signal may be generated based on the second log file. The debugging tool 200 performs steps S502 to S503 on the second log file to generate a second waveform diagram (e.g., the waveform diagram 408 in fig. 4A) of the target signal "a".

In step S505, the debugging tool 200 may receive a first simulation result (e.g., the simulation result 402 in fig. 4A) in a first configuration and a second simulation result (e.g., the simulation result 404 in fig. 4A) in a second configuration. Wherein the first and second waveforms (e.g.,

waveforms

302, 408 in fig. 4A) correspond to the first and second simulation results (e.g., simulation results 402, 404 in fig. 4A), respectively. The simulation results may include a simulation success or a simulation failure. It is understood that the debugging tool 200 may generate more waveforms and receive simulation results corresponding to the waveforms.

At step S506, based on at least the first and second oscillograms (e.g.,

oscillograms

302, 408 in fig. 4A) and the first and second simulation results (e.g., simulation results 402, 404 in fig. 4A), the debugging tool 200 may train a first machine learning model (e.g., learning model 422 of fig. 4A) corresponding to the target signal. The first machine learning model may be used to predict a simulation result corresponding to a waveform map of the target signal.

In some embodiments, the first machine learning model may be trained based on a plurality of oscillograms for which the simulation results are successful. It is to be appreciated that the debugging tool 200 can generate a plurality of machine learning models corresponding to a plurality of signals, respectively, for different signals. How the first machine learning model is used to predict the simulation results will be described further below.

Fig. 5B illustrates a flow diagram of a further exemplary debugging method 510 according to an embodiment of the present disclosure. Method 510 may be performed by, for example, device 100 of fig. 1, and more specifically, by debug tool 200 running on device 100. It is understood that method 510 may be performed as a stand-alone method or may be performed as part of method 500. The method 510 may include the following steps.

At step S511, the debugging tool 200 may read the third log file. The third log file is obtained by simulating the logic system design in a third configuration. In some embodiments, the third configuration is different from the first and second configurations. A third waveform diagram for the target signal (e.g., signal "a") may be generated based on the third log file. The debugging tool 200 may perform steps S502 to S503 of the method 500 for the third log file, generating a third waveform diagram (e.g., the waveform diagram 412 in fig. 4B) of the target signal "a".

At step S512, the debugging tool 200 may determine a third simulation result (e.g., the simulation result 408 in fig. 4B) in a third configuration based on the third waveform map (e.g., the waveform map 412 in fig. 4B) using the first machine learning model (e.g., the machine learning model 422 in fig. 4A). In some embodiments, simulation results 408 may indicate that there is a failure event for waveform diagram 412.

In step S513, in response to determining that the third simulation result (e.g., simulation result 408 in fig. 4B) is a failure, debugging tool 200 may determine a third failure event among a plurality of third simulation events.

In some embodiments,

methods

500 and 510 may be performed multiple times, such that debugging tool 200 may generate multiple oscillograms for multiple signals based on the third log file, process the multiple oscillograms using multiple machine learning models, and determine multiple target oscillograms for which there are failure events in the multiple oscillograms.

In some embodiments, the debugging tool 200 may also cluster a plurality of target waveforms to cluster the plurality of target waveforms into at least one group, each of the at least one group indicating a source of error that caused the failure event.

Further, some of the failure events described above may be caused by the same source of error (e.g., design error). Although the machine learning model trained in the embodiments of the present disclosure cannot accurately determine what error source is specific, failure events caused by the same error source may exhibit some of the same characteristics on the waveform map. The debugging tool 200 may cluster a plurality of target waveforms to cluster the plurality of target waveforms into at least one group, each of the at least one group corresponding to an error source causing the failure event. In some embodiments, clustering may employ one or more combinations of, for example, K-means, mean-shift clustering, density-based clustering methods, and the like.

The disclosure also provides a debugging device for logic system design. The device may be the device 100 shown in fig. 1. The debugging tool 200 may be configured to execute a computer program stored in the memory 104 to implement a debugging method of a logic system design consistent with the present disclosure, such as one of the exemplary methods described above (e.g., the method 500 shown in fig. 5A or the method 510 shown in fig. 5B). And will not be described in detail herein.

The present disclosure also provides a non-transitory computer-readable storage medium. A non-transitory computer readable storage medium stores a computer program. When executed by the debugging tool 200, the computer program causes the debugging tool to implement a debugging method of a logic system design consistent with the present disclosure, such as one of the exemplary methods described above (e.g., the method 500 shown in FIG. 5A or the method 510 shown in FIG. 5B). And will not be described in detail herein.

Computer-readable media, including both permanent and non-permanent, removable and non-removable media, for storing information may be implemented in any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), Read Only Memory (ROM), Electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), Digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device.

The foregoing description of specific embodiments of the present disclosure has been described. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims may be performed in a different order than in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing may also be possible or may be advantageous.

Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, is limited to these examples; within the idea of the present disclosure, features in the above embodiments or in different embodiments may also be combined, steps may be implemented in any order, and there are many other variations of the different aspects of the present disclosure as described above, which are not provided in detail for the sake of brevity.

In addition, well known power/ground connections to Integrated Circuit (IC) chips and other components may or may not be shown in the provided figures for simplicity of illustration and discussion, and so as not to obscure the disclosure. Furthermore, devices may be shown in block diagram form in order to avoid obscuring the disclosure, and also in view of the fact that specifics with respect to implementation of such block diagram devices are highly dependent upon the platform within which the present disclosure is to be implemented (i.e., specifics should be well within purview of one skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the disclosure, it should be apparent to one skilled in the art that the disclosure can be practiced without, or with variation of, these specific details. Accordingly, the description is to be regarded as illustrative instead of restrictive.

While the present disclosure has been described in conjunction with specific embodiments thereof, many alternatives, modifications, and variations of these embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. For example, other memory architectures (e.g., dynamic ram (dram)) may use the discussed embodiments.

The present disclosure is intended to embrace all such alternatives, modifications and variances which fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalents, improvements, and the like that may be made without departing from the spirit or scope of the disclosure are intended to be included within the scope of the disclosure.

Claims

1. A method of debugging a logic system design, comprising:

reading a first log file obtained by simulating the logic system design at a first configuration, the first log file comprising first simulation information of a plurality of first simulation events, each of the first simulation events comprising at least one of a timing of the first simulation event, a plurality of signals in the first simulation event, or values of the plurality of signals at the timing;

extracting first simulation information of the plurality of first simulation events; and

generating a first waveform diagram of a target signal of the plurality of signals, respectively, according to the first simulation information,

the first log file is in a text format.

2. A debugging method in accordance with claim 1, further comprising:

reading a second log file, wherein the second log file is obtained by simulating the logic system design under a second configuration;

generating a second waveform map of the target signal based on the second log file;

receiving a first simulation result under the first configuration and a second simulation result under the second configuration;

training a first machine learning model corresponding to the target signal based on at least the first and second oscillograms and the first and second simulation results.

3. A debugging method in accordance with claim 2, further comprising:

reading a third log file, wherein the third log file is obtained by simulating the logic system design under a third configuration;

generating a third waveform map of the target signal based on the third log file;

determining, using the first machine learning model, a third simulation result in the third configuration based on the third waveform graph.

4. A debugging method in accordance with claim 3, wherein the third log file comprises a plurality of third simulation events, the debugging method further comprising:

determining a third failure event among the plurality of third simulation events in response to determining that the third simulation result is a failure.

5. A debugging method in accordance with claim 4, further comprising:

generating a plurality of machine learning models corresponding to the plurality of signals;

generating a plurality of oscillograms for the plurality of signals based on the third log file;

processing the plurality of oscillograms using the plurality of machine learning models; and

determining a plurality of target waveforms for which a failure event exists among the plurality of waveforms.

6. A debugging method in accordance with claim 5, further comprising:

clustering the plurality of target waveforms to cluster the target waveforms into at least one group, each of the at least one group corresponding to one error source causing the failure event.

7. A debugging device for a logic system design, comprising:

a memory storing a computer program; and

a processor configured to execute the computer program to implement the method of any of claims 1 to 6.

8. A non-transitory computer readable storage medium storing a set of instructions for an electronic device to cause the electronic device to perform the method of any of claims 1-6.