JPH10154170A - Logical simulation device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a logical simulation device which detects a glitch that occurs within a delta time and verifies its occurrence cause in a short time. SOLUTION: After a glitch detecting means 20 detects a signal line on which a glitch occurs in a delta time, this device 10 interlocks a list displaying means 22, a waveform displaying means 24 and a circuit diagram displaying means 26 through a controlling means 28. The means 22 expands a logical simulation result in a delta time of a signal line on which a glitch occurs at the time when the glitch occurs and performs list display, the means 24 changes or flickers the display color of the logical simulation result of the signal line on which a glitch occurs at the time when the glitch occurs and performs waveform display, and the means 26 changes or flickers the display color of a path that is the occurrence cause of the glitch on the signal line on which the glitch occurs.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a logic simulation apparatus for verifying the function and operation timing of a logic circuit.

[0002]

2. Description of the Related Art For example, in the design of a logic LSI,
First, the function, performance, and the like are determined based on the specifications of a product, and a logic circuit is designed using logic gates, functional blocks, and the like. When the design of the logic circuit is completed, a netlist (circuit connection information) is generated from the logic circuit, and a logic simulation device simulates the logic circuit using the netlist, and its functions, performance, operation timing, and the like are determined. Will be verified.

Basically, a logic simulation apparatus is
The signal value of each signal line at each time is displayed in a list or a waveform at certain time intervals. Here, a set of times at which the signal value of each signal line is displayed is expressed as real time. However, due to its algorithm, the logic simulation device can process only one signal line at a time. That is, if the signal values of a plurality of signal lines change at the same time, these logic lines cannot be processed simultaneously.

For this reason, in a logic simulation apparatus, a plurality of signal lines can be processed at the same time by introducing a virtual time concept called a delta time with respect to the real time described above. I have. That is, within the delta time, a plurality of simultaneously changed signal lines are processed one by one, and the final state of the signal value of each signal line when the processing of all signal lines is completed is changed to the final state at that time in real time. List display and waveform display are performed as signal values of signal lines.

For example, at time t, if the signal values of n signal lines change, first, the delta time Δ1 becomes 1
Processing the second signal line, then the delta time Δ at time t
One signal line is processed every one delta time, such as processing the second signal line in 2, and finally, the nth signal line is processed in the delta time Δn at time t. And
Delta time Δn when processing of signal values of all signal lines is completed
The final state of the signal value of each signal line is the signal value of each signal line at the time t in real time.

As described above, in the conventional logic simulation apparatus, normally, the state change of the signal value of each signal line during the delta time is not displayed, but only the signal value of each signal line at each time in real time is displayed. Is done. For this reason, even if the signal line changes within the delta time, for example, 1 → 0 → 1 or 0 → 1 → 0 and a glitch occurs, the signal value of each signal line at the continuous time of the real time does not change. , It was difficult to detect glitches that occurred within the delta time.

For example, a semiconductor memory is generally configured so that data is written into or read from the semiconductor memory in response to a rise or fall of a read / write signal which is one of control signals. Have been. Therefore, for example, if a glitch occurs in the read / write signal, the operation of the semiconductor memory becomes unstable and there is a risk of malfunction. Therefore, it is important to detect the occurrence of glitch by logic simulation and analyze the cause of the glitch. .

For this reason, for example, by providing an option command or the like in the logic simulation device, the state change of the signal value of each signal line during the delta time is displayed, and it is visually confirmed whether or not a glitch has occurred. Some are configured. However, when the state change of the signal value of each signal line during the delta time is displayed, the list display becomes long and very complicated, so that there has been a problem that a long time is required to check for the occurrence of a glitch. .

Conventional logic simulation apparatuses are disclosed in, for example, JP-A-4-273581, JP-A-63-254567, and JP-A-3-196270.

First, the timing verification device disclosed in Japanese Patent Application Laid-Open No. 4-273581 displays an error list of the timing verification result for each error, and selects an error to be checked with a cursor as needed, thereby causing an error. In addition to displaying the circuit diagram of the location and its surroundings, it also displays the waveform of the simulation result of the signal line related to the timing error, making it easy to find out the location and the cause of the timing error and reduce the verification time. It can be shortened.

A display device for verifying the design of a logic circuit disclosed in Japanese Patent Application Laid-Open No. 63-254567 discloses an apparatus for verifying a logic circuit design in which the same signal value is applied in accordance with the state of the signal value of each signal line in the logic circuit within a set time. Is the same color, each different signal value is displayed in each different color, and the signal value of each signal line, as well as the change of the signal in each part of the associated signal line Progress can be easily verified,
It says that it can provide a good and effective environment for verification and debugging for designers.

A logic simulation result display device disclosed in Japanese Patent Application Laid-Open No. 3-196270 discloses a logic simulation result display device, in which a node specified by a cursor on a circuit diagram displayed on a circuit display section has an undefined value, The path to the source of the cause of the indefinite value of the node is highlighted on the circuit diagram, and the signal value of this node is displayed as a waveform. The company says that it will be easier and the verification time can be reduced.

As described above, in the conventional logic simulation apparatus, the list display, the waveform display, and the circuit diagram display are linked, the display color of the signal line is changed according to the state of the signal value, and the circuit diagram is set to the high level. The purpose of the light display is to reduce the time required to verify the cause of the error.However, this is related to the verification of the cause of the error that occurred at each time in real time, and occurred within the delta time. Glitch was not considered at all.

[0014]

SUMMARY OF THE INVENTION An object of the present invention is to provide a logic capable of detecting a glitch generated within a delta time and verifying the cause of the glitch in a short time, in consideration of the problems based on the above prior art. It is to provide a simulation device.

[0015]

To achieve the above object, the present invention provides a logic simulation apparatus for processing a plurality of signal lines simultaneously changed at the same time one by one within a delta time. Glitch detection means for detecting a signal line in which a glitch has occurred during time, list display means for expanding and displaying a list of logic simulation results during a delta time of the signal line in which the glitch has occurred at the time when the glitch has occurred, Waveform display means for changing or blinking the display color of the logic simulation result of the signal line where the glitch has occurred at the time when the glitch has occurred, and displaying the waveform, and a path for causing the glitch of the signal line where the glitch has occurred. Circuit diagram display means for changing or blinking a display color and displaying a circuit diagram by flashing, the glitch detection means, the list display means, Control means for controlling the operations of the waveform display means and the circuit diagram display means, and interlocking the list display by the list display means, the waveform display by the waveform display means, and the circuit diagram display by the circuit diagram display means A logic simulation device characterized by the following.

Here, it is preferable that the waveform display means displays a waveform of a glitch generated during the delta time.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a logic simulation apparatus according to the present invention will be described in detail based on a preferred embodiment shown in the accompanying drawings.

FIG. 1 shows a conceptual diagram of an embodiment of the logic simulation apparatus according to the present invention. As shown in the figure,
The logic simulation device 10 of the present invention includes an input device 12, a logic simulator 14, a storage device 16, and a display device 18 in the same manner as a conventional logic simulation device.
And a glitch detection unit 20, a list display unit 22, a waveform display unit 24, a circuit diagram display unit 26, and a control unit 28, which are characteristic parts of the present invention.

In the logic simulation apparatus 10 of the present invention, first, the input device 12, the logic simulator 14,
The storage device 16 and the display device 18 are usually basic components that are also provided in a conventional logic simulation device. Here, the input device 12, the logic simulator 14, and the storage device 16 are connected to the system bus 30, and the display device 18 is connected to the list display means 22, the waveform display means 24, and the circuit diagram display means 26.

The input device 12 is for inputting commands and data such as a mouse and a keyboard, and the logic simulator 14 is for performing a logic simulation and outputting a logic simulation result. Also,
The storage device 16 stores, for example, a logic simulation result and a glitch detection result described later, such as a hard disk, and the display device 18 stores, for example, a CR.
This is for displaying the result of logic simulation, such as a T display.

Next, the glitch detection means 20, the list display means 22, the waveform display means 24, the circuit diagram display means 26 and the control means 28 are characteristic components provided only in the logic simulation apparatus 10 of the present invention. And both are connected to the system bus 30.

Here, the glitch detection means 20 monitors the execution of the logic simulation by the logic simulator 14 or analyzes the logic simulation result stored in the storage device 16 along the flow of the simulation time. Thus, a signal line where a glitch occurs during the delta time is detected, and as a glitch detection result, for example, the name of the signal line where the glitch occurred during the delta time, the time when the glitch occurred, the signal value, and the like are stored. Is held.

Subsequently, after the execution of the logic simulation by the logic simulator 14 is completed, the list display means 22, the waveform display means 24 and the circuit diagram display means 26
Alternatively, after the analysis of the logic simulation result is completed, for example, a list or a waveform around the time when the first glitch occurs on the display device 18 according to the logic simulation result or the glitch detection result stored in the storage device 16, The circuit diagram around the signal line where the glitch has occurred is displayed.

First, the list display means 22 expands the logic simulation result during the delta time and, for example, scrolls and displays the list by scrolling until the time when the first glitch occurs, thereby improving the visibility. In addition, only the logic simulation result of the delta time at the time when the glitch occurs may be developed, or the logic simulation result of the delta time at the entire time may be developed not limited to only the time at which the glitch occurs. Is also good.

FIG. 2 shows a list of one embodiment of the result of the logic simulation. The illustrated list shows an example of a list display of the logic simulation result by the list display unit 22. In the figure, ps is a unit of simulation time (picoseconds), delta is a delta time, rwn, vclk, hs_tim, hs_tim.
_D and q indicate each signal line. In the drawing, U, 1 and 0 mean an undefined state, a logic 1 and a logic 0, respectively.

At 580000 ps in the illustrated list, first, the signal value of the signal line vclk changes from 0 to 1 at the delta time Δ1, and the signal line hs_ at the delta time Δ2.
After the signal value of tim_d changes from 0 to 1, the signal value of the signal line rwn changes from 1 to 0 at the delta time Δ3, and the signal value of the signal line rwn changes from 0 to 1 again at the delta time Δ4. I have. That is, a glitch occurs on the signal line rwn during the delta time of 580000 ps.

The delta time Δ4 at 580000 ps indicates the final state of the signal value of each signal line, and is usually displayed in a list as the signal value of each signal line at 580000 ps in real time. At this time, the signal value of the signal line rwn at the time of 560000 ps, 580000 ps, and 600000 ps in real time is 1, and the signal line rwn changes at the time of 580000 ps unless the delta time is expanded and displayed as a list. You will not.

As described above, in the conventional logic simulation apparatus which displays only the signal value of each signal line at each time in real time, the occurrence of glitches cannot be detected, so that a problem related to glitches of the signal line rwn, for example, occurs. But it was very difficult to even analyze the cause. On the other hand, according to the logic simulation apparatus 10 of the present invention, since the delta time of the time when the glitch occurs is developed and displayed in a list, it is easy to recognize when and on which signal line the glitch occurred. .

Subsequently, the waveform display means 24 displays, for example, a waveform of the result of the logic simulation before and after the time at which the glitch occurred first, and changes the hue, saturation, lightness, etc., for example, to change the signal line on which the glitch occurred. By changing or blinking the display color of the time at which the glitch has occurred, it is easy to confirm the location where the glitch has occurred. In the waveform display before and after the time when the glitch occurs, the glitch may be displayed by reflecting the result of the logic simulation during the delta time.

In the circuit diagram display means 26, for example, a logic circuit around the signal line where the glitch occurs at the time when the glitch first occurs is displayed in a circuit diagram. Change the hue, saturation, lightness, etc. to change the display color of the signal line where the glitch has occurred or the path to the source of the glitch that has occurred on this signal line, or blink By doing so, it is easy to confirm the location where the glitch has occurred.

Finally, the control means 28 responds to a user's instruction through the input device 12 to control the glitch detection means 20,
The operation of the list display means 22, the waveform display means 24 and the circuit diagram display means 26 is controlled, and the result of the logic simulation by the logic simulator 14 and the glitch detection means 20 are controlled.
Display means 2 based on the glitch detection result by
2, the waveform display by the waveform display means 24 and the circuit diagram display by the circuit diagram display means 26 are linked.

For example, if the user uses the input device 12 to select a specific signal line at another time for the list display by the list display means 22, the control means 28
In the waveform display means 24, the logic simulation result of the signal line selected in the list display means 22 before and after the time selected in the list display means 22 is displayed in a waveform, and in the circuit diagram display means 26, The logic circuits around the selected signal line in the list display means 22 are displayed as a circuit diagram.

The time and signal line selected by the list display means 22 are reflected on the waveform display means 24 and the circuit diagram display means 26, and similarly, the time and signal line selected by the waveform display means 24 Is reflected on the list display means 22 and the circuit diagram display means 26. If a glitch has occurred in the selected time or signal line, the logic simulation results during the delta time are expanded and displayed in a list, and the display color of the signal line where the glitch occurred is changed or blinked and displayed as a waveform. Then, the display color of the path which is the cause of the glitch generated in the signal line is changed or blinked and displayed on the circuit diagram.

The logic simulation apparatus 10 of the present invention
Has basically the above configuration.
Next, the operation of the logic simulation apparatus 10 of the present invention will be described with reference to FIGS. 3 and 4, which are flowcharts of an embodiment showing the operation of the logic simulation apparatus 10 of the present invention.

In the logic simulation apparatus 10 according to the present invention, when a logic simulation is started by, for example, the logic simulator 14, first, as shown in the flowchart of FIG. After the signal value of each signal line at the delta time Δ1 is stored in the storage device 16 and then the signal value of each signal line at the delta time Δ2 is stored, the signal value of each signal line at the delta time Δ2 and Previous delta time Δ
1 is compared with the signal value of each signal line.

If the signal value of each signal line at the delta time Δ2 is equal to the signal value of each signal line at the delta time Δ1, the process returns to the previous step, and the signal of each signal line at the next delta time Δ3 is obtained. After the value is stored, the signal value of each signal line of the delta time Δ3 is compared with the signal value of each signal line of the immediately preceding delta time Δ2 so that the next delta time Δ
After the signal value of each signal line of n is stored, the delta time Δn
And the delta time Δ (n
-1) is compared with the signal value of each signal line.

On the other hand, if the signal value of each signal line at the delta time Δ2 is different from the signal value of each signal line at the delta time Δ1, the process proceeds to the next step, and the signal value of each signal line at the delta time Δ2 Is stored, and it is confirmed that the signal value of the signal line whose signal value has changed at the delta time Δ2 has already changed at the current time t. It is confirmed whether or not the signal value of the signal line whose signal value has changed has already changed at the current time t.

Here, if the signal value of the signal line whose signal value has changed at the delta time Δ2 has not changed at the current time t, the process returns to the first step, and the next delta time Δn,
Here, after the signal value of each signal line of the delta time Δ3 is stored, the signal value of each signal line of the delta time Δn and its 1
The signal value of each signal line of the immediately preceding delta time Δ (n−1), here, the delta time Δ2, is compared, and according to the comparison result, the process similarly proceeds to the above-described steps.

Conversely, when the signal value of the signal line whose signal value has changed in the delta time Δ2 has already changed at the current time t, that is, the glitch has occurred in this signal line. If detected, the delta time Δ2 at the current time t is stored as the time at which the glitch occurred, and then the process returns to the first step, and the next delta time Δn
After the signal value of each signal line is stored, the signal value of each signal line at the delta time Δn and the delta time Δ (n−n
The signal value of each signal line of 1) is compared.

Here, when the glitch detection processing for the last delta time at the current time t is completed, the logic simulation proceeds to the next time, and the glitch detection processing is performed at the next time in the same manner. Then, the glitch detection process described above is performed in exactly the same manner at each time until the logic simulation ends. Subsequently, when the logic simulation by the logic simulator 14 is completed, it is confirmed whether or not a glitch has occurred in each signal line.

If no glitch has occurred in each signal line, the process waits until the next operation (instruction) from the user by the input device 12 is given, for example.

On the other hand, if a glitch occurs in any of the signal lines, the control means 28, for example, interlocks the logic simulation result of the signal line in which the glitch occurred at the first time when the glitch occurred. A list display, a waveform display, and a circuit diagram display are displayed, and the user is notified that a glitch has occurred. For example, the list display unit 22 develops a logic simulation result of the signal line where the glitch has occurred at the time when the glitch has occurred during the delta time and displays the result in a list.

The waveform display means 24 displays the waveform of the logic simulation result before and after the time when the glitch occurred, and displays the signal line where the glitch occurred at the time when the glitch occurred in a different color or color from the other signal lines. The circuit is displayed in a blinking manner, and the logic circuit around the signal line where the glitch has occurred is displayed on the circuit diagram by the circuit diagram display means 26. The signal line where the glitch has occurred and the path of the cause of the glitch that has occurred in this signal line are displayed. Displayed in other colors or flashing.

As described above, the logic simulation apparatus of the present invention has been described in detail. However, the present invention is not limited to the above embodiment, and various improvements and modifications may be made without departing from the gist of the present invention. Of course. For example, the glitch detection means 20, the list display means 22, the waveform display means 24, the circuit diagram display means 26, and the control means 2 which constitute characteristic parts of the logic simulation apparatus of the present invention.
The specific circuit configuration of 8 is not limited, and can be realized by software or hardware, or by combining software and hardware.

[0045]

As described above in detail, the logic simulation apparatus of the present invention detects the signal line in which the glitch has occurred during the delta time by the glitch detection means, and then controls the list display means by controlling the control means. The waveform display means and the circuit diagram display means are linked to each other, and the list display means expands the logic simulation result during the delta time of the signal line at which the glitch occurred at the time when the glitch occurred, and displays the list as a list. Change or blink the display color of the logic simulation result of the signal line where the glitch has occurred at the time when the glitch occurred, and display the waveform,
The circuit diagram display means changes or blinks the display color of the path that causes the glitch of the signal line where the glitch has occurred, and displays the circuit diagram by blinking. This makes it easier for the user to identify the signal line where the glitch has occurred during the delta time. In addition, by linking the list display, waveform display, and circuit diagram display, when the glitch occurred on which signal line, which part of the circuit diagram caused the glitch, and the cause of the glitch The user can appropriately recognize which part corresponds to which part, and as a result, the verification time of the cause of the glitch can be reduced, and a highly reliable logic circuit can be designed. .

[Brief description of the drawings]

FIG. 1 is a conceptual diagram of one embodiment of a logic simulation apparatus according to the present invention.

FIG. 2 is a list of one embodiment of a logic simulation result.

FIG. 3 is a flowchart illustrating an operation of the logic simulation apparatus according to the embodiment of the present invention.

FIG. 4 is a flowchart illustrating an operation of the logic simulation apparatus according to the embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 10 logic simulation device 12 input device 14 logic simulator 16 storage device 18 display device 20 glitch detection means 22 list display means 24 waveform display means 26 circuit diagram display means 28 control means 30 system bus

Claims (2)

[Claims] 1. A logic simulation apparatus for processing a plurality of signal lines changed simultaneously at the same time one by one within a delta time, wherein a glitch detection means for detecting a signal line in which a glitch occurs during the delta time. List display means for expanding and displaying a list of logic simulation results during the delta time of the signal line where the glitch occurred at the time when the glitch occurred, and logic simulation of the signal line where the glitch occurred at the time when the glitch occurred Waveform display means for changing or blinking the display color of the result to display a waveform, and circuit diagram display means for changing or blinking the display color of a path that causes glitching of the signal line in which the glitch has occurred, and displaying a circuit diagram by blinking. And the glitch detection means, the list display means,
Control means for controlling the operations of the waveform display means and the circuit diagram display means, and interlocking the list display by the list display means, the waveform display by the waveform display means, and the circuit diagram display by the circuit diagram display means A logic simulation device characterized by the above-mentioned. 2. The logic simulation apparatus according to claim 1, wherein the waveform display means displays a glitch generated during the delta time in a waveform.