CN115371656B - High-speed course digital converter - Google Patents

High-speed course digital converter Download PDF

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Publication number
CN115371656B
CN115371656B CN202211035056.1A CN202211035056A CN115371656B CN 115371656 B CN115371656 B CN 115371656B CN 202211035056 A CN202211035056 A CN 202211035056A CN 115371656 B CN115371656 B CN 115371656B
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China
Prior art keywords
resistor
comparator
circuit
exclusive
chip
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CN115371656A (en
Inventor
吴涛
张心钰
刘川
张俊华
罗先琼
陈耀山
刘益铭
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Csic Chongqing Changping Machinery Co ltd
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Csic Chongqing Changping Machinery Co ltd
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01C—MEASURING DISTANCES, LEVELS OR BEARINGS; SURVEYING; NAVIGATION; GYROSCOPIC INSTRUMENTS; PHOTOGRAMMETRY OR VIDEOGRAMMETRY
    • G01C17/00—Compasses; Devices for ascertaining true or magnetic north for navigation or surveying purposes
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01C—MEASURING DISTANCES, LEVELS OR BEARINGS; SURVEYING; NAVIGATION; GYROSCOPIC INSTRUMENTS; PHOTOGRAMMETRY OR VIDEOGRAMMETRY
    • G01C21/00—Navigation; Navigational instruments not provided for in groups G01C1/00 - G01C19/00
    • G01C21/10—Navigation; Navigational instruments not provided for in groups G01C1/00 - G01C19/00 by using measurements of speed or acceleration
    • G01C21/12—Navigation; Navigational instruments not provided for in groups G01C1/00 - G01C19/00 by using measurements of speed or acceleration executed aboard the object being navigated; Dead reckoning
    • G01C21/16—Navigation; Navigational instruments not provided for in groups G01C1/00 - G01C19/00 by using measurements of speed or acceleration executed aboard the object being navigated; Dead reckoning by integrating acceleration or speed, i.e. inertial navigation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude

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  • Engineering & Computer Science (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Remote Sensing (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Nonlinear Science (AREA)
  • Automation & Control Theory (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

The invention discloses a high-speed course digital converter, which comprises a microprocessor module, a self-angle machine signal circuit, an excitation signal circuit, an analog signal processing circuit, a power failure detection circuit and a data storage circuit, wherein the microprocessor module comprises a digital signal processing circuit and a main control chip; the self-angle machine signal circuit is used for inputting the three-phase analog signals output by the self-angle machine into the analog signal processing circuit; the excitation signal circuit is used for inputting an excitation signal into the analog signal processing circuit; the analog signal processing circuit is used for converting the three-phase analog signals into 6 paths of digital signals under the action of the excitation signals and inputting the 6 paths of digital signals into the digital signal processing circuit; the digital signal processing circuit is used for comparing the input 6 paths of digital signals with a set heading initial value so as to obtain a real-time heading signal. According to the invention, the analog heading value of the electronic compass is converted into the digital heading value, so that the ship signal interaction capability can be greatly improved.

Description

High-speed course digital converter
Technical Field
The invention relates to the technical field of communication navigation, in particular to a high-speed course digitizer.
Background
The electric compass is also called as gyro compass, which can automatically and continuously provide the course signal of the ship and transmit the course signal to each position of the ship where the course signal is needed through the course transmitting device. Thereby meeting the requirements of ship navigation and armaments and military provisions systems, being the essential precise navigation equipment of the ship, and being called as the 'eyes' of the ship.
The electric compass comprises an automatic angle regulator, and when the electric compass transmits a course signal, the analog signal transmitted by the automatic angle regulator is three sine alternating signals which mutually form 120-degree phase. The heading converter is an accessory instrument for intelligent interface of the electronic compass and other devices, and the demands for the heading converter are increasing in the current age with more and more prominent intellectualization.
In the prior art, the course converter directly sends the received analog signals of the self-angle adjusting machine to each instrument needing course signals on the ship, and as the quantity of the instruments needing course signals on the ship is large, and the installation positions of the instruments are far away from the electric compass, the course signals transmitted by the course converter can not meet the needs of the instruments on the ship, meanwhile, the problems of signal loss or distortion and the like can be caused in the long-distance transmission of the analog signals, and the course signals received by the instruments with far installation positions are different from the actual course signals of the ship, so that the navigation of the ship is influenced.
Disclosure of Invention
Aiming at the defects existing in the prior art, the invention aims to solve the technical problems that: how to provide a high-speed course digitizer which can meet the requirements of various instruments on a ship on course signals and can avoid the problems of missing and distortion of course signals during long-distance transmission.
In order to solve the technical problems, the invention adopts the following technical scheme:
the high-speed course digital converter comprises a microprocessor module, a self-angle machine signal circuit, an excitation signal circuit, an analog signal processing circuit, a power failure detection circuit and a data storage circuit, wherein the microprocessor module comprises a digital signal processing circuit and a main control chip;
the output end of the self-angle-setting machine signal circuit is in communication connection with the input end of the analog signal processing circuit and is used for inputting the three-phase analog signals output by the self-angle-setting machine into the analog signal processing circuit;
The output end of the excitation signal circuit is in communication connection with the input end of the analog signal processing circuit, and is used for inputting an excitation signal into the analog signal processing circuit after attenuation and comparison processing;
the output end of the analog signal processing circuit is in communication connection with the input end of the digital signal processing circuit, and is used for converting the three-phase analog signals output by the self-angle adjusting machine into six paths of digital signals under the action of excitation signals and inputting the six paths of digital signals into the digital signal processing circuit;
the digital signal processing circuit is used for comparing the input six paths of digital signals with a set course initial value to obtain a real-time course signal;
the power-down detection circuit is in bidirectional communication connection with the microprocessor module, and is used for comparing the voltage value of the main control chip with a voltage reference value and sending a low-level signal to the main control chip when the voltage value of the main control chip is lower than the voltage reference value;
The data storage circuit is in bidirectional communication connection with the microprocessor module, the data storage circuit stores data when the main control chip receives a low-level signal, and the main control chip reads the data stored in the last power-off state from the data storage circuit when the main control chip is powered on again so as to automatically match course information.
The working principle of the invention is as follows: when the high-speed course digital converter is used, the self-angle machine signal circuit receives three-phase analog signals from the self-angle machine, the self-angle machine signal circuit inputs the received three-phase analog signals of the self-angle machine into the analog signal processing circuit for processing, meanwhile, the analog signal processing circuit also receives the attenuated and compared excitation signals from the excitation signal circuit, the analog signal processing circuit converts the three-phase analog signals output by the self-angle machine into six-way digital signals under the action of the excitation signals and outputs the six-way digital signals to the digital signal processing circuit, the course initial value of a ship is set in the digital signal processing circuit, the digital signal processing circuit compares the received six-way digital signals with the course initial value, and further, the digital real-time course signals of the ship can be obtained, and then the digital real-time course signals are transmitted to various instruments on the ship, and the course information is required to be acquired.
Meanwhile, the navigation digital converter is also provided with the power-down detection circuit and the data storage circuit, the power-down detection circuit can send a low-level signal to the main control chip when power is down so as to save data through the data storage circuit, and when the power is on again, the navigation digital converter can automatically match course information by reading the data saved by last power failure so as to avoid the problem that the course information needs to be matched again after power is off each time.
Preferably, the analog signal processing circuit comprises an attenuation unit, a comparison and subtraction unit and an exclusive-or unit, wherein the attenuation unit is used for carrying out attenuation processing on three-phase analog signals output by the self-angle-setting machine, the comparison and subtraction unit is used for respectively comparing the three-phase analog signals subjected to attenuation processing with a reference value and simultaneously comparing the three-phase analog signals subjected to attenuation processing with each other to output six paths of signals to the exclusive-or unit, and the exclusive-or unit carries out exclusive-or operation on the six paths of digital signals and the excitation signals subjected to attenuation and comparison processing output by the excitation signal circuit and outputs six paths of digital signals to the digital signal processing circuit;
The excitation signal circuit comprises an excitation signal attenuation unit and an excitation signal comparison unit, wherein the excitation signal attenuation unit is used for carrying out attenuation processing on an excitation signal, and the excitation signal comparison unit is used for comparing the excitation signal subjected to attenuation processing with an excitation reference value, carrying out exclusive-or processing on a comparison result and outputting the comparison result to the exclusive-or unit.
Preferably, the attenuation unit includes an a-phase attenuation circuit, a B-phase attenuation circuit and a C-phase attenuation circuit, where the a-phase attenuation circuit includes a capacitor C25, a capacitor C28, a capacitor C29, a resistor R13, a resistor R14, a resistor R17, a resistor R18 and a comparator U6A, where a non-inverting input terminal of the comparator U6A is grounded through the capacitor C25, an inverting input terminal of the comparator U6A is connected to an output terminal, an output terminal of the comparator U6A is simultaneously connected to one end of the capacitor C28 and one end of the capacitor C29, another end of the capacitor C28 and another end of the capacitor C29 are simultaneously connected to one end of the resistor R17, another end of the resistor R17 is connected to a non-inverting input terminal of the comparator U6A, one end of the resistor R13 is connected to an a-phase output terminal of the self-rectifying signal circuit, another end of the resistor R13 is simultaneously connected to one end of the resistor R18 and one end of the resistor R14, and another end of the resistor R14 is grounded, and one end of the resistor R18 is connected to one end of the resistor R17;
The phase B attenuation circuit comprises a capacitor C54, a capacitor C30, a capacitor C31, a resistor R9, a resistor R10, a resistor R19, a resistor R20 and a comparator U6B, wherein the non-inverting input end of the comparator U6B is grounded through the capacitor C54, the inverting input end of the comparator U6B is connected with the output end, the output end of the comparator U6B is simultaneously connected with one end of the capacitor C30 and one end of the capacitor C31, the other end of the capacitor C30 and the other end of the capacitor C31 are simultaneously connected with one end of the resistor R19, the other end of the resistor R19 is connected with the non-inverting input end of the comparator U6B, one end of the resistor R9 is simultaneously connected with one end of the resistor R10 and one end of the resistor R20, the other end of the resistor R10 is grounded, and the other end of the resistor R20 is connected with one end of the resistor R19;
The C-phase attenuation circuit comprises a capacitor C55, a capacitor C32, a capacitor C33, a resistor R11, a resistor R12, a resistor R21, a resistor R22 and a comparator U6C, wherein the non-inverting input end of the comparator U6C is grounded through the capacitor C55, the inverting input end of the comparator U6C is connected with the output end, the output end of the comparator U6C is simultaneously connected with one end of the capacitor C32 and one end of the capacitor C33, the other end of the capacitor C32 and the other end of the capacitor C33 are simultaneously connected with one end of the resistor R21, the other end of the resistor R21 is connected with the non-inverting input end of the comparator U6C, one end of the resistor R11 is connected with the C-phase output end of the self-rectifying machine signal circuit, the other end of the resistor R11 is simultaneously connected with one end of the resistor R12 and one end of the resistor R22, and the other end of the resistor R12 is grounded, and the other end of the resistor R22 is connected with one end of the resistor R21;
The excitation signal attenuation unit comprises a capacitor C56, a capacitor C34, a capacitor C35, a resistor R15, a resistor R16, a resistor R23, a resistor R24 and a comparator U6D, wherein the non-inverting input end of the comparator U6D is grounded through the capacitor C56, the inverting input end of the comparator U6D is connected with the output end, the output end of the comparator U6D is simultaneously connected with one end of the capacitor C34 and one end of the capacitor C35, the other end of the capacitor C34 and the other end of the capacitor C35 are simultaneously connected with one end of the resistor R23, the other end of the resistor R23 is connected with the non-inverting input end of the comparator U6D, one end of the resistor R15 is connected with an excitation signal, the other end of the resistor R15 is simultaneously connected with one end of the resistor R16 and one end of the resistor R24, the other end of the resistor R16 is grounded, and the other end of the resistor R24 is connected with one end of the resistor R23.
Preferably, the comparison and subtraction unit includes an a comparison circuit, a B comparison circuit, a C comparison circuit, an AB subtraction circuit, an AC subtraction circuit, and a BC subtraction circuit;
The A comparison circuit comprises a resistor R25, a resistor R38, a resistor R49, a comparator USA and a diode D1, wherein the anode of the diode D1 is grounded, the cathode of the diode D1 is simultaneously connected with the inverting input end of the comparator USA and one end of the resistor R25, the other end of the resistor R25 is connected with the output end of the comparator U6A in the A-phase attenuation circuit, the non-inverting input end of the comparator USA is grounded through the resistor R38, and the output end of the comparator USA is grounded through the resistor R49;
The B comparison circuit comprises a resistor R26, a resistor R37, a resistor R48, a comparator USB and a diode D2, wherein the anode of the diode D2 is grounded, the cathode of the diode D2 is simultaneously connected with the inverting input end of the comparator USB and one end of the resistor R26, the other end of the resistor R26 is connected with the output end of the comparator U6B in the B phase attenuation circuit, the non-inverting input end of the comparator USB is grounded through the resistor R37, and the output end of the comparator USB is grounded through the resistor R48;
The C comparison circuit comprises a resistor R27, a resistor R36, a resistor R47, a comparator USC and a diode D3, wherein the anode of the diode D3 is grounded, the cathode of the diode D3 is simultaneously connected with the inverting input end of the comparator USC and one end of the resistor R27, the other end of the resistor R27 is connected with the output end of the comparator U6C in the C-phase attenuation circuit, the non-inverting input end of the comparator USC is grounded through the resistor R36, and the output end of the comparator USB is grounded through the resistor R47;
The AB subtraction circuit comprises a resistor R41, a resistor R42, a resistor R51 and a comparator UAB, wherein the non-inverting input end of the comparator UAB is simultaneously connected with one ends of a resistor R33 and a resistor R30 through the resistor R41, the other end of the resistor R33 is grounded, the other end of the resistor R30 is connected with the output end of a comparator U6B, the inverting input end of the comparator UAB is simultaneously connected with one end of a resistor R32 and one end of a resistor R29 through the resistor R42, the other end of the resistor R32 is grounded, the other end of the resistor R29 is connected with the output end of a comparator U6A, and the output end of the comparator UAB is connected with a +5V power supply through the resistor R51;
The AC phase subtraction circuit comprises a resistor R39, a resistor R40, a resistor R50 and a comparator UAC, wherein the non-inverting input end of the comparator UAC is connected with one end of a resistor R29 through the resistor R39, the inverting input end of the comparator UAC is simultaneously connected with one ends of a resistor R34 and a resistor R31 through the resistor R40, the other end of the resistor R34 is grounded, the other end of the resistor R31 is connected with the output end of the comparator U6C, and the output end of the comparator UAC is connected with a +5V power supply through the resistor R50;
the BC phase-subtracting circuit comprises a resistor R43, a resistor R44, a resistor R52 and a comparator UBC, wherein the non-inverting input end of the comparator UBC is connected with one end of the resistor R31 through the resistor R43, the inverting input end of the comparator UBC is connected with one end of the resistor R30 through the resistor R44, and the output end of the comparator UBC is connected with a +5V power supply through the resistor R52.
Preferably, the excitation signal comparing unit includes a resistor R28, a resistor R35, a resistor R45, a resistor R46, a diode D4, a comparator USD and an exclusive or gate U10D, wherein an inverting input end of the comparator USD is connected to a cathode of the diode D4 and one end of the resistor R28 at the same time, the other end of the resistor R28 is connected to an output end of the comparator U6D, an anode of the diode D4 is grounded, an in-phase input end of the comparator USD is connected to one end of the resistor R35 and one end of the resistor R45 at the same time, the other end of the resistor R35 is grounded, the other end of the resistor R45 is connected to an output end of the comparator USD, one end of the resistor R46 is connected to a +5v power supply, the other end of the resistor R46 is connected to an output end of the comparator USD, one input end of the exclusive or gate U10D is connected to an output end of the comparator USD, the other input end of the exclusive or gate U10D is grounded, and the output end of the exclusive or gate 10D is connected to the unit.
Preferably, the method comprises the steps of, the exclusive OR unit comprises an A-phase difference or circuit, a B-phase difference or circuit, a C-phase difference or circuit, an AB-phase difference or circuit, an AC-phase difference or circuit and a BC-phase difference or circuit;
The A-phase exclusive OR circuit comprises an exclusive OR gate U10A and a resistor R147, wherein one input end of the exclusive OR gate U10A is connected with the output end of the comparator USA, the other input end of the exclusive OR gate U10A is connected with the output end of the exclusive OR gate U10D, the output end of the exclusive OR gate U10A is connected with one end of the resistor R147, and the other end of the resistor R147 is used as one output end of the analog signal processing circuit to be connected with the digital signal processing circuit;
The B-phase exclusive OR circuit comprises an exclusive OR gate U10B and a resistor R146, wherein one input end of the exclusive OR gate U10B is connected with the output end of the comparator USB, the other input end of the exclusive OR gate U10B is connected with the output end of the exclusive OR gate U10D, the output end of the exclusive OR gate U10B is connected with one end of the resistor R146, and the other end of the resistor R146 is used as one output end of the analog signal processing circuit to be connected with the digital signal processing circuit;
The C-phase exclusive OR circuit comprises an exclusive OR gate U10C and a resistor R145, wherein one input end of the exclusive OR gate U10C is connected with the output end of the comparator USC, the other input end of the exclusive OR gate U10C is connected with the output end of the exclusive OR gate U10D, the output end of the exclusive OR gate U10C is connected with one end of the resistor R145, and the other end of the resistor R145 is used as one output end of the analog signal processing circuit to be connected with the digital signal processing circuit;
the AB dissimilarity OR circuit comprises an exclusive OR gate U10AB and a resistor R149, wherein one input end of the exclusive OR gate U10AB is connected with the output end of the comparator UAB, the other input end of the exclusive OR gate U10AB is connected with the output end of the exclusive OR gate U10D, the output end of the exclusive OR gate U10AB is connected with one end of the resistor R149, and the other end of the resistor R149 is used as one output end of the analog signal processing circuit to be connected with the digital signal processing circuit;
The AC dissimilarity OR circuit comprises an exclusive OR gate U10AC and a resistor R148, wherein one input end of the exclusive OR gate U10AC is connected with the output end of the comparator UAC, the other input end of the exclusive OR gate U10AC is connected with the output end of the exclusive OR gate U10D, the output end of the exclusive OR gate U10AC is connected with one end of the resistor R148, and the other end of the resistor R148 is used as one output end of the analog signal processing circuit to be connected with the digital signal processing circuit;
The BC differential OR circuit comprises an exclusive OR gate U10BC and a resistor R150, wherein one input end of the exclusive OR gate U10BC is connected with the output end of the comparator UBC, the other input end of the exclusive OR gate U10BC is connected with the output end of the exclusive OR gate U10D, the output end of the exclusive OR gate U10BC is connected with one end of the resistor R150, and the other end of the resistor R150 is used as one output end of the analog signal processing circuit to be connected with the digital signal processing circuit.
Preferably, the power failure detection circuit comprises a MAX706SEPA chip, a resistor R4, a resistor R5, a resistor R6 and a resistor R78, wherein a PFI interface of the MAX706SEPA chip is simultaneously connected with one end of the resistor R4 and one end of the resistor R5, the other end of the resistor R4 is connected with a +5V power supply, the other end of the resistor R5 is grounded through the resistor R6, a GND interface of the MAX706SEPA chip is grounded, a VCC interface of the MAX706SEPA is connected with a power supply, and a PFO interface of the MAX706SEPA chip is connected with the resistor R78.
Preferably, the data storage circuit includes AN AT24C08AN chip, a resistor R72, a resistor R73 and a capacitor C60, where AN A0 interface, AN A1 interface, AN A2 interface and a GND interface of the AT24C08AN chip are all grounded, a VCC interface of the AT24C08AN chip is connected to a power supply, one end of the capacitor C60 is grounded, the other end of the capacitor C60 is connected to a VCC interface of the AT24C08AN chip, one end of the resistor R72 is connected to a VCC interface of the AT24C08AN chip, the other end of the resistor R72 is connected to AN SDA interface of the AT24C08AN chip, and one end of the resistor R73 is connected to a VCC interface of the AT24C08AN chip, and the other end of the resistor R73 is connected to AN SCL interface of the AT24C08AN chip.
Preferably, the high-speed course digital converter further comprises a digital display circuit, the digital display circuit comprises a nixie tube driving assembly, a bit code driving assembly and a digital display assembly, the input ends of the nixie tube driving assembly and the bit code driving assembly are connected with the microprocessor module, and the output ends of the nixie tube driving assembly and the bit code driving assembly are connected with the digital display assembly, so that display information is obtained from the microprocessor module and the digital display assembly is driven to display.
Preferably, the nixie tube driving component comprises a 74HC595 chip, the bit code driving component comprises a MC1413BD chip, and the digital display component comprises a SM420564 chip;
The Q0 interface of the 74HC595 chip is connected with the A interface of the SM420564 chip through a resistor R58, the Q1 interface of the 74HC595 chip is connected with the B interface of the SM420564 chip through a resistor R59, the Q2 interface of the 74HC595 chip is connected with the C interface of the SM420564 chip through a resistor R60, the Q3 interface of the 74HC595 chip is connected with the D interface of the SM420564 chip through a resistor R61, the Q4 interface of the 74HC595 chip is connected with the E interface of the SM420564 chip through a resistor R62, the Q5 interface of the 74HC595 chip is connected with the F interface of the SM420564 chip through a resistor R63, the Q6 interface of the 74HC595 chip is connected with the G interface of the SM420564 chip through a resistor R64, and the Q7 interface of the 74HC595 chip is connected with the Dp interface of the SM420564 chip through a resistor R65.
The OUT1 interface of MC1413BD chip pass through resistance R66 with the S1 interface connection of SM420564 chip, the OUT2 interface of MC1413BD chip pass through resistance R67 with the S2 interface connection of SM420564 chip, the OUT3 interface of MC1413BD chip pass through resistance R68 with the S3 interface connection of SM420564 chip, the OUT4 interface of MC1413BD chip pass through resistance R69 with the S4 interface connection of SM420564 chip.
Compared with the prior art, the invention has the following advantages:
1. The invention can automatically track and display the heading angle value of the electric compass by collecting the analog signals output by the electric compass self-angle regulator and taking the excitation signals as the power supply and the reference signals, and then can output the heading angle data of the electric compass to other equipment in a timing manner in an RS-422 communication mode. Because the analog signal sent out by the electric compass self-angle machine is three sine alternating signals which mutually form 120 degrees of phase, the three sine alternating signals have strict phase relation with the self-angle machine (when the rotation speed ratio of the electric compass to the self-angle machine is 1:360, the corresponding electric compass angle is 1 degree), and therefore, after the analog signal is subjected to the processes of attenuation, zero discrimination, phase discrimination, shaping, addition and the like, the three-phase signals Fa, fb and Fc output by the self-angle machine are converted into 6-bit cyclic codes and are sent into a digital signal processor, and then the three-phase signals are collected and processed by a digital signal processing circuit, and the heading initial value set during starting is added, so that the digital real-time heading value of the electric compass is obtained. By converting the analog heading value of the electric compass into the digital heading value, the ship signal interaction capability can be greatly improved.
2. The power failure detection circuit in the invention mainly aims at detecting the power failure of equipment so as to save the course value and other setting parameters at the time of power failure, prevent data loss and avoid the need of re-matching the course value when the next power is on. The power failure detection circuit monitors voltage by adopting the MAX706SEPA chip, and outputs a low-level signal to the main control chip when the voltage is lower than a reference value, so that the main control chip can finish data storage operation.
3. The data storage circuit in the invention mainly aims AT storing the data AT the time of power failure, and uses the AT24C08AN as a storage chip, when the system is powered off, the main control chip stores the data; when the system is powered on, the main control chip will first read the last stored value to match the course value and other setting parameters automatically.
4. The invention selects a high-performance digital signal processor TMS320F2812 as a main control chip, wherein TMS320F2812 is a 32-bit fixed-point micro control unit, and the main frequency is up to 150MHz; the system has bus interfaces such as I2C, SPI, CAN, PWM and the like, is suitable for various control industrial equipment, and is completely enough for processing digital signals by using ultra-high frequency of 150MHz, so that the heading tracking capability can be obviously improved by improving the acquisition and operation speed, and the actual measurement can improve the tracking speed from the original 14 degrees/s to 70 degrees/s.
5. The invention is by the analog signal processing circuit that the frequency compensation operational amplifier of the high gain, analog comparator and input exclusive OR gate make up, receive from the input of the self-angle machine and excitation signal, output six high-low level comparison signals; the high-speed digital signal processing circuit collects high-low level signals and carries out logic processing on the high-low level signals to obtain heading signals; the digital display circuit is communicated with the digital signal processing circuit through the SPI bus, and the current course is refreshed and displayed in real time; the key circuit is responsible for course matching setting and brightness adjustment; the power-down detection circuit compares the current voltage with the reference voltage in real time, when the current voltage is lower than the reference voltage, the E2PROM stores the current course value and the display brightness value, and the course value and the display brightness stored in the E2PROM are read when the main compass is started next time.
Drawings
FIG. 1 is a system block diagram of a high speed heading digitizer of the present invention;
FIG. 2 is a circuit diagram of an excitation signal circuit and an analog signal processing circuit in the high speed heading digital converter of the present invention;
FIG. 3 is a partial circuit diagram of a power down detection circuit in the high speed heading digitizer of the present invention;
FIG. 4 is a partial circuit diagram of a data storage circuit in the high speed heading digitizer of the present invention;
FIG. 5 is a partial circuit diagram of a digital display circuit in the high speed heading digital converter of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. It will be apparent that the described embodiments are some, but not all, embodiments of the invention. All other embodiments, which can be made by a person skilled in the art without creative efforts, based on the described embodiments of the present invention fall within the protection scope of the present invention. Unless defined otherwise, technical or scientific terms used herein should be given the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs.
The terms "first," "second," and the like in the description and in the claims, are not used for any order, quantity, or importance, but are used for distinguishing between different elements. Also, unless the context clearly indicates otherwise, singular forms "a," "an," or "the" and similar terms do not denote a limitation of quantity, but rather denote the presence of at least one. The terms "comprises," "comprising," or the like are intended to cover a feature, integer, step, operation, element, and/or component recited as being present in the element or article that "comprises" or "comprising" does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. "up", "down", "left", "right" and the like are used only to indicate a relative positional relationship, and when the absolute position of the object to be described is changed, the relative positional relationship may be changed accordingly.
As shown in figure 1, the high-speed course digital converter comprises a microprocessor module, a self-angle machine signal circuit, an excitation signal circuit, an analog signal processing circuit, a power failure detection circuit and a data storage circuit, wherein the microprocessor module comprises a digital signal processing circuit and a main control chip;
the output end of the self-angle-setting machine signal circuit is in communication connection with the input end of the analog signal processing circuit, and is used for inputting the three-phase analog signal output by the self-angle-setting machine into the analog signal processing circuit;
The output end of the excitation signal circuit is in communication connection with the input end of the analog signal processing circuit and is used for inputting the excitation signal into the analog signal processing circuit after attenuation and comparison processing;
The output end of the analog signal processing circuit is in communication connection with the input end of the digital signal processing circuit, and is used for converting the three-phase analog signal output by the self-angle shaper into six paths of digital signals under the action of the excitation signal and inputting the six paths of digital signals into the digital signal processing circuit;
The digital signal processing circuit is used for comparing the input six paths of digital signals with a set heading initial value to obtain a real-time heading signal;
The power-down detection circuit is in bidirectional communication connection with the microprocessor module, and is used for comparing the voltage value of the main control chip with the voltage reference value and sending a low-level signal to the main control chip when the voltage value of the main control chip is lower than the voltage reference value;
The data storage circuit is in bidirectional communication connection with the microprocessor module, the data storage circuit stores data when the main control chip receives the low-level signal, and the main control chip reads the data stored in the last power-off process from the data storage circuit when the main control chip is powered on again so as to automatically match the heading information.
The working principle of the invention is as follows: when the high-speed course digital converter is used, the self-angle machine signal circuit receives three-phase analog signals from the self-angle machine, the self-angle machine signal circuit inputs the received three-phase analog signals of the self-angle machine into the analog signal processing circuit for processing, meanwhile, the analog signal processing circuit also receives the attenuated and compared excitation signals from the excitation signal circuit, the analog signal processing circuit converts the three-phase analog signals output by the self-angle machine into six-way digital signals under the action of the excitation signals and outputs the six-way digital signals to the digital signal processing circuit, the course initial value of a ship is set in the digital signal processing circuit, the digital signal processing circuit compares the received six-way digital signals with the course initial value, and further, the digital real-time course signals of the ship can be obtained, and then the digital real-time course signals are transmitted to various instruments on the ship, and the course information is required to be acquired.
Meanwhile, the navigation digital converter is also provided with the power-down detection circuit and the data storage circuit, the power-down detection circuit can send a low-level signal to the main control chip when power is down so as to save data through the data storage circuit, and when the power is on again, the navigation digital converter can automatically match course information by reading the data saved by last power failure so as to avoid the problem that the course information needs to be matched again after power is off each time.
As shown in fig. 2, in this embodiment, the analog signal processing circuit includes an attenuation unit, a comparison and subtraction unit and an exclusive-or unit, where the attenuation unit is configured to attenuate three-phase analog signals output from the squaring machine, the comparison and subtraction unit is configured to compare the attenuated three-phase analog signals with a reference value, and simultaneously compare the attenuated three-phase analog signals two by two and output six paths of signals to the exclusive-or unit, and the exclusive-or unit performs exclusive-or operation on the six paths of digital signals and the attenuated and compared excitation signals output from the excitation signal circuit and outputs six paths of digital signals to the digital signal processing circuit;
the excitation signal circuit comprises an excitation signal attenuation unit and an excitation signal comparison unit, wherein the excitation signal attenuation unit is used for carrying out attenuation processing on an excitation signal, the excitation signal comparison unit is used for comparing the excitation signal subjected to attenuation processing with an excitation reference value, and the comparison result is subjected to exclusive-or processing and then is output to the exclusive-or unit.
In this embodiment, the attenuation unit includes an a-phase attenuation circuit, a B-phase attenuation circuit, and a C-phase attenuation circuit, where the a-phase attenuation circuit includes a capacitor C25, a capacitor C28, a capacitor C29, a resistor R13, a resistor R14, a resistor R17, a resistor R18, and a comparator U6A, where the non-inverting input terminal of the comparator U6A is grounded through the capacitor C25, the inverting input terminal of the comparator U6A is connected to the output terminal, the output terminal of the comparator U6A is simultaneously connected to one end of the capacitor C28 and one end of the capacitor C29, the other end of the capacitor C28 and the other end of the capacitor C29 are simultaneously connected to one end of the resistor R17, the other end of the resistor R17 is connected to the non-inverting input terminal of the comparator U6A, one end of the resistor R13 is simultaneously connected to one end of the resistor R18 and one end of the resistor R14, the other end of the resistor R14 is grounded, and the other end of the resistor R18 is connected to one end of the resistor R17;
The B-phase attenuation circuit comprises a capacitor C54, a capacitor C30, a capacitor C31, a resistor R9, a resistor R10, a resistor R19, a resistor R20 and a comparator U6B, wherein the non-inverting input end of the comparator U6B is grounded through the capacitor C54, the inverting input end of the comparator U6B is connected with the output end, the output end of the comparator U6B is simultaneously connected with one end of the capacitor C30 and one end of the capacitor C31, the other end of the capacitor C30 and the other end of the capacitor C31 are simultaneously connected with one end of a resistor R19, the other end of the resistor R19 is connected with the non-inverting input end of the comparator U6B, one end of the resistor R9 is simultaneously connected with one end of the resistor R10 and one end of the resistor R20, the other end of the resistor R10 is grounded, and the other end of the resistor R20 is connected with one end of the resistor R19;
The C-phase attenuation circuit comprises a capacitor C55, a capacitor C32, a capacitor C33, a resistor R11, a resistor R12, a resistor R21, a resistor R22 and a comparator U6C, wherein the non-inverting input end of the comparator U6C is grounded through the capacitor C55, the inverting input end of the comparator U6C is connected with the output end, the output end of the comparator U6C is simultaneously connected with one end of the capacitor C32 and one end of the capacitor C33, the other end of the capacitor C32 and the other end of the capacitor C33 are simultaneously connected with one end of a resistor R21, the other end of the resistor R21 is connected with the non-inverting input end of the comparator U6C, one end of the resistor R11 is simultaneously connected with one end of the resistor R12 and one end of the resistor R22, the other end of the resistor R12 is grounded, and the other end of the resistor R22 is connected with one end of the resistor R21;
The excitation signal attenuation unit comprises a capacitor C56, a capacitor C34, a capacitor C35, a resistor R15, a resistor R16, a resistor R23, a resistor R24 and a comparator U6D, wherein the non-inverting input end of the comparator U6D is grounded through the capacitor C56, the inverting input end of the comparator U6D is connected with the output end, the output end of the comparator U6D is simultaneously connected with one end of the capacitor C34 and one end of the capacitor C35, the other end of the capacitor C34 and the other end of the capacitor C35 are simultaneously connected with one end of the resistor R23, the other end of the resistor R23 is connected with the non-inverting input end of the comparator U6D, one end of the resistor R15 is connected with an excitation signal, the other end of the resistor R15 is simultaneously connected with one end of the resistor R16 and one end of the resistor R24, the other end of the resistor R16 is grounded, and the other end of the resistor R24 is connected with one end of the resistor R23.
In the present embodiment, the comparison and subtraction unit includes an a comparison circuit, a B comparison circuit, a C comparison circuit, an AB subtraction circuit, an AC subtraction circuit, and a BC subtraction circuit;
The A comparison circuit comprises a resistor R25, a resistor R38, a resistor R49, a comparator USA and a diode D1, wherein the anode of the diode D1 is grounded, the cathode of the diode D1 is simultaneously connected with the inverting input end of the comparator USA and one end of the resistor R25, the other end of the resistor R25 is connected with the output end of a comparator U6A in the A-phase attenuation circuit, the non-inverting input end of the comparator USA is grounded through the resistor R38, and the output end of the comparator USA is grounded through the resistor R49;
The B comparison circuit comprises a resistor R26, a resistor R37, a resistor R48, a comparator USB and a diode D2, wherein the anode of the diode D2 is grounded, the cathode of the diode D2 is simultaneously connected with the inverting input end of the comparator USB and one end of the resistor R26, the other end of the resistor R26 is connected with the output end of a comparator U6B in the B-phase attenuation circuit, the non-inverting input end of the comparator USB is grounded through the resistor R37, and the output end of the comparator USB is grounded through the resistor R48;
The C comparison circuit comprises a resistor R27, a resistor R36, a resistor R47, a comparator USC and a diode D3, wherein the anode of the diode D3 is grounded, the cathode of the diode D3 is simultaneously connected with the inverting input end of the comparator USC and one end of the resistor R27, the other end of the resistor R27 is connected with the output end of the comparator U6C in the C-phase attenuation circuit, the non-inverting input end of the comparator USC is grounded through the resistor R36, and the output end of the comparator USB is grounded through the resistor R47;
The AB subtraction circuit comprises a resistor R41, a resistor R42, a resistor R51 and a comparator UAB, wherein the non-inverting input end of the comparator UAB is simultaneously connected with one end of a resistor R33 and one end of a resistor R30 through the resistor R41, the other end of the resistor R33 is grounded, the other end of the resistor R30 is connected with the output end of a comparator U6B, the inverting input end of the comparator UAB is simultaneously connected with one end of a resistor R32 and one end of a resistor R29 through the resistor R42, the other end of the resistor R32 is grounded, the other end of the resistor R29 is connected with the output end of the comparator U6A, and the output end of the comparator UAB is connected with a +5V power supply through the resistor R51;
the AC phase subtraction circuit comprises a resistor R39, a resistor R40, a resistor R50 and a comparator UAC, wherein the non-inverting input end of the comparator UAC is connected with one end of a resistor R29 through the resistor R39, the inverting input end of the comparator UAC is simultaneously connected with one end of a resistor R34 and one end of a resistor R31 through the resistor R40, the other end of the resistor R34 is grounded, the other end of the resistor R31 is connected with the output end of the comparator U6C, and the output end of the comparator UAC is connected with a +5V power supply through the resistor R50;
The BC phase-subtracting circuit comprises a resistor R43, a resistor R44, a resistor R52 and a comparator UBC, wherein the non-inverting input end of the comparator UBC is connected with one end of the resistor R31 through the resistor R43, the inverting input end of the comparator UBC is connected with one end of the resistor R30 through the resistor R44, and the output end of the comparator UBC is connected with a +5V power supply through the resistor R52.
In this embodiment, the excitation signal comparing unit includes a resistor R28, a resistor R35, a resistor R45, a resistor R46, a diode D4, a comparator USD and an exclusive-or gate U10D, the inverting input terminal of the comparator USD is connected to the cathode of the diode D4 and one end of the resistor R28 at the same time, the other end of the resistor R28 is connected to the output terminal of the comparator U6D, the anode of the diode D4 is grounded, the non-inverting input terminal of the comparator USD is connected to one end of the resistor R35 and one end of the resistor R45 at the same time, the other end of the resistor R35 is grounded, the other end of the resistor R45 is connected to the output terminal of the comparator USD, one end of the resistor R46 is connected to the +5v power supply, one input terminal of the exclusive-or gate U10D is connected to the output terminal of the comparator USD, the other input terminal of the exclusive-or gate U10D is grounded, and the output terminal of the exclusive-or gate U10D is connected to the exclusive-or unit.
In this embodiment, the exclusive or unit includes a different or circuit, B different or circuit, C different or circuit, AB different or circuit, AC different or circuit, and BC different or circuit;
The A-phase exclusive OR circuit comprises an exclusive OR gate U10A and a resistor R147, one input end of the exclusive OR gate U10A is connected with the output end of the comparator USA, the other input end of the exclusive OR gate U10A is connected with the output end of the exclusive OR gate U10D, the output end of the exclusive OR gate U10A is connected with one end of the resistor R147, and the other end of the resistor R147 is used as one output end of the analog signal processing circuit to be connected with the digital signal processing circuit;
The B-phase exclusive OR circuit comprises an exclusive OR gate U10B and a resistor R146, one input end of the exclusive OR gate U10B is connected with the output end of the comparator USB, the other input end of the exclusive OR gate U10B is connected with the output end of the exclusive OR gate U10D, the output end of the exclusive OR gate U10B is connected with one end of the resistor R146, and the other end of the resistor R146 is used as one output end of the analog signal processing circuit to be connected with the digital signal processing circuit;
the C-phase exclusive OR circuit comprises an exclusive OR gate U10C and a resistor R145, wherein one input end of the exclusive OR gate U10C is connected with the output end of the comparator USC, the other input end of the exclusive OR gate U10C is connected with the output end of the exclusive OR gate U10D, the output end of the exclusive OR gate U10C is connected with one end of the resistor R145, and the other end of the resistor R145 is used as one output end of the analog signal processing circuit to be connected with the digital signal processing circuit;
The AB exclusive OR circuit comprises an exclusive OR gate U10AB and a resistor R149, wherein one input end of the exclusive OR gate U10AB is connected with the output end of the comparator UAB, the other input end of the exclusive OR gate U10AB is connected with the output end of the exclusive OR gate U10D, the output end of the exclusive OR gate U10AB is connected with one end of the resistor R149, and the other end of the resistor R149 is used as one output end of the analog signal processing circuit to be connected with the digital signal processing circuit;
The AC exclusive OR circuit comprises an exclusive OR gate U10AC and a resistor R148, wherein one input end of the exclusive OR gate U10AC is connected with the output end of the comparator UAC, the other input end of the exclusive OR gate U10AC is connected with the output end of the exclusive OR gate U10D, the output end of the exclusive OR gate U10AC is connected with one end of the resistor R148, and the other end of the resistor R148 is used as one output end of the analog signal processing circuit to be connected with the digital signal processing circuit;
The BC exclusive OR circuit comprises an exclusive OR gate U10BC and a resistor R150, one input end of the exclusive OR gate U10BC is connected with the output end of the comparator UBC, the other input end of the exclusive OR gate U10BC is connected with the output end of the exclusive OR gate U10D, the output end of the exclusive OR gate U10BC is connected with one end of the resistor R150, and the other end of the resistor R150 is used as one output end of the analog signal processing circuit to be connected with the digital signal processing circuit.
As shown in fig. 3, in this embodiment, the power failure detection circuit includes a MAX706SEPA chip, a resistor R4, a resistor R5, a resistor R6, and a resistor R78, where the PFI interface of the MAX706SEPA chip is connected to one end of the resistor R4 and one end of the resistor R5 at the same time, the other end of the resistor R4 is connected to a +5v power supply, the other end of the resistor R5 is grounded through the resistor R6, the GND interface of the MAX706SEPA chip is grounded, the VCC interface of the MAX706SEPA is connected to the power supply, and the PFO interface of the MAX706SEPA chip is connected to the resistor R78.
As shown in fig. 4, in this embodiment, the data storage circuit includes AN AT24C08AN chip, a resistor R72, a resistor R73, and a capacitor C60, where the A0 interface, the A1 interface, the A2 interface, and the GND interface of the AT24C08AN chip are all grounded, the VCC interface of the AT24C08AN chip is connected to a power supply, one end of the capacitor C60 is grounded, the other end of the capacitor C60 is connected to the VCC interface of the AT24C08AN chip, one end of the resistor R72 is connected to the VCC interface of the AT24C08AN chip, the other end of the resistor R72 is connected to the SDA interface of the AT24C08AN chip, one end of the resistor R73 is connected to the VCC interface of the AT24C08AN chip, and the other end of the resistor R73 is connected to the SCL interface of the AT24C08AN chip.
As shown in FIG. 5, in this embodiment, the high-speed heading digital converter further includes a digital display circuit, where the digital display circuit includes a nixie tube driving component, a bit code driving component and a digital display component, input ends of the nixie tube driving component and the bit code driving component are connected with the microprocessor module, and output ends of the nixie tube driving component and the bit code driving component are connected with the digital display component, so as to obtain display information from the microprocessor module and drive the digital display component to display.
In this embodiment, the nixie tube driving component includes a 74HC595 chip, the bit code driving component includes a MC1413BD chip, and the digital display component includes a SM420564 chip;
the Q0 interface of the 74HC595 chip is connected with the A interface of the SM420564 chip through a resistor R58, the Q1 interface of the 74HC595 chip is connected with the B interface of the SM420564 chip through a resistor R59, the Q2 interface of the 74HC595 chip is connected with the C interface of the SM420564 chip through a resistor R60, the Q3 interface of the 74HC595 chip is connected with the D interface of the SM420564 chip through a resistor R61, the Q4 interface of the 74HC595 chip is connected with the E interface of the SM420564 chip through a resistor R62, the Q5 interface of the 74HC595 chip is connected with the F interface of the SM420564 chip through a resistor R63, the Q6 interface of the 74HC595 chip is connected with the G interface of the SM420564 chip through a resistor R64, and the Q7 interface of the 74HC595 chip is connected with the Dp interface of the SM420564 chip through a resistor R65.
The OUT1 interface of the MC1413BD chip is connected with the S1 interface of the SM420564 chip through a resistor R66, the OUT2 interface of the MC1413BD chip is connected with the S2 interface of the SM420564 chip through a resistor R67, the OUT3 interface of the MC1413BD chip is connected with the S3 interface of the SM420564 chip through a resistor R68, and the OUT4 interface of the MC1413BD chip is connected with the S4 interface of the SM420564 chip through a resistor R69.
The invention can automatically track and display the heading angle value of the electric compass by collecting the analog signals output by the electric compass self-angle regulator and taking the excitation signals as the power supply and the reference signals, and then can output the heading angle data of the electric compass to other equipment in a timing manner in an RS-422 communication mode. Because the analog signal sent out by the electric compass self-angle machine is three sine alternating signals which mutually form 120 degrees of phase, the three sine alternating signals have strict phase relation with the self-angle machine (when the rotation speed ratio of the electric compass to the self-angle machine is 1:360, the corresponding electric compass angle is 1 degree), and therefore, after the analog signal is subjected to the processes of attenuation, zero discrimination, phase discrimination, shaping, addition and the like, the three-phase signals Fa, fb and Fc output by the self-angle machine are converted into 6-bit cyclic codes and are sent into a digital signal processor, and then the three-phase signals are collected and processed by a digital signal processing circuit, and the heading initial value set during starting is added, so that the digital real-time heading value of the electric compass is obtained. By converting the analog heading value of the electric compass into the digital heading value, the ship signal interaction capability can be greatly improved.
The power failure detection circuit in the invention mainly aims at detecting the power failure of equipment so as to save the course value and other setting parameters at the time of power failure, prevent data loss and avoid the need of re-matching the course value when the next power is on. The power failure detection circuit monitors voltage by adopting the MAX706SEPA chip, and outputs a low-level signal to the main control chip when the voltage is lower than a reference value, so that the main control chip can finish data storage operation.
The data storage circuit in the invention mainly aims AT storing the data AT the time of power failure, and uses the AT24C08AN as a storage chip, when the system is powered off, the main control chip stores the data; when the system is powered on, the main control chip will first read the last stored value to match the course value and other setting parameters automatically.
The invention selects a high-performance digital signal processor TMS320F2812 as a main control chip, wherein TMS320F2812 is a 32-bit fixed-point micro control unit, and the main frequency is up to 150MHz; the system has bus interfaces such as I2C, SPI, CAN, PWM and the like, is suitable for various control industrial equipment, and is completely enough for processing digital signals by using ultra-high frequency of 150MHz, so that the heading tracking capability can be obviously improved by improving the acquisition and operation speed, and the actual measurement can improve the tracking speed from the original 14 degrees/s to 70 degrees/s.
The invention is by the analog signal processing circuit that the frequency compensation operational amplifier of the high gain, analog comparator and input exclusive OR gate make up, receive from the input of the self-angle machine and excitation signal, output six high-low level comparison signals; the high-speed digital signal processing circuit collects high-low level signals and carries out logic processing on the high-low level signals to obtain heading signals; the digital display circuit is communicated with the digital signal processing circuit through the SPI bus, and the current course is refreshed and displayed in real time; the key circuit is responsible for course matching setting and brightness adjustment; the power-down detection circuit compares the current voltage with the reference voltage in real time, when the current voltage is lower than the reference voltage, the E2PROM stores the current course value and the display brightness value, and the course value and the display brightness stored in the E2PROM are read when the main compass is started next time.
Finally, it should be noted that the above embodiments are only for illustrating the technical solution of the present invention and not for limiting the technical solution, and those skilled in the art should understand that modifications and equivalents may be made to the technical solution of the present invention without departing from the spirit and scope of the present invention, and all such modifications and equivalents are included in the scope of the claims.

Claims (10)

1. The high-speed course digital converter is characterized by comprising a microprocessor module, a self-angle machine signal circuit, an excitation signal circuit, an analog signal processing circuit, a power failure detection circuit and a data storage circuit, wherein the microprocessor module comprises a digital signal processing circuit and a main control chip;
the output end of the self-angle-setting machine signal circuit is in communication connection with the input end of the analog signal processing circuit and is used for inputting the three-phase analog signals output by the self-angle-setting machine into the analog signal processing circuit;
The output end of the excitation signal circuit is in communication connection with the input end of the analog signal processing circuit, and is used for inputting an excitation signal into the analog signal processing circuit after attenuation and comparison processing;
the output end of the analog signal processing circuit is in communication connection with the input end of the digital signal processing circuit, and is used for converting the three-phase analog signals output by the self-angle adjusting machine into six paths of digital signals under the action of excitation signals and inputting the six paths of digital signals into the digital signal processing circuit;
the digital signal processing circuit is used for comparing the input six paths of digital signals with a set course initial value to obtain a real-time course signal;
the power-down detection circuit is in bidirectional communication connection with the microprocessor module, and is used for comparing the voltage value of the main control chip with a voltage reference value and sending a low-level signal to the main control chip when the voltage value of the main control chip is lower than the voltage reference value;
The data storage circuit is in bidirectional communication connection with the microprocessor module, the data storage circuit stores data when the main control chip receives a low-level signal, and the main control chip reads the data stored in the last power-off state from the data storage circuit when the main control chip is powered on again so as to automatically match course information.
2. The high-speed heading digital converter according to claim 1, wherein the analog signal processing circuit comprises an attenuation unit, a comparison and subtraction unit and an exclusive-or unit, the attenuation unit is used for carrying out attenuation processing on three-phase analog signals output by the self-angle shaper, the comparison and subtraction unit is used for respectively comparing the three-phase analog signals subjected to attenuation processing with a reference value, simultaneously comparing the three-phase analog signals subjected to attenuation processing in pairs and outputting six paths of signals to the exclusive-or unit, and the exclusive-or unit carries out exclusive-or operation on the six paths of digital signals respectively with the excitation signals subjected to attenuation and comparison processing output by the excitation signal circuit and outputting six paths of digital signals to the digital signal processing circuit;
The excitation signal circuit comprises an excitation signal attenuation unit and an excitation signal comparison unit, wherein the excitation signal attenuation unit is used for carrying out attenuation processing on an excitation signal, and the excitation signal comparison unit is used for comparing the excitation signal subjected to attenuation processing with an excitation reference value, carrying out exclusive-or processing on a comparison result and outputting the comparison result to the exclusive-or unit.
3. The high speed heading digital converter according to claim 2, wherein the attenuation unit comprises an a-phase attenuation circuit, a B-phase attenuation circuit and a C-phase attenuation circuit, the a-phase attenuation circuit comprises a capacitor C25, a capacitor C28, a capacitor C29, a resistor R13, a resistor R14, a resistor R17, a resistor R18 and a comparator U6A, the non-inverting input of the comparator U6A is grounded through the capacitor C25, the inverting input of the comparator U6A is connected with an output terminal, the output terminal of the comparator U6A is simultaneously connected with one end of the capacitor C28 and one end of the capacitor C29, the other end of the capacitor C28 and the other end of the capacitor C29 are simultaneously connected with one end of the resistor R17, the other end of the resistor R17 is connected with the non-inverting input terminal of the comparator U6A, one end of the resistor R13 is simultaneously connected with one end of the resistor R18 and one end of the resistor R14, the other end of the resistor R14 is connected with one end of the resistor R17;
The phase B attenuation circuit comprises a capacitor C54, a capacitor C30, a capacitor C31, a resistor R9, a resistor R10, a resistor R19, a resistor R20 and a comparator U6B, wherein the non-inverting input end of the comparator U6B is grounded through the capacitor C54, the inverting input end of the comparator U6B is connected with the output end, the output end of the comparator U6B is simultaneously connected with one end of the capacitor C30 and one end of the capacitor C31, the other end of the capacitor C30 and the other end of the capacitor C31 are simultaneously connected with one end of the resistor R19, the other end of the resistor R19 is connected with the non-inverting input end of the comparator U6B, one end of the resistor R9 is simultaneously connected with one end of the resistor R10 and one end of the resistor R20, the other end of the resistor R10 is grounded, and the other end of the resistor R20 is connected with one end of the resistor R19;
The C-phase attenuation circuit comprises a capacitor C55, a capacitor C32, a capacitor C33, a resistor R11, a resistor R12, a resistor R21, a resistor R22 and a comparator U6C, wherein the non-inverting input end of the comparator U6C is grounded through the capacitor C55, the inverting input end of the comparator U6C is connected with the output end, the output end of the comparator U6C is simultaneously connected with one end of the capacitor C32 and one end of the capacitor C33, the other end of the capacitor C32 and the other end of the capacitor C33 are simultaneously connected with one end of the resistor R21, the other end of the resistor R21 is connected with the non-inverting input end of the comparator U6C, one end of the resistor R11 is connected with the C-phase output end of the self-rectifying machine signal circuit, the other end of the resistor R11 is simultaneously connected with one end of the resistor R12 and one end of the resistor R22, and the other end of the resistor R12 is grounded, and the other end of the resistor R22 is connected with one end of the resistor R21;
The excitation signal attenuation unit comprises a capacitor C56, a capacitor C34, a capacitor C35, a resistor R15, a resistor R16, a resistor R23, a resistor R24 and a comparator U6D, wherein the non-inverting input end of the comparator U6D is grounded through the capacitor C56, the inverting input end of the comparator U6D is connected with the output end, the output end of the comparator U6D is simultaneously connected with one end of the capacitor C34 and one end of the capacitor C35, the other end of the capacitor C34 and the other end of the capacitor C35 are simultaneously connected with one end of the resistor R23, the other end of the resistor R23 is connected with the non-inverting input end of the comparator U6D, one end of the resistor R15 is connected with an excitation signal, the other end of the resistor R15 is simultaneously connected with one end of the resistor R16 and one end of the resistor R24, the other end of the resistor R16 is grounded, and the other end of the resistor R24 is connected with one end of the resistor R23.
4. The high speed heading digitizer of claim 3, wherein the comparison and subtraction unit comprises an a comparison circuit, a B comparison circuit, a C comparison circuit, an AB subtraction circuit, an AC subtraction circuit, and a BC subtraction circuit;
The A comparison circuit comprises a resistor R25, a resistor R38, a resistor R49, a comparator USA and a diode D1, wherein the anode of the diode D1 is grounded, the cathode of the diode D1 is simultaneously connected with the inverting input end of the comparator USA and one end of the resistor R25, the other end of the resistor R25 is connected with the output end of the comparator U6A in the A-phase attenuation circuit, the non-inverting input end of the comparator USA is grounded through the resistor R38, and the output end of the comparator USA is grounded through the resistor R49;
The B comparison circuit comprises a resistor R26, a resistor R37, a resistor R48, a comparator USB and a diode D2, wherein the anode of the diode D2 is grounded, the cathode of the diode D2 is simultaneously connected with the inverting input end of the comparator USB and one end of the resistor R26, the other end of the resistor R26 is connected with the output end of the comparator U6B in the B phase attenuation circuit, the non-inverting input end of the comparator USB is grounded through the resistor R37, and the output end of the comparator USB is grounded through the resistor R48;
The C comparison circuit comprises a resistor R27, a resistor R36, a resistor R47, a comparator USC and a diode D3, wherein the anode of the diode D3 is grounded, the cathode of the diode D3 is simultaneously connected with the inverting input end of the comparator USC and one end of the resistor R27, the other end of the resistor R27 is connected with the output end of the comparator U6C in the C-phase attenuation circuit, the non-inverting input end of the comparator USC is grounded through the resistor R36, and the output end of the comparator USB is grounded through the resistor R47;
The AB subtraction circuit comprises a resistor R41, a resistor R42, a resistor R51 and a comparator UAB, wherein the non-inverting input end of the comparator UAB is simultaneously connected with one ends of a resistor R33 and a resistor R30 through the resistor R41, the other end of the resistor R33 is grounded, the other end of the resistor R30 is connected with the output end of a comparator U6B, the inverting input end of the comparator UAB is simultaneously connected with one end of a resistor R32 and one end of a resistor R29 through the resistor R42, the other end of the resistor R32 is grounded, the other end of the resistor R29 is connected with the output end of a comparator U6A, and the output end of the comparator UAB is connected with a +5V power supply through the resistor R51;
The AC phase subtraction circuit comprises a resistor R39, a resistor R40, a resistor R50 and a comparator UAC, wherein the non-inverting input end of the comparator UAC is connected with one end of a resistor R29 through the resistor R39, the inverting input end of the comparator UAC is simultaneously connected with one ends of a resistor R34 and a resistor R31 through the resistor R40, the other end of the resistor R34 is grounded, the other end of the resistor R31 is connected with the output end of the comparator U6C, and the output end of the comparator UAC is connected with a +5V power supply through the resistor R50;
the BC phase-subtracting circuit comprises a resistor R43, a resistor R44, a resistor R52 and a comparator UBC, wherein the non-inverting input end of the comparator UBC is connected with one end of the resistor R31 through the resistor R43, the inverting input end of the comparator UBC is connected with one end of the resistor R30 through the resistor R44, and the output end of the comparator UBC is connected with a +5V power supply through the resistor R52.
5. The high-speed heading digital converter according to claim 4, wherein the excitation signal comparing unit comprises a resistor R28, a resistor R35, a resistor R45, a resistor R46, a diode D4, a comparator USD and an exclusive or gate U10D, wherein an inverting input terminal of the comparator USD is connected to a cathode of the diode D4 and one end of the resistor R28 at the same time, the other end of the resistor R28 is connected to an output terminal of the comparator U6D, an anode of the diode D4 is grounded, a non-inverting input terminal of the comparator USD is connected to one end of the resistor R35 and one end of the resistor R45 at the same time, the other end of the resistor R35 is grounded, the other end of the resistor R45 is connected to an output terminal of the comparator USD, one end of the resistor R46 is connected to a +5v power supply, one input terminal of the exclusive or gate 10D is connected to an output terminal of the comparator USD, and the other input terminal of the exclusive or gate 10D is connected to the exclusive or gate 10D.
6. The high speed heading digitizer of claim 5, the exclusive OR unit comprises an A-phase difference or circuit, a B-phase difference or circuit, a C-phase difference or circuit, an AB-phase difference or circuit, an AC-phase difference or circuit and a BC-phase difference or circuit;
The A-phase exclusive OR circuit comprises an exclusive OR gate U10A and a resistor R147, wherein one input end of the exclusive OR gate U10A is connected with the output end of the comparator USA, the other input end of the exclusive OR gate U10A is connected with the output end of the exclusive OR gate U10D, the output end of the exclusive OR gate U10A is connected with one end of the resistor R147, and the other end of the resistor R147 is used as one output end of the analog signal processing circuit to be connected with the digital signal processing circuit;
The B-phase exclusive OR circuit comprises an exclusive OR gate U10B and a resistor R146, wherein one input end of the exclusive OR gate U10B is connected with the output end of the comparator USB, the other input end of the exclusive OR gate U10B is connected with the output end of the exclusive OR gate U10D, the output end of the exclusive OR gate U10B is connected with one end of the resistor R146, and the other end of the resistor R146 is used as one output end of the analog signal processing circuit to be connected with the digital signal processing circuit;
The C-phase exclusive OR circuit comprises an exclusive OR gate U10C and a resistor R145, wherein one input end of the exclusive OR gate U10C is connected with the output end of the comparator USC, the other input end of the exclusive OR gate U10C is connected with the output end of the exclusive OR gate U10D, the output end of the exclusive OR gate U10C is connected with one end of the resistor R145, and the other end of the resistor R145 is used as one output end of the analog signal processing circuit to be connected with the digital signal processing circuit;
the AB dissimilarity OR circuit comprises an exclusive OR gate U10AB and a resistor R149, wherein one input end of the exclusive OR gate U10AB is connected with the output end of the comparator UAB, the other input end of the exclusive OR gate U10AB is connected with the output end of the exclusive OR gate U10D, the output end of the exclusive OR gate U10AB is connected with one end of the resistor R149, and the other end of the resistor R149 is used as one output end of the analog signal processing circuit to be connected with the digital signal processing circuit;
The AC dissimilarity OR circuit comprises an exclusive OR gate U10AC and a resistor R148, wherein one input end of the exclusive OR gate U10AC is connected with the output end of the comparator UAC, the other input end of the exclusive OR gate U10AC is connected with the output end of the exclusive OR gate U10D, the output end of the exclusive OR gate U10AC is connected with one end of the resistor R148, and the other end of the resistor R148 is used as one output end of the analog signal processing circuit to be connected with the digital signal processing circuit;
The BC differential OR circuit comprises an exclusive OR gate U10BC and a resistor R150, wherein one input end of the exclusive OR gate U10BC is connected with the output end of the comparator UBC, the other input end of the exclusive OR gate U10BC is connected with the output end of the exclusive OR gate U10D, the output end of the exclusive OR gate U10BC is connected with one end of the resistor R150, and the other end of the resistor R150 is used as one output end of the analog signal processing circuit to be connected with the digital signal processing circuit.
7. The high speed heading digital converter of claim 1, wherein the power down detection circuit comprises a MAX706SEPA chip, a resistor R4, a resistor R5, a resistor R6, and a resistor R78, a PFI interface of the MAX706SEPA chip is connected to one end of the resistor R4 and one end of the resistor R5 at the same time, the other end of the resistor R4 is connected to a +5v power supply, the other end of the resistor R5 is grounded through the resistor R6, a GND interface of the MAX706SEPA chip is grounded, a VCC interface of the MAX706SEPA chip is connected to a power supply, and a PFO interface of the MAX706SEPA chip is connected to the resistor R78.
8. The high speed heading digital converter according to claim 1, wherein the data storage circuit comprises AN AT24C08AN chip, a resistor R72, a resistor R73 and a capacitor C60, wherein AN A0 interface, AN A1 interface, AN A2 interface and a GND interface of the AT24C08AN chip are all grounded, a VCC interface of the AT24C08AN chip is connected to a power supply, one end of the capacitor C60 is grounded, the other end of the capacitor C60 is connected to a VCC interface of the AT24C08AN chip, one end of the resistor R72 is connected to a VCC interface of the AT24C08AN chip, the other end of the resistor R72 is connected to AN SDA interface of the AT24C08AN chip, one end of the resistor R73 is connected to a VCC interface of the AT24C08AN chip, and the other end of the resistor R73 is connected to AN SCL interface of the AT24C08AN chip.
9. The high speed heading digitizer of claim 1, further comprising a digital display circuit comprising a nixie tube drive assembly, a bit code drive assembly, and a digital display assembly, wherein the inputs of the nixie tube drive assembly and the bit code drive assembly are both connected to the microprocessor module, and the outputs of the nixie tube drive assembly and the bit code drive assembly are both connected to the digital display assembly to obtain display information from the microprocessor module and drive the digital display assembly to display.
10. The high speed heading digitizer of claim 9, wherein the nixie tube drive assembly comprises a 74HC595 chip, the bit code drive assembly comprises a MC1413BD chip, and the digital display assembly comprises a SM420564 chip;
The Q0 interface of the 74HC595 chip is connected with the A interface of the SM420564 chip through a resistor R58, the Q1 interface of the 74HC595 chip is connected with the B interface of the SM420564 chip through a resistor R59, the Q2 interface of the 74HC595 chip is connected with the C interface of the SM420564 chip through a resistor R60, the Q3 interface of the 74HC595 chip is connected with the D interface of the SM420564 chip through a resistor R61, the Q4 interface of the 74HC595 chip is connected with the E interface of the SM420564 chip through a resistor R62, the Q5 interface of the 74HC595 chip is connected with the F interface of the SM420564 chip through a resistor R63, the Q6 interface of the 74HC595 chip is connected with the G interface of the SM420564 chip through a resistor R64, and the Q7 interface of the 74HC595 chip is connected with the Dp interface of the SM420564 chip through a resistor R65.
The OUT1 interface of MC1413BD chip pass through resistance R66 with the S1 interface connection of SM420564 chip, the OUT2 interface of MC1413BD chip pass through resistance R67 with the S2 interface connection of SM420564 chip, the OUT3 interface of MC1413BD chip pass through resistance R68 with the S3 interface connection of SM420564 chip, the OUT4 interface of MC1413BD chip pass through resistance R69 with the S4 interface connection of SM420564 chip.
CN202211035056.1A 2022-08-26 2022-08-26 High-speed course digital converter Active CN115371656B (en)

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