CN115371656A - High-speed course digital converter - Google Patents

High-speed course digital converter Download PDF

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Publication number
CN115371656A
CN115371656A CN202211035056.1A CN202211035056A CN115371656A CN 115371656 A CN115371656 A CN 115371656A CN 202211035056 A CN202211035056 A CN 202211035056A CN 115371656 A CN115371656 A CN 115371656A
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China
Prior art keywords
resistor
comparator
circuit
exclusive
chip
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CN202211035056.1A
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CN115371656B (en
Inventor
吴涛
张心钰
刘川
张俊华
罗先琼
陈耀山
刘益铭
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Csic Chongqing Changping Machinery Co ltd
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Csic Chongqing Changping Machinery Co ltd
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01C—MEASURING DISTANCES, LEVELS OR BEARINGS; SURVEYING; NAVIGATION; GYROSCOPIC INSTRUMENTS; PHOTOGRAMMETRY OR VIDEOGRAMMETRY
    • G01C17/00—Compasses; Devices for ascertaining true or magnetic north for navigation or surveying purposes
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01C—MEASURING DISTANCES, LEVELS OR BEARINGS; SURVEYING; NAVIGATION; GYROSCOPIC INSTRUMENTS; PHOTOGRAMMETRY OR VIDEOGRAMMETRY
    • G01C21/00—Navigation; Navigational instruments not provided for in groups G01C1/00 - G01C19/00
    • G01C21/10—Navigation; Navigational instruments not provided for in groups G01C1/00 - G01C19/00 by using measurements of speed or acceleration
    • G01C21/12—Navigation; Navigational instruments not provided for in groups G01C1/00 - G01C19/00 by using measurements of speed or acceleration executed aboard the object being navigated; Dead reckoning
    • G01C21/16—Navigation; Navigational instruments not provided for in groups G01C1/00 - G01C19/00 by using measurements of speed or acceleration executed aboard the object being navigated; Dead reckoning by integrating acceleration or speed, i.e. inertial navigation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude

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  • Engineering & Computer Science (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Remote Sensing (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Nonlinear Science (AREA)
  • Automation & Control Theory (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

The invention discloses a high-speed course digital converter, which comprises a microprocessor module, an autosyn signal circuit, an excitation signal circuit, an analog signal processing circuit, a power failure detection circuit and a data storage circuit, wherein the microprocessor module comprises a digital signal processing circuit and a main control chip; the signal circuit of the synchro is used for inputting the three-phase analog signal output by the synchro into the analog signal processing circuit; the excitation signal circuit is used for inputting an excitation signal into the analog signal processing circuit; the analog signal processing circuit is used for converting the three-phase analog signals into 6 paths of digital signals under the action of the excitation signals and inputting the digital signals into the digital signal processing circuit; the digital signal processing circuit is used for comparing the input 6 paths of digital signals with a set course initial value to obtain a real-time course signal. The invention can greatly improve the signal interaction capability of the ship by converting the analog course value of the compass into the digital course value.

Description

High-speed course digital converter
Technical Field
The invention relates to the technical field of communication navigation, in particular to a high-speed course digital converter.
Background
The electric compass, also known as gyrocompass, can automatically and continuously provide course signals of ships and warships, and transmit the course signals to each part of the ships and warships needing the course signals through the course transmitting device. Therefore, the system meets the requirements of ship navigation and armed systems, is indispensable precise navigation equipment for ships, and is called as the 'eye' of the ships.
The compass comprises a synchro, and when the compass sends a heading signal, an analog signal sent by the compass synchro is three sinusoidal alternating signals with phases of 120 degrees with each other. The course converter is an accessory instrument for intelligent interface of the electronic compass and other devices, and the demand for the course converter is increasing in the modern age with more and more outstanding intellectualization.
In the prior art, a course converter directly sends received analog signals of a synchrotron to each instrument needing course signals on a ship, and because the quantity of the instruments needing course signals on the ship is large and the installation positions of a plurality of instruments are far away from an electric compass, the course signals transmitted by the course converter cannot meet the requirements of the instruments on the ship, and meanwhile, the remote transmission of the analog signals has the problems of signal loss or distortion and the like, so that the course signals received by the instruments far away from the installation positions are inconsistent with the actual course signals of the ship, and further the navigation of the ship is influenced.
Disclosure of Invention
Aiming at the defects in the prior art, the technical problems to be solved by the invention are as follows: how to provide a high-speed course digital converter which can meet the requirement of each instrument on a ship on course signals and can avoid the problems of loss and distortion when the course signals are transmitted in a long distance.
In order to solve the technical problems, the invention adopts the following technical scheme:
a high-speed course digital converter comprises a microprocessor module, an autosyn signal circuit, an excitation signal circuit, an analog signal processing circuit, a power failure detection circuit and a data storage circuit, wherein the microprocessor module comprises a digital signal processing circuit and a main control chip;
the output end of the signal circuit of the synchro is in communication connection with the input end of the analog signal processing circuit and is used for inputting the three-phase analog signals output by the synchro into the analog signal processing circuit;
the output end of the excitation signal circuit is in communication connection with the input end of the analog signal processing circuit and is used for inputting the excitation signal into the analog signal processing circuit after attenuation and comparison processing;
the output end of the analog signal processing circuit is in communication connection with the input end of the digital signal processing circuit and is used for converting the three-phase analog signals output by the synchro into 6 paths of digital signals under the action of excitation signals and inputting the digital signals into the digital signal processing circuit;
the digital signal processing circuit is used for comparing the input 6 paths of digital signals with a set course initial value to obtain a real-time course signal;
the power failure detection circuit is in bidirectional communication connection with the microprocessor module and is used for comparing the voltage value of the main control chip with a voltage reference value and sending a low level signal to the main control chip when the voltage value of the main control chip is lower than the voltage reference value;
the data storage circuit is in bidirectional communication connection with the microprocessor module, the data storage circuit stores data when the main control chip receives a low level signal, and the main control chip reads the data stored in the last power failure from the data storage circuit when being electrified again so as to automatically match course information.
The working principle of the invention is as follows: therefore, when the high-speed course digital converter is used, the self-angle machine signal circuit receives three-phase analog signals from a self-angle machine, then the self-angle machine signal circuit inputs the received three-phase analog signals of the self-angle machine into the analog signal processing circuit for processing, meanwhile, the analog signal processing circuit also receives the excitation signals which are attenuated and compared in the excitation signal circuit, then the analog signal processing circuit converts the three-phase analog signals output by the self-angle machine into 6 paths of digital signals under the action of the excitation signals and outputs the digital signals to the digital signal processing circuit, the digital signal processing circuit sets a course initial value of a ship, the digital signal processing circuit compares the received 6 paths of digital signals with the course initial value, so that digital real-time signals of the ship can be obtained, then the digital real-time signals are sent to various instruments which need course information on the ship, no matter how many digital real-time signals are sent by the digital converter, the digital real-time signals can be sent to the ship, and all the digital real-time signals can be accurately transmitted to various instruments which need course information, so that the course signals are difficult to be transmitted to the digital converter can be compared with various course instruments which are difficult to obtain course information when the course signals.
Meanwhile, the navigation digital converter is also provided with a power failure detection circuit and a data storage circuit, the power failure detection circuit can send a low level signal to the main control chip when the power is off so as to store the data through the data storage circuit, and course information can be automatically matched by reading the data stored in the last power failure when the power is on again so as to avoid the problem that the course information needs to be matched again after each power failure.
Preferably, the analog signal processing circuit includes an attenuation unit, a comparison subtraction unit and an exclusive or unit, the attenuation unit is configured to perform attenuation processing on a three-phase analog signal output by the synchro, the comparison subtraction unit is configured to compare the three-phase analog signal after the attenuation processing with a reference value, compare the three-phase analog signal after the attenuation processing with each other, and output six paths of signals to the exclusive or unit, the exclusive or unit performs exclusive or operation on the six paths of digital signals with an excitation signal output by the excitation signal circuit and subjected to the attenuation processing and the comparison processing, and outputs six paths of digital signals to the digital signal processing circuit;
the excitation signal circuit comprises an excitation signal attenuation unit and an excitation signal comparison unit, the excitation signal attenuation unit is used for carrying out attenuation processing on the excitation signal, the excitation signal comparison unit is used for comparing the excitation signal subjected to attenuation processing with an excitation reference value, and outputting a comparison result to the XOR unit after carrying out XOR processing.
Preferably, the attenuation unit includes an a-phase attenuation circuit, a B-phase attenuation circuit and a C-phase attenuation circuit, the a-phase attenuation circuit includes a capacitor C25, a capacitor C28, a capacitor C29, a resistor R13, a resistor R14, a resistor R17, a resistor R18 and a comparator U6A, a non-inverting input terminal of the comparator U6A is grounded through the capacitor C25, an inverting input terminal of the comparator U6A is connected to an output terminal, an output terminal of the comparator U6A is simultaneously connected to one end of the capacitor C28 and one end of the capacitor C29, the other ends of the capacitor C28 and the capacitor C29 are simultaneously connected to one end of the resistor R17, the other end of the resistor R17 is connected to the non-inverting input terminal of the comparator U6A, one end of the resistor R13 is connected to the a-phase output terminal of the selsyn-angle machine signal circuit, the other end of the resistor R13 is simultaneously connected to one end of the resistor R18 and one end of the resistor R14, the other end of the resistor R14 is grounded, and the other end of the resistor R18 is connected to one end of the resistor R17;
the B-phase attenuation circuit comprises a capacitor C54, a capacitor C30, a capacitor C31, a resistor R9, a resistor R10, a resistor R19, a resistor R20 and a comparator U6B, wherein the non-inverting input end of the comparator U6B is grounded through the capacitor C54, the inverting input end of the comparator U6B is connected with the output end, the output end of the comparator U6B is simultaneously connected with one end of the capacitor C30 and one end of the capacitor C31, the other end of the capacitor C30 and the other end of the capacitor C31 are simultaneously connected with one end of the resistor R19, the other end of the resistor R19 is connected with the non-inverting input end of the comparator U6B, one end of the resistor R9 is connected with the B-phase output end of the selsyn signal circuit, the other end of the resistor R9 is simultaneously connected with one end of the resistor R10 and one end of the resistor R20, the other end of the resistor R10 is grounded, and the other end of the resistor R20 is connected with one end of the resistor R19;
the C-phase attenuation circuit comprises a capacitor C55, a capacitor C32, a capacitor C33, a resistor R11, a resistor R12, a resistor R21, a resistor R22 and a comparator U6C, wherein the non-inverting input end of the comparator U6C is grounded through the capacitor C55, the inverting input end of the comparator U6C is connected with the output end, the output end of the comparator U6C is simultaneously connected with one end of the capacitor C32 and one end of the capacitor C33, the other end of the capacitor C32 and the other end of the capacitor C33 are simultaneously connected with one end of the resistor R21, the other end of the resistor R21 is connected with the non-inverting input end of the comparator U6C, one end of the resistor R11 is connected with the C-phase output end of the auto-angle machine signal circuit, the other end of the resistor R11 is simultaneously connected with one end of the resistor R12 and one end of the resistor R22, the other end of the resistor R12 is grounded, and the other end of the resistor R22 is connected with one end of the resistor R21;
the excitation signal attenuation unit comprises a capacitor C56, a capacitor C34, a capacitor C35, a resistor R15, a resistor R16, a resistor R23, a resistor R24 and a comparator U6D, wherein the non-inverting input end of the comparator U6D is grounded through the capacitor C56, the inverting input end of the comparator U6D is connected with the output end, the output end of the comparator U6D is simultaneously connected with one end of the capacitor C34 and one end of the capacitor C35, the other end of the capacitor C34 and the other end of the capacitor C35 are simultaneously connected with one end of the resistor R23, the other end of the resistor R23 is connected with the non-inverting input end of the comparator U6D, one end of the resistor R15 is connected with an excitation signal, the other end of the resistor R15 is simultaneously connected with one end of the resistor R16 and one end of the resistor R24, the other end of the resistor R16 is grounded, and the other end of the resistor R24 is connected with one end of the resistor R23.
Preferably, the comparison subtraction unit includes an a comparison circuit, a B comparison circuit, a C comparison circuit, an AB phase subtraction circuit, an AC phase subtraction circuit, and a BC phase subtraction circuit;
the A phase comparison circuit comprises a resistor R25, a resistor R38, a resistor R49, a comparator USA and a diode D1, wherein the anode of the diode D1 is grounded, the cathode of the diode D1 is simultaneously connected with the inverting input end of the comparator USA and one end of the resistor R25, the other end of the resistor R25 is connected with the output end of the comparator U6A in the A phase attenuation circuit, the non-inverting input end of the comparator USA is grounded through the resistor R38, and the output end of the comparator USA is grounded through the resistor R49;
the B phase comparison circuit comprises a resistor R26, a resistor R37, a resistor R48, a comparator USB and a diode D2, wherein the anode of the diode D2 is grounded, the cathode of the diode D2 is simultaneously connected with the inverting input end of the comparator USB and one end of the resistor R26, the other end of the resistor R26 is connected with the output end of the comparator U6B in the B phase attenuation circuit, the non-inverting input end of the comparator USB is grounded through the resistor R37, and the output end of the comparator USB is grounded through the resistor R48;
the C comparison circuit comprises a resistor R27, a resistor R36, a resistor R47, a comparator USC and a diode D3, wherein the anode of the diode D3 is grounded, the cathode of the diode D3 is simultaneously connected with the inverting input end of the comparator USC and one end of the resistor R27, the other end of the resistor R27 is connected with the output end of the comparator U6C in the C-phase attenuation circuit, the non-inverting input end of the comparator USC is grounded through the resistor R36, and the output end of the comparator USB is grounded through the resistor R47;
the AB phase subtraction circuit comprises a resistor R41, a resistor R42, a resistor R51 and a comparator UAB, wherein the non-inverting input end of the comparator UAB is simultaneously connected with one ends of a resistor R33 and a resistor R30 through the resistor R41, the other end of the resistor R33 is grounded, the other end of the resistor R30 is connected with the output end of the comparator U6B, the inverting input end of the comparator UAB is simultaneously connected with one end of a resistor R32 and one end of a resistor R29 through the resistor R42, the other end of the resistor R32 is grounded, the other end of the resistor R29 is connected with the output end of the comparator U6A, and the output end of the comparator UAB is connected with a +5V power supply through the resistor R51;
the AC phase subtraction circuit comprises a resistor R39, a resistor R40, a resistor R50 and a comparator UAC, wherein the non-inverting input end of the comparator UAC is connected with one end of the resistor R29 through the resistor R39, the inverting input end of the comparator UAC is simultaneously connected with one ends of the resistor R34 and the resistor R31 through the resistor R40, the other end of the resistor R34 is grounded, the other end of the resistor R31 is connected with the output end of the comparator U6C, and the output end of the comparator UAC is connected with a +5V power supply through the resistor R50;
the BC phase subtraction circuit comprises a resistor R43, a resistor R44, a resistor R52 and a comparator UBC, wherein the non-inverting input end of the comparator UBC is connected with one end of the resistor R31 through the resistor R43, the inverting input end of the comparator UBC is connected with one end of the resistor R30 through the resistor R44, and the output end of the comparator UBC is connected with a +5V power supply through the resistor R52.
Preferably, the excitation signal comparison unit includes a resistor R28, a resistor R35, a resistor R45, a resistor R46, a diode D4, a comparator USD, and an exclusive or gate U10D, wherein an inverting input terminal of the comparator USD is simultaneously connected to a cathode of the diode D4 and one end of the resistor R28, the other end of the resistor R28 is connected to an output terminal of the comparator U6D, an anode of the diode D4 is grounded, a non-inverting input terminal of the comparator USD is simultaneously connected to one end of the resistor R35 and one end of the resistor R45, the other end of the resistor R35 is grounded, the other end of the resistor R45 is connected to an output terminal of the comparator USD, one end of the resistor R46 is connected to a +5V power supply, the other end of the resistor R46 is connected to an output terminal of the comparator USD, one input terminal of the exclusive or gate U10D is connected to an output terminal of the comparator USD, the other input terminal of the exclusive or gate U10D is grounded, and an output terminal of the exclusive or gate U10D is connected to the exclusive or gate unit.
Preferably, the exclusive or unit includes an a-phase exclusive or circuit, a B-phase exclusive or circuit, a C-phase exclusive or circuit, an AB-phase exclusive or circuit, an AC-phase exclusive or circuit, and a BC-phase exclusive or circuit;
the A exclusive-OR circuit comprises an exclusive-OR gate U10A and a resistor R147, one input end of the exclusive-OR gate U10A is connected with the output end of the comparator USA, the other input end of the exclusive-OR gate U10A is connected with the output end of the exclusive-OR gate U10D, the output end of the exclusive-OR gate U10A is connected with one end of the resistor R147, and the other end of the resistor R147 is used as one output end of the analog signal processing circuit and is connected with the digital signal processing circuit;
the B exclusive-OR circuit comprises an exclusive-OR gate U10B and a resistor R146, one input end of the exclusive-OR gate U10B is connected with the output end of the comparator USB, the other input end of the exclusive-OR gate U10B is connected with the output end of the exclusive-OR gate U10D, the output end of the exclusive-OR gate U10B is connected with one end of the resistor R146, and the other end of the resistor R146 is used as one output end of the analog signal processing circuit and is connected with the digital signal processing circuit;
the C exclusive or circuit comprises an exclusive or gate U10C and a resistor R145, one input end of the exclusive or gate U10C is connected with the output end of the comparator USC, the other input end of the exclusive or gate U10C is connected with the output end of the exclusive or gate U10D, the output end of the exclusive or gate U10C is connected with one end of the resistor R145, and the other end of the resistor R145 is connected with the digital signal processing circuit as one output end of the analog signal processing circuit;
the AB exclusive OR circuit comprises an exclusive OR gate U10AB and a resistor R149, one input end of the exclusive OR gate U10AB is connected with the output end of the comparator UAB, the other input end of the exclusive OR gate U10AB is connected with the output end of the exclusive OR gate U10D, the output end of the exclusive OR gate U10AB is connected with one end of the resistor R149, and the other end of the resistor R149, which serves as one output end of the analog signal processing circuit, is connected with the digital signal processing circuit;
the AC exclusive-OR circuit comprises an exclusive-OR gate U10AC and a resistor R148, wherein one input end of the exclusive-OR gate U10AC is connected with the output end of the comparator UAC, the other input end of the exclusive-OR gate U10AC is connected with the output end of the exclusive-OR gate U10D, the output end of the exclusive-OR gate U10AC is connected with one end of the resistor R148, and the other end of the resistor R148 is used as one output end of the analog signal processing circuit and is connected with the digital signal processing circuit;
the BC exclusive or circuit includes an exclusive or gate U10BC and a resistor R150, one input terminal of the exclusive or gate U10BC is connected to the output terminal of the comparator UBC, the other input terminal of the exclusive or gate U10BC is connected to the output terminal of the exclusive or gate U10D, the output terminal of the exclusive or gate U10BC is connected to one end of the resistor R150, and the other end of the resistor R150 is connected to the digital signal processing circuit as one output terminal of the analog signal processing circuit.
Preferably, the power failure detection circuit includes a MAX706SEPA chip, a resistor R4, a resistor R5, a resistor R6, and a resistor R78, a PFI interface of the MAX706SEPA chip is connected to one end of the resistor R4 and one end of the resistor R5, the other end of the resistor R4 is connected to a +5V power supply, the other end of the resistor R5 is grounded via the resistor R6, a GND interface of the MAX706SEPA chip is grounded, a VCC interface of the MAX706SEPA chip is connected to the power supply, and a PFO interface of the MAX706SEPA chip is connected to the resistor R78.
Preferably, the data storage circuit includes AN AT24C08AN chip, a resistor R72, a resistor R73, and a capacitor C60, where AN A0 interface, AN A1 interface, AN A2 interface, and a GND interface of the AT24C08AN chip are all grounded, a VCC interface of the AT24C08AN chip is connected to a power supply, one end of the capacitor C60 is grounded, the other end of the capacitor C60 is connected to a VCC interface of the AT24C08AN chip, one end of the resistor R72 is connected to a VCC interface of the AT24C08AN chip, the other end of the resistor R72 is connected to a SDA interface of the AT24C08AN chip, one end of the resistor R73 is connected to a VCC interface of the AT24C08AN chip, and the other end of the resistor R73 is connected to AN SCL interface of the AT24C08AN chip.
Preferably, the high-speed heading digitizer further comprises a digital display circuit, wherein the digital display circuit comprises a nixie tube driving component, a bit code driving component and a digital display component, the input ends of the nixie tube driving component and the bit code driving component are connected with the microprocessor module, and the output ends of the nixie tube driving component and the bit code driving component are connected with the digital display component so as to obtain display information from the microprocessor module and drive the digital display component to display.
Preferably, the nixie tube driving component comprises a 74HC595 chip, the bit code driving component comprises an MC1413BD chip, and the digital display component comprises an SM420564 chip;
the Q0 interface of the 74HC595 chip is connected to the a interface of the SM420564 chip through a resistor R58, the Q1 interface of the 74HC595 chip is connected to the B interface of the SM420564 chip through a resistor R59, the Q2 interface of the 74HC595 chip is connected to the C interface of the SM420564 chip through a resistor R60, the Q3 interface of the 74HC595 chip is connected to the D interface of the SM420564 chip through a resistor R61, the Q4 interface of the 74HC595 chip is connected to the E interface of the SM420564 chip through a resistor R62, the Q5 interface of the 74HC595 chip is connected to the F interface of the SM420564 chip through a resistor R63, the Q6 interface of the 74HC595 chip is connected to the G interface of the SM420564 chip through a resistor R64, and the Q7 interface of the 74HC595 chip is connected to the Dp 420564 chip through a resistor R65;
the OUT1 interface of the MC1413BD chip is connected with the S1 interface of the SM420564 chip through a resistor R66, the OUT2 interface of the MC1413BD chip is connected with the S2 interface of the SM420564 chip through a resistor R67, the OUT3 interface of the MC1413BD chip is connected with the S3 interface of the SM420564 chip through a resistor R68, and the OUT4 interface of the MC1413BD chip is connected with the S4 interface of the SM420564 chip through a resistor R69.
Compared with the prior art, the invention has the following advantages:
1. the invention can automatically track and display the course angle numerical value of the electric compass by collecting the analog signal output by the electric compass synchro and taking the excitation signal as the power supply and the reference signal, and then can output the course angle data of the electric compass to other equipment at fixed time in an RS-422 communication mode. Because the analog signal sent out by the compass synchro is three sine alternating signals which mutually form 120 degrees of phase, and has strict phase relation with the rotation of the synchro (when the ratio of the rotation speed of the compass to the rotation speed of the synchro is 1. By converting the analog course value of the compass into the digital course value, the signal interaction capacity of the ship can be greatly improved.
2. The power failure detection circuit mainly has the function of detecting the power failure of equipment so as to store the course value and other set parameters at the power failure moment, prevent data loss and avoid the need of re-matching the course value when the equipment is powered on next time. The power failure detection circuit monitors voltage by adopting a MAX706SEPA chip, and when the voltage is lower than a reference value, a low level signal is output to the main control chip, so that the main control chip finishes data storage operation.
3. The data storage circuit is mainly used for storing data AT the power-off moment, the AT24C08AN is used as a storage chip, and when the system is powered off, the data can be stored by the main control chip; when the system is powered on, the main control chip will first read the last stored value to automatically match the course value with other set parameters.
4. The invention selects a high-performance digital signal processor TMS320F2812 as a main control chip, the TMS320F2812 is a 32-bit fixed-point micro control unit, and the main frequency is up to 150MHz; the system is provided with bus interfaces such as I2C, SPI, CAN, PWM and the like, is suitable for various control industrial equipment, and is completely enough to process digital signals by using the ultra-high frequency of 150MHz aiming at the project, so that the course tracking capability CAN be obviously improved by increasing the acquisition and operation speed, and the tracking speed CAN be increased to 70 degrees/s from the original 14 degrees/s through actual measurement.
5. The invention is composed of high gain frequency compensation operational amplifier, analog comparator and input XOR gate analog signal processing circuit to receive the input from the synchro and excitation signal, output 6 high and low level comparison signal; the high-speed digital signal processing circuit acquires high and low level signals, and the high and low level signals are subjected to logic processing to obtain a course signal; the digital display circuit is communicated with the digital signal processing circuit through the SPI bus to refresh and display the current course in real time; the key circuit is responsible for course matching setting and brightness adjustment; the power failure detection circuit compares the current voltage with the reference voltage in real time, when the current voltage is lower than the reference voltage, the E2PROM stores the current course value and the display brightness value, and the course value and the display brightness value stored in the E2PROM are read when the main compass is started next time.
Drawings
FIG. 1 is a system diagram of a high speed heading digitizer according to the present invention;
FIG. 2 is a circuit diagram of an excitation signal circuit and an analog signal processing circuit in the high speed heading digitizer of the present invention;
FIG. 3 is a partial circuit diagram of the power down detection circuit in the high speed heading digitizer of the present invention;
FIG. 4 is a partial circuit diagram of a data storage circuit in the high speed heading digitizer of the present invention;
FIG. 5 is a partial circuit diagram of a digital display circuit in the high speed heading digitizer of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the drawings of the embodiments of the present invention. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the invention without inventive step, are within the scope of protection of the invention. Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs.
The use of "first," "second," and similar terms in the description and claims of the present application do not denote any order, quantity, or importance, but rather the terms are used to distinguish one element from another. Similarly, the singular forms "a," "an," or "the" do not denote a limitation of quantity, but rather denote the presence of at least one, unless the context clearly dictates otherwise. The terms "comprises" or "comprising," and the like, mean that the elements or components listed in the preceding list of elements or components include the features, integers, steps, operations, elements and/or components listed in the following list of elements or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof. "upper", "lower", "left", "right", and the like are used only to indicate relative positional relationships, and when the absolute position of the object to be described is changed, the relative positional relationships may also be changed accordingly.
As shown in the attached figure 1, the high-speed course digital converter comprises a microprocessor module, an autosyn signal circuit, an excitation signal circuit, an analog signal processing circuit, a power failure detection circuit and a data storage circuit, wherein the microprocessor module comprises a digital signal processing circuit and a main control chip;
the output end of the signal circuit of the synchro is in communication connection with the input end of the analog signal processing circuit and is used for inputting the three-phase analog signals output by the synchro into the analog signal processing circuit;
the output end of the excitation signal circuit is in communication connection with the input end of the analog signal processing circuit and is used for inputting the excitation signal into the analog signal processing circuit after attenuation and comparison processing;
the output end of the analog signal processing circuit is in communication connection with the input end of the digital signal processing circuit and is used for converting the three-phase analog signals output by the synchro into 6 paths of digital signals under the action of the excitation signals and inputting the digital signals into the digital signal processing circuit;
the digital signal processing circuit is used for comparing the input 6 paths of digital signals with a set course initial value to obtain a real-time course signal;
the power failure detection circuit is in bidirectional communication connection with the microprocessor module and is used for comparing the voltage value of the main control chip with a voltage reference value and sending a low-level signal to the main control chip when the voltage value of the main control chip is lower than the voltage reference value;
the data storage circuit is in bidirectional communication connection with the microprocessor module, the data storage circuit stores data when the main control chip receives a low level signal, and the main control chip reads the data stored in the last power-off state from the data storage circuit when being powered on again so as to automatically match course information.
The working principle of the invention is as follows: therefore, when the high-speed course digital converter is used, the self-angle machine signal circuit receives three-phase analog signals from a self-angle machine, then the self-angle machine signal circuit inputs the received three-phase analog signals of the self-angle machine into the analog signal processing circuit for processing, meanwhile, the analog signal processing circuit also receives the excitation signals which are attenuated and compared in the excitation signal circuit, then the analog signal processing circuit converts the three-phase analog signals output by the self-angle machine into 6 paths of digital signals under the action of the excitation signals and outputs the digital signals to the digital signal processing circuit, the digital signal processing circuit sets a course initial value of a ship, the digital signal processing circuit compares the received 6 paths of digital signals with the course initial value, so that digital real-time signals of the ship can be obtained, then the digital real-time signals are sent to various instruments which need course information on the ship, no matter how many digital real-time signals are sent by the digital converter, the digital real-time signals can be sent to the ship, and all the digital real-time signals can be accurately transmitted to various instruments which need course information, so that the course signals are difficult to be transmitted to the digital converter can be compared with various course instruments which are difficult to obtain course information when the course signals.
Meanwhile, the navigation digital converter is also provided with a power failure detection circuit and a data storage circuit, the power failure detection circuit can send a low level signal to the main control chip when the power is off so as to store the data through the data storage circuit, and course information can be automatically matched by reading the data stored in the last power failure when the power is on again so as to avoid the problem that the course information needs to be matched again after each power failure.
As shown in fig. 2, in this embodiment, the analog signal processing circuit includes an attenuation unit, a comparison subtraction unit and an exclusive or unit, the attenuation unit is configured to perform attenuation processing on a three-phase analog signal output by the synchro, the comparison subtraction unit is configured to compare the three-phase analog signal after the attenuation processing with a reference value, and simultaneously compare every two of the three-phase analog signal after the attenuation processing with each other and output six paths of signals to the exclusive or unit, and the exclusive or unit performs exclusive or operation on the six paths of digital signals with an excitation signal after the attenuation processing and the comparison processing output by the excitation signal circuit and outputs six paths of digital signals to the digital signal processing circuit;
the excitation signal circuit comprises an excitation signal attenuation unit and an excitation signal comparison unit, the excitation signal attenuation unit is used for carrying out attenuation processing on the excitation signal, the excitation signal comparison unit is used for comparing the excitation signal subjected to attenuation processing with an excitation reference value, and outputting the comparison result to the XOR unit after carrying out XOR processing.
In this embodiment, the attenuation unit includes an a-phase attenuation circuit, a B-phase attenuation circuit and a C-phase attenuation circuit, the a-phase attenuation circuit includes a capacitor C25, a capacitor C28, a capacitor C29, a resistor R13, a resistor R14, a resistor R17, a resistor R18 and a comparator U6A, a non-inverting input terminal of the comparator U6A is grounded through the capacitor C25, an inverting input terminal of the comparator U6A is connected to an output terminal, an output terminal of the comparator U6A is simultaneously connected to one end of the capacitor C28 and one end of the capacitor C29, the other end of the capacitor C28 and the other end of the capacitor C29 are simultaneously connected to one end of the resistor R17, the other end of the resistor R17 is connected to a non-inverting input terminal of the comparator U6A, one end of the resistor R13 is connected to an a-phase output terminal of the selsyn signal circuit, the other end of the resistor R13 is simultaneously connected to one end of the resistor R18 and one end of the resistor R14, the other end of the resistor R14 is grounded, and the other end of the resistor R18 is connected to one end of the resistor R17;
the B-phase attenuation circuit comprises a capacitor C54, a capacitor C30, a capacitor C31, a resistor R9, a resistor R10, a resistor R19, a resistor R20 and a comparator U6B, wherein the non-inverting input end of the comparator U6B is grounded through the capacitor C54, the inverting input end of the comparator U6B is connected with the output end, the output end of the comparator U6B is simultaneously connected with one end of the capacitor C30 and one end of the capacitor C31, the other end of the capacitor C30 and the other end of the capacitor C31 are simultaneously connected with one end of the resistor R19, the other end of the resistor R19 is connected with the non-inverting input end of the comparator U6B, one end of the resistor R9 is connected with the B-phase output end of the selsyn signal circuit, the other end of the resistor R9 is simultaneously connected with one end of the resistor R10 and one end of the resistor R20, the other end of the resistor R10 is grounded, and the other end of the resistor R20 is connected with one end of the resistor R19;
the C-phase attenuation circuit comprises a capacitor C55, a capacitor C32, a capacitor C33, a resistor R11, a resistor R12, a resistor R21, a resistor R22 and a comparator U6C, wherein the non-inverting input end of the comparator U6C is grounded through the capacitor C55, the inverting input end of the comparator U6C is connected with the output end, the output end of the comparator U6C is connected with one end of the capacitor C32 and one end of the capacitor C33 at the same time, the other end of the capacitor C32 and the other end of the capacitor C33 are connected with one end of the resistor R21 at the same time, the other end of the resistor R21 is connected with the non-inverting input end of the comparator U6C, one end of the resistor R11 is connected with the C-phase output end of the corner trimmer signal circuit, the other end of the resistor R11 is connected with one end of the resistor R12 and one end of the resistor R22 at the same time, the other end of the resistor R12 is grounded, and the other end of the resistor R22 is connected with one end of the resistor R21;
the excitation signal attenuation unit comprises a capacitor C56, a capacitor C34, a capacitor C35, a resistor R15, a resistor R16, a resistor R23, a resistor R24 and a comparator U6D, wherein the non-inverting input end of the comparator U6D is grounded through the capacitor C56, the inverting input end of the comparator U6D is connected with the output end, the output end of the comparator U6D is simultaneously connected with one end of the capacitor C34 and one end of the capacitor C35, the other end of the capacitor C34 and the other end of the capacitor C35 are simultaneously connected with one end of the resistor R23, the other end of the resistor R23 is connected with the non-inverting input end of the comparator U6D, one end of the resistor R15 is connected with an excitation signal, the other end of the resistor R15 is simultaneously connected with one end of the resistor R16 and one end of the resistor R24, the other end of the resistor R16 is grounded, and the other end of the resistor R24 is connected with one end of the resistor R23.
In this embodiment, the comparison subtraction unit includes an a-phase comparison circuit, a B-phase comparison circuit, a C-phase comparison circuit, an AB-phase subtraction circuit, an AC-phase subtraction circuit, and a BC-phase subtraction circuit;
the A comparison circuit comprises a resistor R25, a resistor R38, a resistor R49, a comparator USA and a diode D1, wherein the anode of the diode D1 is grounded, the cathode of the diode D1 is simultaneously connected with the inverting input end of the comparator USA and one end of the resistor R25, the other end of the resistor R25 is connected with the output end of a comparator U6A in the A phase attenuation circuit, the non-inverting input end of the comparator USA is grounded through the resistor R38, and the output end of the comparator USA is grounded through the resistor R49;
the B phase comparison circuit comprises a resistor R26, a resistor R37, a resistor R48, a comparator USB and a diode D2, wherein the anode of the diode D2 is grounded, the cathode of the diode D2 is connected with the inverting input end of the comparator USB and one end of the resistor R26 at the same time, the other end of the resistor R26 is connected with the output end of a comparator U6B in the B phase attenuation circuit, the non-inverting input end of the comparator USB is grounded through the resistor R37, and the output end of the comparator USB is grounded through the resistor R48;
the C phase comparison circuit comprises a resistor R27, a resistor R36, a resistor R47, a comparator USC and a diode D3, wherein the anode of the diode D3 is grounded, the cathode of the diode D3 is simultaneously connected with the inverting input end of the comparator USC and one end of the resistor R27, the other end of the resistor R27 is connected with the output end of a comparator U6C in the C phase attenuation circuit, the non-inverting input end of the comparator USC is grounded through the resistor R36, and the output end of a comparator USB is grounded through the resistor R47;
the AB phase subtraction circuit comprises a resistor R41, a resistor R42, a resistor R51 and a comparator UAB, wherein the non-inverting input end of the comparator UAB is simultaneously connected with one ends of a resistor R33 and a resistor R30 through the resistor R41, the other end of the resistor R33 is grounded, the other end of the resistor R30 is connected with the output end of a comparator U6B, the inverting input end of the comparator UAB is simultaneously connected with one end of a resistor R32 and one end of a resistor R29 through the resistor R42, the other end of the resistor R32 is grounded, the other end of the resistor R29 is connected with the output end of a comparator U6A, and the output end of the comparator UAB is connected with a +5V power supply through the resistor R51;
the AC phase subtraction circuit comprises a resistor R39, a resistor R40, a resistor R50 and a comparator UAC, wherein the non-inverting input end of the comparator UAC is connected with one end of the resistor R29 through the resistor R39, the inverting input end of the comparator UAC is simultaneously connected with one ends of the resistor R34 and the resistor R31 through the resistor R40, the other end of the resistor R34 is grounded, the other end of the resistor R31 is connected with the output end of a comparator U6C, and the output end of the comparator UAC is connected with a +5V power supply through the resistor R50;
the BC phase subtraction circuit comprises a resistor R43, a resistor R44, a resistor R52 and a comparator UBC, wherein the non-inverting input end of the comparator UBC is connected with one end of the resistor R31 through the resistor R43, the inverting input end of the comparator UBC is connected with one end of the resistor R30 through the resistor R44, and the output end of the comparator UBC is connected with a +5V power supply through the resistor R52.
In this embodiment, the excitation signal comparing unit includes a resistor R28, a resistor R35, a resistor R45, a resistor R46, a diode D4, a comparator USD and an exclusive or gate U10D, an inverting input terminal of the comparator USD is connected to both a cathode of the diode D4 and one end of the resistor R28, the other end of the resistor R28 is connected to an output terminal of the comparator U6D, an anode of the diode D4 is grounded, a non-inverting input terminal of the comparator USD is connected to both one end of the resistor R35 and one end of the resistor R45, the other end of the resistor R35 is grounded, the other end of the resistor R45 is connected to an output terminal of the comparator USD, one end of the resistor R46 is connected to a +5V power supply, the other end of the resistor R46 is connected to an output terminal of the comparator USD, one input terminal of the exclusive or gate U10D is connected to an output terminal of the comparator USD, the other input terminal of the exclusive or gate U10D is connected to the exclusive or unit.
In the present embodiment, the exclusive or unit includes an a-phase exclusive or circuit, a B-phase exclusive or circuit, a C-phase exclusive or circuit, an AB-phase exclusive or circuit, an AC-phase exclusive or circuit, and a BC-phase exclusive or circuit;
the A exclusive-OR circuit comprises an exclusive-OR gate U10A and a resistor R147, one input end of the exclusive-OR gate U10A is connected with the output end of the comparator USA, the other input end of the exclusive-OR gate U10A is connected with the output end of the exclusive-OR gate U10D, the output end of the exclusive-OR gate U10A is connected with one end of the resistor R147, and the other end of the resistor R147 is used as one output end of the analog signal processing circuit and is connected with the digital signal processing circuit;
the B exclusive OR circuit comprises an exclusive OR gate U10B and a resistor R146, one input end of the exclusive OR gate U10B is connected with the output end of the comparator USB, the other input end of the exclusive OR gate U10B is connected with the output end of the exclusive OR gate U10D, the output end of the exclusive OR gate U10B is connected with one end of the resistor R146, and the other end of the resistor R146 is used as one output end of the analog signal processing circuit and is connected with the digital signal processing circuit;
the C exclusive-OR circuit comprises an exclusive-OR gate U10C and a resistor R145, one input end of the exclusive-OR gate U10C is connected with the output end of the comparator USC, the other input end of the exclusive-OR gate U10C is connected with the output end of the exclusive-OR gate U10D, the output end of the exclusive-OR gate U10C is connected with one end of the resistor R145, and the other end of the resistor R145 is used as one output end of the analog signal processing circuit and is connected with the digital signal processing circuit;
the AB exclusive OR circuit comprises an exclusive OR gate U10AB and a resistor R149, one input end of the exclusive OR gate U10AB is connected with the output end of the comparator UAB, the other input end of the exclusive OR gate U10AB is connected with the output end of the exclusive OR gate U10D, the output end of the exclusive OR gate U10AB is connected with one end of the resistor R149, and the other end of the resistor R149, as one output end of the analog signal processing circuit, is connected with the digital signal processing circuit;
the AC exclusive-OR circuit comprises an exclusive-OR gate U10AC and a resistor R148, one input end of the exclusive-OR gate U10AC is connected with the output end of the comparator UAC, the other input end of the exclusive-OR gate U10AC is connected with the output end of the exclusive-OR gate U10D, the output end of the exclusive-OR gate U10AC is connected with one end of the resistor R148, and the other end of the resistor R148 is used as one output end of the analog signal processing circuit and is connected with the digital signal processing circuit;
the BC exclusive-OR circuit comprises an exclusive-OR gate U10BC and a resistor R150, one input end of the exclusive-OR gate U10BC is connected with the output end of the comparator UBC, the other input end of the exclusive-OR gate U10BC is connected with the output end of the exclusive-OR gate U10D, the output end of the exclusive-OR gate U10BC is connected with one end of the resistor R150, and the other end of the resistor R150 serving as one output end of the analog signal processing circuit is connected with the digital signal processing circuit.
As shown in fig. 3, in this embodiment, the power down detection circuit includes a MAX706SEPA chip, a resistor R4, a resistor R5, a resistor R6, and a resistor R78, a PFI interface of the MAX706SEPA chip is connected to one end of the resistor R4 and one end of the resistor R5 at the same time, the other end of the resistor R4 is connected to a +5V power supply, the other end of the resistor R5 is grounded via the resistor R6, a GND interface of the MAX706SEPA chip is grounded, a VCC interface of the MAX706SEPA chip is connected to the power supply, and a PFO interface of the MAX706SEPA chip is connected to the resistor R78.
As shown in fig. 4, in this embodiment, the data storage circuit includes AN AT24C08AN chip, a resistor R72, a resistor R73, and a capacitor C60, where AN A0 interface, AN A1 interface, AN A2 interface, and a GND interface of the AT24C08AN chip are all grounded, a VCC interface of the AT24C08AN chip is connected to a power supply, one end of the capacitor C60 is grounded, the other end of the capacitor C60 is connected to a VCC interface of the AT24C08AN chip, one end of the resistor R72 is connected to a VCC interface of the AT24C08AN chip, the other end of the resistor R72 is connected to a SDA interface of the AT24C08AN chip, one end of the resistor R73 is connected to a VCC interface of the AT24C08AN chip, and the other end of the resistor R73 is connected to AN SCL interface of the AT24C08AN chip.
As shown in fig. 5, in this embodiment, the high-speed heading digitizer further includes a digital display circuit, the digital display circuit includes a nixie tube driving component, a bit code driving component and a digital display component, the input ends of the nixie tube driving component and the bit code driving component are both connected to the microprocessor module, and the output ends of the nixie tube driving component and the bit code driving component are both connected to the digital display component, so as to obtain display information from the microprocessor module and drive the digital display component to display.
In this embodiment, the nixie tube driving component comprises a 74HC595 chip, the bit code driving component comprises an MC1413BD chip, and the digital display component comprises an SM420564 chip;
the Q0 interface of the 74HC595 chip is connected with the A interface of the SM420564 chip through a resistor R58, the Q1 interface of the 74HC595 chip is connected with the B interface of the SM420564 chip through a resistor R59, the Q2 interface of the 74HC595 chip is connected with the C interface of the SM420564 chip through a resistor R60, the Q3 interface of the 74HC595 chip is connected with the D interface of the SM420564 chip through a resistor R61, the Q4 interface of the 74HC595 chip is connected with the E interface of the SM420564 chip through a resistor R62, the Q5 interface of the 74HC595 chip is connected with the F interface of the SM420564 chip through a resistor R63, the Q6 interface of the 74HC595 chip is connected with the G interface of the SM420564 chip through a resistor R64, and the Q7 interface of the 74HC595 chip is connected with the Dxp interface of the SM420564 chip through a resistor R65;
the OUT1 interface of the MC1413BD chip is connected with the S1 interface of the SM420564 chip through a resistor R66, the OUT2 interface of the MC1413BD chip is connected with the S2 interface of the SM420564 chip through a resistor R67, the OUT3 interface of the MC1413BD chip is connected with the S3 interface of the SM420564 chip through a resistor R68, and the OUT4 interface of the MC1413BD chip is connected with the S4 interface of the SM420564 chip through a resistor R69.
The invention can automatically track and display the course angle numerical value of the electric compass by collecting the analog signal output by the electric compass synchro and taking the excitation signal as the power supply and the reference signal, and then can output the course angle data of the electric compass to other equipment at fixed time in an RS-422 communication mode. Because the analog signal sent out by the compass synchro is three sine alternating signals which mutually form 120 degrees of phase, and has strict phase relation with the rotation of the synchro (when the ratio of the rotation speed of the compass to the rotation speed of the synchro is 1. By converting the analog course value of the compass into the digital course value, the signal interaction capacity of the ship can be greatly improved.
The power failure detection circuit mainly has the function of detecting the power failure of equipment so as to store the course value and other set parameters at the power failure moment, prevent data loss and avoid the need of re-matching the course value when the equipment is powered on next time. The power failure detection circuit monitors voltage by adopting a MAX706SEPA chip, and when the voltage is lower than a reference value, a low level signal is output to the main control chip, so that the main control chip finishes data storage operation.
The data storage circuit is mainly used for storing data AT the power-off moment, the AT24C08AN is used as a storage chip, and when the system is powered off, the data can be stored by the main control chip; when the system is powered on, the main control chip will first read the last stored value to automatically match the course value and other set parameters.
The invention selects a high-performance digital signal processor TMS320F2812 as a main control chip, the TMS320F2812 is a 32-bit fixed-point micro control unit, and the main frequency is up to 150MHz; the system is provided with bus interfaces such as I2C, SPI, CAN, PWM and the like, is suitable for various control industrial equipment, and is completely enough to process digital signals by using the ultra-high frequency of 150MHz aiming at the project, so that the course tracking capability CAN be obviously improved by increasing the acquisition and operation speed, and the tracking speed CAN be increased to 70 degrees/s from the original 14 degrees/s through actual measurement.
The invention is composed of high gain frequency compensation operational amplifier, analog comparator and input XOR gate analog signal processing circuit to receive the input from the synchro and excitation signal, output 6 high and low level comparison signal; the high-speed digital signal processing circuit acquires high and low level signals and obtains a course signal after logic processing; the digital display circuit is communicated with the digital signal processing circuit through the SPI bus, and the current course is refreshed and displayed in real time; the key circuit is responsible for course matching setting and brightness adjustment; the power failure detection circuit compares the current voltage with the reference voltage in real time, when the current voltage is lower than the reference voltage, the E2PROM stores the current course value and the display brightness value, and the course value and the display brightness value stored in the E2PROM are read when the main compass is started next time.
Finally, it should be noted that the above embodiments are only used for illustrating the technical solutions of the present invention and not for limiting the technical solutions, and those skilled in the art should understand that modifications or equivalent substitutions can be made on the technical solutions of the present invention without departing from the spirit and scope of the technical solutions, and all that should be covered by the claims of the present invention.

Claims (10)

1. A high-speed course digital converter is characterized by comprising a microprocessor module, a synchro signal circuit, an excitation signal circuit, an analog signal processing circuit, a power failure detection circuit and a data storage circuit, wherein the microprocessor module comprises a digital signal processing circuit and a main control chip;
the output end of the signal circuit of the synchro is in communication connection with the input end of the analog signal processing circuit and is used for inputting the three-phase analog signals output by the synchro into the analog signal processing circuit;
the output end of the excitation signal circuit is in communication connection with the input end of the analog signal processing circuit and is used for inputting the excitation signal into the analog signal processing circuit after attenuation and comparison processing;
the output end of the analog signal processing circuit is in communication connection with the input end of the digital signal processing circuit and is used for converting the three-phase analog signal output by the synchro into 6 paths of digital signals under the action of an excitation signal and inputting the digital signals into the digital signal processing circuit;
the digital signal processing circuit is used for comparing the input 6 paths of digital signals with a set course initial value to obtain a real-time course signal;
the power failure detection circuit is in bidirectional communication connection with the microprocessor module and is used for comparing the voltage value of the main control chip with a voltage reference value and sending a low level signal to the main control chip when the voltage value of the main control chip is lower than the voltage reference value;
the data storage circuit is in bidirectional communication connection with the microprocessor module, the data storage circuit stores data when the main control chip receives a low level signal, and the main control chip reads the data stored in the last power-off state from the data storage circuit when being powered on again so as to automatically match course information.
2. The high-speed heading digitizer as claimed in claim 1, wherein the analog signal processing circuit comprises an attenuation unit, a comparison subtraction unit and an exclusive or unit, the attenuation unit is configured to attenuate a three-phase analog signal output from the synchro, the comparison subtraction unit is configured to compare the three-phase analog signal after the attenuation processing with a reference value, and compare the three-phase analog signal after the attenuation processing with each other and output six digital signals to the exclusive or unit, and the exclusive or unit is configured to output six digital signals to the digital signal processing circuit after performing exclusive or operation on the six digital signals and an excitation signal after the attenuation processing and the comparison processing output by the excitation signal circuit;
the excitation signal circuit comprises an excitation signal attenuation unit and an excitation signal comparison unit, the excitation signal attenuation unit is used for carrying out attenuation processing on the excitation signal, the excitation signal comparison unit is used for comparing the excitation signal subjected to attenuation processing with an excitation reference value, and outputting a comparison result to the XOR unit after carrying out XOR processing.
3. The high-speed heading digitizer as claimed in claim 2, wherein the attenuation unit comprises an a-phase attenuation circuit, a B-phase attenuation circuit and a C-phase attenuation circuit, the a-phase attenuation circuit comprises a capacitor C25, a capacitor C28, a capacitor C29, a resistor R13, a resistor R14, a resistor R17, a resistor R18 and a comparator U6A, a non-inverting input terminal of the comparator U6A is grounded via the capacitor C25, a non-inverting input terminal of the comparator U6A is connected to an output terminal, an output terminal of the comparator U6A is connected to one end of the capacitor C28 and one end of the capacitor C29 at the same time, the other end of the capacitor C28 and the other end of the capacitor C29 are connected to one end of the resistor R17 at the same time, the other end of the resistor R17 is connected to the non-inverting input terminal of the comparator U6A, one end of the resistor R13 is connected to the a-phase output terminal of the selsyn signal circuit, the other end of the resistor R13 is connected to one end of the resistor R18 and one end of the resistor R14 are grounded;
the B-phase attenuation circuit comprises a capacitor C54, a capacitor C30, a capacitor C31, a resistor R9, a resistor R10, a resistor R19, a resistor R20 and a comparator U6B, wherein the non-inverting input end of the comparator U6B is grounded through the capacitor C54, the inverting input end of the comparator U6B is connected with the output end, the output end of the comparator U6B is simultaneously connected with one end of the capacitor C30 and one end of the capacitor C31, the other end of the capacitor C30 and the other end of the capacitor C31 are simultaneously connected with one end of the resistor R19, the other end of the resistor R19 is connected with the non-inverting input end of the comparator U6B, one end of the resistor R9 is connected with the B-phase output end of the selsyn signal circuit, the other end of the resistor R9 is simultaneously connected with one end of the resistor R10 and one end of the resistor R20, the other end of the resistor R10 is grounded, and the other end of the resistor R20 is connected with one end of the resistor R19;
the C-phase attenuation circuit comprises a capacitor C55, a capacitor C32, a capacitor C33, a resistor R11, a resistor R12, a resistor R21, a resistor R22 and a comparator U6C, wherein the non-inverting input end of the comparator U6C is grounded through the capacitor C55, the inverting input end of the comparator U6C is connected with the output end, the output end of the comparator U6C is simultaneously connected with one end of the capacitor C32 and one end of the capacitor C33, the other end of the capacitor C32 and the other end of the capacitor C33 are simultaneously connected with one end of the resistor R21, the other end of the resistor R21 is connected with the non-inverting input end of the comparator U6C, one end of the resistor R11 is connected with the C-phase output end of the auto-angle machine signal circuit, the other end of the resistor R11 is simultaneously connected with one end of the resistor R12 and one end of the resistor R22, the other end of the resistor R12 is grounded, and the other end of the resistor R22 is connected with one end of the resistor R21;
the excitation signal attenuation unit comprises a capacitor C56, a capacitor C34, a capacitor C35, a resistor R15, a resistor R16, a resistor R23, a resistor R24 and a comparator U6D, the non-inverting input end of the comparator U6D is grounded through the capacitor C56, the inverting input end of the comparator U6D is connected with the output end, the output end of the comparator U6D is connected with one end of the capacitor C34 and one end of the capacitor C35, the other end of the capacitor C34 and the other end of the capacitor C35 are connected with one end of the resistor R23, the other end of the resistor R23 is connected with the non-inverting input end of the comparator U6D, one end of the resistor R15 is connected with an excitation signal, the other end of the resistor R15 is connected with one end of the resistor R16 and one end of the resistor R24, the other end of the resistor R16 is grounded, and the other end of the resistor R24 is connected with one end of the resistor R23.
4. The high-speed heading digitizer as claimed in claim 3, wherein the comparing and subtracting unit comprises an A-phase comparing circuit, a B-phase comparing circuit, a C-phase comparing circuit, an AB-phase subtracting circuit, an AC-phase subtracting circuit and a BC-phase subtracting circuit;
the A phase comparison circuit comprises a resistor R25, a resistor R38, a resistor R49, a comparator USA and a diode D1, wherein the anode of the diode D1 is grounded, the cathode of the diode D1 is simultaneously connected with the inverting input end of the comparator USA and one end of the resistor R25, the other end of the resistor R25 is connected with the output end of the comparator U6A in the A phase attenuation circuit, the non-inverting input end of the comparator USA is grounded through the resistor R38, and the output end of the comparator USA is grounded through the resistor R49;
the B phase comparison circuit comprises a resistor R26, a resistor R37, a resistor R48, a comparator USB and a diode D2, wherein the anode of the diode D2 is grounded, the cathode of the diode D2 is simultaneously connected with the inverting input end of the comparator USB and one end of the resistor R26, the other end of the resistor R26 is connected with the output end of the comparator U6B in the B phase attenuation circuit, the non-inverting input end of the comparator USB is grounded through the resistor R37, and the output end of the comparator USB is grounded through the resistor R48;
the C comparison circuit comprises a resistor R27, a resistor R36, a resistor R47, a comparator USC and a diode D3, wherein the anode of the diode D3 is grounded, the cathode of the diode D3 is simultaneously connected with the inverting input end of the comparator USC and one end of the resistor R27, the other end of the resistor R27 is connected with the output end of the comparator U6C in the C-phase attenuation circuit, the non-inverting input end of the comparator USC is grounded through the resistor R36, and the output end of the comparator USB is grounded through the resistor R47;
the AB phase subtraction circuit comprises a resistor R41, a resistor R42, a resistor R51 and a comparator UAB, wherein the non-inverting input end of the comparator UAB is simultaneously connected with one ends of a resistor R33 and a resistor R30 through the resistor R41, the other end of the resistor R33 is grounded, the other end of the resistor R30 is connected with the output end of the comparator U6B, the inverting input end of the comparator UAB is simultaneously connected with one end of a resistor R32 and one end of a resistor R29 through the resistor R42, the other end of the resistor R32 is grounded, the other end of the resistor R29 is connected with the output end of the comparator U6A, and the output end of the comparator UAB is connected with a +5V power supply through the resistor R51;
the AC phase subtraction circuit comprises a resistor R39, a resistor R40, a resistor R50 and a comparator UAC, wherein the non-inverting input end of the comparator UAC is connected with one end of the resistor R29 through the resistor R39, the inverting input end of the comparator UAC is simultaneously connected with one ends of the resistor R34 and the resistor R31 through the resistor R40, the other end of the resistor R34 is grounded, the other end of the resistor R31 is connected with the output end of the comparator U6C, and the output end of the comparator UAC is connected with a +5V power supply through the resistor R50;
the BC phase subtraction circuit comprises a resistor R43, a resistor R44, a resistor R52 and a comparator UBC, wherein the non-inverting input end of the comparator UBC is connected with one end of the resistor R31 through the resistor R43, the inverting input end of the comparator UBC is connected with one end of the resistor R30 through the resistor R44, and the output end of the comparator UBC is connected with a +5V power supply through the resistor R52.
5. The high-speed heading digitizer as claimed in claim 4, wherein the excitation signal comparing unit includes a resistor R28, a resistor R35, a resistor R45, a resistor R46, a diode D4, a comparator USD and an exclusive or gate U10D, an inverting input terminal of the comparator USD is connected to the cathode of the diode D4 and one end of the resistor R28, the other end of the resistor R28 is connected to the output terminal of the comparator U6D, an anode of the diode D4 is grounded, a non-inverting input terminal of the comparator USD is connected to one end of the resistor R35 and one end of the resistor R45, the other end of the resistor R35 is grounded, the other end of the resistor R45 is connected to the output terminal of the comparator USD, one end of the resistor R46 is connected to the +5V power supply, the other end of the resistor R46 is connected to the output terminal of the comparator USD, one input terminal of the exclusive or gate U10D is connected to the output terminal of the comparator USD, the other input terminal of the exclusive or gate U10D is connected to the exclusive or gate U10D, and an output terminal of the exclusive or gate U10D is connected to the exclusive or gate unit.
6. The high speed heading digitizer as claimed in claim 5, wherein the XOR unit comprises an A-phase exclusive OR circuit, a B-phase exclusive OR circuit, a C-phase exclusive OR circuit, an AB-phase exclusive OR circuit, an AC-phase exclusive OR circuit, and a BC-phase exclusive OR circuit;
the A exclusive-OR circuit comprises an exclusive-OR gate U10A and a resistor R147, one input end of the exclusive-OR gate U10A is connected with the output end of the comparator USA, the other input end of the exclusive-OR gate U10A is connected with the output end of the exclusive-OR gate U10D, the output end of the exclusive-OR gate U10A is connected with one end of the resistor R147, and the other end of the resistor R147 is used as one output end of the analog signal processing circuit and is connected with the digital signal processing circuit;
the B exclusive-OR circuit comprises an exclusive-OR gate U10B and a resistor R146, one input end of the exclusive-OR gate U10B is connected with the output end of the comparator USB, the other input end of the exclusive-OR gate U10B is connected with the output end of the exclusive-OR gate U10D, the output end of the exclusive-OR gate U10B is connected with one end of the resistor R146, and the other end of the resistor R146 is used as one output end of the analog signal processing circuit and is connected with the digital signal processing circuit;
the C exclusive or circuit comprises an exclusive or gate U10C and a resistor R145, one input end of the exclusive or gate U10C is connected with the output end of the comparator USC, the other input end of the exclusive or gate U10C is connected with the output end of the exclusive or gate U10D, the output end of the exclusive or gate U10C is connected with one end of the resistor R145, and the other end of the resistor R145 is connected with the digital signal processing circuit as one output end of the analog signal processing circuit;
the AB exclusive OR circuit comprises an exclusive OR gate U10AB and a resistor R149, one input end of the exclusive OR gate U10AB is connected with the output end of the comparator UAB, the other input end of the exclusive OR gate U10AB is connected with the output end of the exclusive OR gate U10D, the output end of the exclusive OR gate U10AB is connected with one end of the resistor R149, and the other end of the resistor R149, which serves as one output end of the analog signal processing circuit, is connected with the digital signal processing circuit;
the AC exclusive-OR circuit comprises an exclusive-OR gate U10AC and a resistor R148, wherein one input end of the exclusive-OR gate U10AC is connected with the output end of the comparator UAC, the other input end of the exclusive-OR gate U10AC is connected with the output end of the exclusive-OR gate U10D, the output end of the exclusive-OR gate U10AC is connected with one end of the resistor R148, and the other end of the resistor R148 is used as one output end of the analog signal processing circuit and is connected with the digital signal processing circuit;
the BC exclusive or circuit includes an exclusive or gate U10BC and a resistor R150, one input terminal of the exclusive or gate U10BC is connected to the output terminal of the comparator UBC, the other input terminal of the exclusive or gate U10BC is connected to the output terminal of the exclusive or gate U10D, the output terminal of the exclusive or gate U10BC is connected to one end of the resistor R150, and the other end of the resistor R150 is connected to the digital signal processing circuit as one output terminal of the analog signal processing circuit.
7. The high-speed heading digitizer as claimed in claim 1, wherein the power down detection circuit comprises a MAX706SEPA chip, a resistor R4, a resistor R5, a resistor R6 and a resistor R78, a PFI interface of the MAX706SEPA chip is connected to one end of the resistor R4 and one end of the resistor R5 at the same time, the other end of the resistor R4 is connected to a +5V power supply, the other end of the resistor R5 is grounded through the resistor R6, a GND interface of the MAX706SEPA chip is grounded, a VCC interface of the MAX706SEPA chip is connected to a power supply, and a PFO interface of the MAX706SEPA chip is connected to the resistor R78.
8. The high-speed heading digitizer as claimed in claim 1, wherein the data storage circuit includes AN AT24C08AN chip, a resistor R72, a resistor R73 and a capacitor C60, AN A0 interface, AN A1 interface, AN A2 interface and a GND interface of the AT24C08AN chip are all grounded, a VCC interface of the AT24C08AN chip is connected to a power supply, one end of the capacitor C60 is grounded, the other end of the capacitor C60 is connected to the VCC interface of the AT24C08AN chip, one end of the resistor R72 is connected to the VCC interface of the AT24C08AN chip, the other end of the resistor R72 is connected to AN SDA interface of the AT24C08AN chip, one end of the resistor R73 is connected to the VCC interface of the AT24C08AN chip, and the other end of the resistor R73 is connected to AN SCL interface of the AT24C08AN chip.
9. The high-speed heading digitizer as claimed in claim 1, further comprising a digital display circuit, wherein the digital display circuit comprises a nixie tube driver, a bit code driver and a digital display, wherein the nixie tube driver and the bit code driver have input terminals connected to the microprocessor module, and output terminals connected to the digital display for obtaining display information from the microprocessor module and driving the digital display to display.
10. The high speed heading digitizer as claimed in claim 9, wherein the nixie tube driver component comprises a 74HC595 chip, the bit code driver component comprises a MC1413BD chip, and the digital display component comprises an SM420564 chip;
the Q0 interface of the 74HC595 chip is connected to the a interface of the SM420564 chip through a resistor R58, the Q1 interface of the 74HC595 chip is connected to the B interface of the SM420564 chip through a resistor R59, the Q2 interface of the 74HC595 chip is connected to the C interface of the SM420564 chip through a resistor R60, the Q3 interface of the 74HC595 chip is connected to the D interface of the SM420564 chip through a resistor R61, the Q4 interface of the 74HC595 chip is connected to the E interface of the SM420564 chip through a resistor R62, the Q5 interface of the 74HC595 chip is connected to the F interface of the SM420564 chip through a resistor R63, the Q6 interface of the 74HC595 chip is connected to the G interface of the SM420564 chip through a resistor R64, and the Q7 interface of the 74HC595 chip is connected to the Dp 420564 chip through a resistor R65;
the OUT1 interface of the MC1413BD chip is connected with the S1 interface of the SM420564 chip through a resistor R66, the OUT2 interface of the MC1413BD chip is connected with the S2 interface of the SM420564 chip through a resistor R67, the OUT3 interface of the MC1413BD chip is connected with the S3 interface of the SM420564 chip through a resistor R68, and the OUT4 interface of the MC1413BD chip is connected with the S4 interface of the SM420564 chip through a resistor R69.
CN202211035056.1A 2022-08-26 2022-08-26 High-speed course digital converter Active CN115371656B (en)

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