CN115361795A - Semi-additive process method of FCBGA substrate - Google Patents
Semi-additive process method of FCBGA substrate Download PDFInfo
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- CN115361795A CN115361795A CN202211022518.6A CN202211022518A CN115361795A CN 115361795 A CN115361795 A CN 115361795A CN 202211022518 A CN202211022518 A CN 202211022518A CN 115361795 A CN115361795 A CN 115361795A
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- additive process
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- 238000000034 method Methods 0.000 title claims abstract description 61
- 239000000758 substrate Substances 0.000 title claims abstract description 60
- 230000008569 process Effects 0.000 title claims abstract description 39
- 239000000654 additive Substances 0.000 title claims abstract description 26
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 45
- 239000011889 copper foil Substances 0.000 claims abstract description 26
- 229910052802 copper Inorganic materials 0.000 claims abstract description 16
- 239000010949 copper Substances 0.000 claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 claims abstract description 16
- 238000004806 packaging method and process Methods 0.000 claims abstract description 16
- 238000010438 heat treatment Methods 0.000 claims abstract description 13
- 238000010030 laminating Methods 0.000 claims abstract description 8
- 238000007747 plating Methods 0.000 claims description 25
- 238000009713 electroplating Methods 0.000 claims description 20
- 229910000679 solder Inorganic materials 0.000 claims description 13
- 238000005553 drilling Methods 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 10
- 230000001681 protective effect Effects 0.000 claims description 10
- 239000003292 glue Substances 0.000 claims description 5
- 229910000831 Steel Inorganic materials 0.000 claims description 4
- 238000002955 isolation Methods 0.000 claims description 4
- 239000010959 steel Substances 0.000 claims description 4
- 238000001259 photo etching Methods 0.000 claims description 3
- 238000003825 pressing Methods 0.000 claims description 3
- 238000007788 roughening Methods 0.000 claims description 2
- 238000004880 explosion Methods 0.000 abstract description 4
- 238000013461 design Methods 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 107
- 238000010586 diagram Methods 0.000 description 7
- 238000003672 processing method Methods 0.000 description 4
- 239000002904 solvent Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000005187 foaming Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 239000002893 slag Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The invention provides a semi-additive process method of an FCBGA substrate, and relates to the technical field of manufacturing of packaging substrates. The method comprises the following steps: step S1, sequentially laminating an ABF layer and a copper foil on the surface of an inner layer circuit of a packaging substrate; s2, placing the laminated ABF layer in an oven for baking to finish pre-curing; s3, carrying out vacuum heating and pressurization on the pre-cured ABF layer to completely cure the ABF layer; s4, removing the copper foil, and manufacturing an outer layer circuit on the completely cured ABF layer; and S5, repeating the steps S1 to S4 to form the multilayer circuit packaging substrate. The invention can solve the technical problem of large copper sheet explosion, ensure the reliability of the substrate, reduce the process limitation, improve the design freedom, reduce the process window, improve the yield and reduce the substrate warpage.
Description
Technical Field
The invention relates to the technical field of packaging substrate manufacturing, in particular to a semi-additive process method of an FCBGA substrate.
Background
Due to the requirement of high-density wiring, the main process of manufacturing FCBGA (Flip Chip Ball Grid Array) substrates is semi-additive. Not only is the problem of copper wiring technology, but the technology generally uses only ABF (Ajinomoto Build-up Film) material as the insulating layer. In other words, only ABF materials enable the fabrication of high density wiring with semi-additive methods.
Due to the nature of the material, the ABF material contains a certain amount of solvent, and the solvent is removed in the manufacturing process of the substrate, and after the wiring layers are accumulated in a plurality of layers, the solvent accumulated in the substrate is easy to cause foaming and board explosion of the substrate. Continuous large-area copper sheets cannot be arranged in the wiring metal layer of the substrate, and air holes with certain intervals must be processed in the area needing the copper sheets so that gas in the ABF layer can be removed through the air holes, and plate explosion is avoided.
Disclosure of Invention
In view of the above problems, the present invention provides a semi-additive process method for an FCBGA substrate, which avoids board explosion caused by a large copper sheet.
In order to achieve the above object, the present invention provides a semi-additive process method for an FCBGA substrate, comprising: s1, sequentially pressing an ABF layer 3 and a copper foil 4 on the surface of an inner layer circuit 2 of a packaging substrate; s2, placing the laminated ABF layer 3 in an oven for baking to finish pre-curing; s3, carrying out vacuum heating and pressurizing on the pre-cured ABF layer 3 to completely cure the ABF layer 3; step S4, removing the copper foil 4, and manufacturing an outer layer circuit 9 on the completely cured ABF layer 3; and S5, repeating the steps S1 to S4 to form the multilayer circuit packaging substrate.
Further, before the step S1 of sequentially laminating the ABF layer 3 and the copper foil 4, the method further includes: the surface of the inner layer wire 2 is roughened.
Further, in step S2, the pressed ABF layer 3 is baked in an oven, which includes: baking at 130 deg.C for 30min, and baking at 180 deg.C for 60min.
Further, in step S3, the vacuum heating and pressurizing of the pre-cured ABF layer 3 includes: the pre-cured ABF layer 3 is placed under vacuum conditions, and the ABF layer 3 is completely cured by heating and pressurizing under the clamping of a mirror isolation steel plate of a laminating machine.
Furthermore, the temperature after heating is 190-210 ℃, and the pressure after pressurization is more than 1MPa.
Further, in step S4, the copper foil 4 is removed, and the outer layer wiring 9 is fabricated on the fully cured ABF layer 3, including: step S41, laser drilling is carried out on the completely cured ABF layer 3 and the copper foil 4, so that a blind hole 5 communicated with the inner layer circuit 2 is formed in the ABF layer 3 and the copper foil 4; s42, removing residual glue residues of laser drilling; step S43, removing the surface copper foil 4; step S44, chemically plating copper in the ABF layer 3 and the blind holes 5 to form a plating seed layer 6; step S45, forming a pattern electroplating mask 7 on the electroplating seed layer 6 by photoetching; step S46, forming a circuit pattern 8 in the electroplating seed layer 6 in the area uncovered by the pattern electroplating mask 7 by electroplating and filling the blind hole 5; step S47, removing the pattern electroplating mask 7; in step S48, the plating seed layer 6 covered by the pattern plating mask 7 is removed to form the outer layer wiring 9.
Further, in step S44, the thickness of the plating seed layer 6 is 0.3 μm to 1 μm.
Further, in step S5, after the multilayer circuit package substrate is formed, the method further includes: a solder resist layer 10 is formed on the outermost layer of the multilayer circuit package substrate.
Further, after the solder resist layer 10 is fabricated, the method further includes: an organic protective film 11 is coated on the outermost layer of the multilayer wiring package substrate in a region not covered with the solder resist layer 10.
Further, the material of the organic protective film 11 includes any one of NiAu, niPdAu, OSP, and Sn.
Compared with the prior art, the semi-additive process method of the FCBGA substrate provided by the invention at least has the following beneficial effects:
(1) The large copper sheet does not explode, so that the reliability of the substrate is ensured;
(2) The process limitation is reduced, and the design freedom is improved;
(3) The process window is reduced, and the yield is improved;
(4) The warpage of the substrate is reduced.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:
FIG. 1 schematically illustrates an operational flow diagram of a semi-additive processing method of an FCBGA substrate, in accordance with an embodiment of the present invention;
FIG. 2 schematically illustrates a process flow diagram of a semi-additive processing method of an FCBGA substrate according to an embodiment of the present invention;
FIG. 3 schematically illustrates an operational flow diagram of a fabrication process for outer layer circuitry in accordance with an embodiment of the present invention;
FIG. 4 schematically illustrates a process flow diagram of a fabrication process for an outer layer circuit according to an embodiment of the invention;
FIG. 5 schematically illustrates a block diagram of a multilayer circuit package substrate according to an embodiment of the invention;
fig. 6 schematically shows a structural view of a solder resist layer according to an embodiment of the present invention;
fig. 7 schematically shows a structural view of an organic protective film according to an embodiment of the present invention.
[ description of reference ]
1-a core plate; 2-inner layer circuit; 3-ABF layer; 4-copper foil; 5-blind holes; 6-electroplating seed layer; 7-pattern electroplating mask; 8-circuit pattern; 9-outer layer circuit; 10-a solder mask layer; 11-organic protective film.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to specific embodiments and the accompanying drawings. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The terms "comprises," "comprising," and the like, as used herein, specify the presence of stated features, steps, operations, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, or components.
All terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs, unless otherwise defined. It is noted that the terms used herein should be interpreted as having a meaning that is consistent with the context of this specification and should not be interpreted in an idealized or overly formal sense.
Fig. 1 schematically illustrates an operational flow diagram of a semi-additive processing method of an FCBGA substrate in accordance with an embodiment of the present invention. Fig. 2 schematically illustrates a process flow diagram of a semi-additive processing method of an FCBGA substrate in accordance with an embodiment of the present invention.
Referring to fig. 1 and 2, the semi-additive process method for FCBGA substrate according to this embodiment may include steps S1 to S5.
And S1, sequentially laminating an ABF layer 3 and a copper foil 4 on the surface of the inner layer circuit 2 of the packaging substrate.
The innermost layer material of the packaging substrate is a core board 1, and a copper circuit is manufactured on the core board 1 to be used as an inner layer circuit 2. The manufacturing method and structure of the inner layer circuit 2 are the same as those of a conventional printed circuit board, for example, as shown in fig. 2, a through groove is formed in the core board 1, and the through groove penetrates through the upper and lower surfaces of the core board 1. The inner layer circuit 2 is filled in the through groove and extends to the upper surface and the lower surface of the core board 1.
Before the ABF layer 3 and the copper foil 4 are sequentially laminated, the surface of the inner layer circuit 2 needs to be roughened so as to improve the bonding force between the inner layer circuit 2 and the ABF layer 3.
The embodiment of the invention adopts the ABF layer product as the interlayer insulating material of the circuit, and can be used for manufacturing a precise circuit on the surface of the material by adopting a semi-additive process.
Next, on the surface of the inner layer circuit 2, a vacuum laminator may be used to laminate the ABF layer 3 first and then laminate the copper foil 4 on the surface of the ABF layer 3 at a temperature lower than the conventional temperature.
And S2, placing the laminated ABF layer 3 in an oven for baking to finish pre-curing.
The step adopts low-temperature baking, and the main purpose of the step is to remove water vapor absorbed by the packaging substrate in the processing process. Specifically, the pressed ABF layer 3 is baked in an oven, which may be baked at 130 ℃ for 30min and then at 180 ℃ for 60min. After baking, the degree of cure of the ABF layer 3 slightly increased.
And S3, heating and pressurizing the pre-cured ABF layer 3 in vacuum to completely cure the ABF layer 3.
In an embodiment of the present invention, the vacuum heating and pressurizing the pre-cured ABF layer 3 may include: the pre-cured ABF layer 3 is placed under vacuum conditions, and the ABF layer 3 is completely cured by heating and pressurizing under the clamping of a mirror isolation steel plate of a laminating machine.
Furthermore, the temperature after heating can be 190-210 ℃, and the pressure after pressurization can be more than 1MPa.
In the conventional ABF curing, after the ABF surface circuit is manufactured, the ABF surface circuit is baked in an oven at 130 ℃ for 30 minutes and then baked in an oven at 190-210 ℃ for 1 hour. In the embodiment of the invention, the pre-cured packaging substrate is clamped by a mirror surface isolation steel plate in a laminating machine, and the ABF is completely cured in a vacuum chamber under the action of temperature and pressure.
Step S4, the copper foil 4 is removed, and the outer layer wiring 9 is manufactured on the completely cured ABF layer 3.
And S5, repeating the steps S1 to S4 to form the multilayer circuit packaging substrate.
Thus, the outer layer circuit 9 is formed on the surface of the completely cured ABF layer 3, and the steps are repeated using the formed outer layer circuit 9 as the inner layer circuit 2, thereby obtaining a multilayer circuit package substrate.
To specifically explain the manufacturing process of the outer layer wire 9, fig. 3 schematically shows an operation flowchart of the manufacturing process of the outer layer wire according to an embodiment of the present invention, and fig. 4 schematically shows a process flowchart of the manufacturing process of the outer layer wire according to an embodiment of the present invention.
Referring to fig. 3 and 4, in the embodiment of the invention, in the step S4, the copper foil 4 is removed, and the outer layer circuit 9 is manufactured on the fully cured ABF layer 3, which may further include steps S41 to S48.
Step S41, laser drilling is performed on the completely cured ABF layer 3 and the copper foil 4, so that the blind hole 5 communicating with the inner layer circuit 2 is formed in the ABF layer 3 and the copper foil 4.
Laser drilling is carried out, so that blind holes 5 communicated with the inner layer circuit 2 are formed in the ABF layer 3 and the copper foil 4, and an interlayer mutual communication channel is formed.
It should be noted that the conventional laser drilling process is performed on the pre-cured ABF surface. Unlike conventional processes, the laser drilling process of the present embodiment is performed on the surface of the fully cured ABF layer 3.
And S42, removing the residual glue residues of the laser drilling.
And removing residual glue slag carried by laser drilling in the blind hole 5. Unlike the conventional process, the conventional process removes the glue on the surface of the pre-cured ABF pores.
In step S43, the surface copper foil 4 is removed.
Thereby, the ABF layer 3 and the blind hole 5 are exposed to the outside.
In step S44, copper is chemically plated in the ABF layer 3 and the blind via 5 to form a plating seed layer 6.
Electroless copper plating can provide conductivity for subsequent plating. Unlike conventional electroless copper plating, which is deposited on the surface of the pre-cured ABF, the electroless copper plating of the embodiment of the present invention is deposited on the surface of the fully cured ABF layer 3 without performing a de-gumming roughening treatment on the non-porous region of the ABF layer 3.
Further, the thickness of the plating seed layer 6 may be 0.3 μm to 1 μm.
In step S45, a patterned plating mask 7 is formed on the plating seed layer 6 by photolithography.
And pressing a dry film on the electroplating seed layer 6, and photoetching and developing to form a patterned electroplating mask 7.
In step S46, the circuit pattern 8 is formed by electroplating in the area of the plating seed layer 6 not covered by the pattern plating mask 7 and the blind via 5 is filled.
This step is pattern plating for plating out the circuit pattern 8.
In step S47, the pattern plating mask 7 is removed.
In step S48, the plating seed layer 6 covered by the pattern plating mask 7 is removed to form the outer layer wiring 9.
The plating seed layer covered by the patterned plating mask 7 is removed by rapid etching to form an outer layer wiring 9.
Next, fig. 5 schematically shows a structural view of a multilayer wiring package substrate according to an embodiment of the present invention.
As shown in fig. 5, in the embodiment of the present invention, the manufactured outer layer wiring 9 is used as the inner layer wiring 2, and the above steps S1 to S4 are repeated to alternately stack the inner layer wiring 2, the ABF layer 3, and the outer layer wiring 9, thereby obtaining the multilayer wiring package substrate.
Fig. 6 schematically shows a structure of a solder resist layer according to an embodiment of the present invention.
As shown in fig. 6, in the embodiment of the present invention, after the step S5 of forming the multilayer circuit package substrate, the method may further include: a solder resist layer 10 is formed on the outermost layer of the multilayer circuit package substrate. The solder mask layer is used as a protective layer, can be coated on a circuit or a base material of the packaging substrate without being welded, and can also protect the formed circuit pattern for a long time.
Fig. 7 schematically shows a structural view of an organic protective film according to an embodiment of the present invention.
As shown in fig. 7, in the embodiment of the present invention, after the solder mask layer 10 is manufactured, the method may further include: an organic protective film 11 is coated on the outermost layer of the multilayer wiring package substrate in a region not covered with the solder resist layer 10. The coating of the organic protective film can protect copper from being oxidized and improve the weldability of the copper bonding pad.
Further, the material of the organic protective film 11 includes any one of NiAu, niPdAu, OSP, and Sn.
From the above description, it can be seen that the semi-additive process method for the FCBGA substrate provided by the embodiment of the present invention at least achieves the following technical effects:
(1) The large copper sheet does not explode, so that the reliability of the substrate is ensured;
(2) The process limitation is reduced, and the design freedom is improved;
(3) The process window is reduced, and the yield is improved;
(4) The warpage of the substrate is reduced.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise. Furthermore, the word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements.
The above-mentioned embodiments, objects, technical solutions and advantages of the present invention are further described in detail, it should be understood that the above-mentioned embodiments are only examples of the present invention, and should not be construed as limiting the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A semi-additive process method of an FCBGA substrate is characterized by comprising the following steps:
the method comprises the following steps of S1, sequentially pressing an ABF layer (3) and a copper foil (4) on the surface of an inner layer circuit (2) of a packaging substrate;
s2, placing the laminated ABF layer (3) in an oven for baking to finish pre-curing;
s3, carrying out vacuum heating and pressurization on the pre-cured ABF layer (3) to completely cure the ABF layer (3);
s4, removing the copper foil (4), and manufacturing an outer layer circuit (9) on the completely solidified ABF layer (3);
and S5, repeating the steps S1 to S4 to form the multilayer circuit packaging substrate.
2. The FCBGA substrate semi-additive process method of claim 1, wherein the step S1 further comprises, before the step of sequentially laminating the ABF layer (3) and the copper foil (4):
and roughening the surface of the inner layer circuit (2).
3. The semi-additive process method for FCBGA substrate of claim 1, wherein in step S2, the step of baking the laminated ABF layer (3) in an oven comprises:
baking at 130 deg.C for 30min, and baking at 180 deg.C for 60min.
4. The semi-additive process of FCBGA substrate of claim 1, wherein in step S3, said vacuum heating and pressurizing the pre-cured ABF layer (3) comprises:
and (2) putting the pre-cured ABF layer (3) under a vacuum condition, and heating and pressurizing under the clamping of a mirror surface isolation steel plate of a laminating machine to completely cure the ABF layer (3).
5. The semi-additive process of claim 4, wherein the temperature after heating is 190 ℃ to 210 ℃, and the pressure after pressurizing is greater than 1MPa.
6. The semi-additive process of FCBGA substrate of claim 1, wherein in step S4, said removing said copper foil (4) and fabricating outer layer traces (9) on the fully cured ABF layer (3) comprises:
step S41, carrying out laser drilling on the completely cured ABF layer (3) and the copper foil (4) to form a blind hole (5) communicated with the inner layer circuit (2) in the ABF layer (3) and the copper foil (4);
s42, removing residual glue residues of laser drilling;
step S43, removing the surface copper foil (4);
step S44, electroless copper plating is carried out in the ABF layer (3) and the blind holes (5) to form a plating seed layer (6);
step S45, forming a pattern electroplating mask (7) on the electroplating seed layer (6) through photoetching;
step S46, forming a circuit pattern (8) in the electroplating seed layer (6) in an electroplating area uncovered by the pattern electroplating mask (7) by electroplating and filling the blind hole (5);
s47, removing the pattern electroplating mask (7);
and S48, removing the electroplating seed layer (6) covered by the pattern electroplating mask (7) to form the outer layer circuit (9).
7. The FCBGA substrate semi-additive process method of claim 6, wherein in step S44, the plating seed layer (6) has a thickness of 0.3 μm to 1 μm.
8. The FCBGA substrate semi-additive process of claim 1, wherein the step S5, after forming the multi-layer circuit package substrate, further comprises:
and manufacturing a solder mask layer (10) on the outermost layer of the multilayer circuit packaging substrate.
9. The FCBGA substrate semi-additive process of claim 8, wherein after the solder mask layer (10) is formed, the method further comprises:
and an organic protective film (11) is coated on the region of the outermost layer of the multilayer circuit packaging substrate, which is not covered by the solder mask layer (10).
10. The FCBGA substrate semi-additive process of claim 9, wherein the organic protective film (11) material comprises any one of NiAu, niPdAu, OSP, sn.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211022518.6A CN115361795A (en) | 2022-08-24 | 2022-08-24 | Semi-additive process method of FCBGA substrate |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202211022518.6A CN115361795A (en) | 2022-08-24 | 2022-08-24 | Semi-additive process method of FCBGA substrate |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117320332A (en) * | 2023-11-29 | 2023-12-29 | 福莱盈电子股份有限公司 | Manufacturing method of HDI inner layer circuit board and HDI circuit board |
| WO2024103773A1 (en) * | 2022-11-15 | 2024-05-23 | 华为技术有限公司 | Wiring carrier board and manufacturing method therefor |
-
2022
- 2022-08-24 CN CN202211022518.6A patent/CN115361795A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024103773A1 (en) * | 2022-11-15 | 2024-05-23 | 华为技术有限公司 | Wiring carrier board and manufacturing method therefor |
| CN117320332A (en) * | 2023-11-29 | 2023-12-29 | 福莱盈电子股份有限公司 | Manufacturing method of HDI inner layer circuit board and HDI circuit board |
| CN117320332B (en) * | 2023-11-29 | 2024-04-16 | 福莱盈电子股份有限公司 | Manufacturing method of HDI inner layer circuit board and HDI circuit board |
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