CN115361795A - Semi-additive process method for FCBGA substrate - Google Patents
Semi-additive process method for FCBGA substrate Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 63
- 239000000758 substrate Substances 0.000 title claims abstract description 59
- 230000008569 process Effects 0.000 title claims abstract description 39
- 239000000654 additive Substances 0.000 title claims abstract description 26
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 46
- 239000011889 copper foil Substances 0.000 claims abstract description 26
- 238000004806 packaging method and process Methods 0.000 claims abstract description 24
- 229910052802 copper Inorganic materials 0.000 claims abstract description 16
- 239000010949 copper Substances 0.000 claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 claims abstract description 16
- 238000010438 heat treatment Methods 0.000 claims abstract description 11
- 238000010030 laminating Methods 0.000 claims abstract description 6
- 238000009713 electroplating Methods 0.000 claims description 35
- 229910000679 solder Inorganic materials 0.000 claims description 13
- 239000000463 material Substances 0.000 claims description 10
- 238000007747 plating Methods 0.000 claims description 10
- 230000001681 protective effect Effects 0.000 claims description 10
- 238000005553 drilling Methods 0.000 claims description 9
- 229910000831 Steel Inorganic materials 0.000 claims description 4
- 239000003292 glue Substances 0.000 claims description 4
- 238000002955 isolation Methods 0.000 claims description 4
- 239000010959 steel Substances 0.000 claims description 4
- 238000003825 pressing Methods 0.000 claims description 3
- 238000007788 roughening Methods 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 claims 1
- 238000013461 design Methods 0.000 abstract description 3
- 238000004880 explosion Methods 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 88
- 238000010586 diagram Methods 0.000 description 8
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 239000002904 solvent Substances 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 239000002893 slag Substances 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
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Abstract
Description
技术领域technical field
本发明涉及封装基板制造技术领域,尤其涉及一种FCBGA基板的半加成工艺方法。The invention relates to the technical field of packaging substrate manufacturing, in particular to a semi-additive process method for FCBGA substrates.
背景技术Background technique
由于高密度布线的要求,FCBGA(Flip Chip Ball Grid Array,倒装芯片球栅阵列)基板制造的主要工艺方法是半加成法。半加成法不仅是铜线路制造技术问题,而且这种技术通常只能使用ABF(Ajinomoto Build-up Film,味之素堆积膜)材料作为绝缘层。换句话说,只有ABF材料才能实现用半加成法制造高密度布线。Due to the requirement of high-density wiring, the main process method of FCBGA (Flip Chip Ball Grid Array, flip-chip ball grid array) substrate manufacturing is the semi-additive method. The semi-additive method is not only a problem of copper circuit manufacturing technology, but this technology can usually only use ABF (Ajinomoto Build-up Film, Ajinomoto build-up film) material as the insulating layer. In other words, only ABF materials can realize high-density wiring by semi-additive method.
由于材料本身性质决定,ABF材料中包含有一定量的溶剂,该溶剂在基板制造过程中如果不通过去除掉,后面布线层累计多层后,积累在基板中的溶剂极易造成基板起泡爆板。在基板布线金属层中不能设置连续的大面积铜皮,需要铜皮的区域必须加工一定间距的气孔,以便ABF层中的气体通过排除,避免爆板。Due to the nature of the material itself, the ABF material contains a certain amount of solvent. If the solvent is not removed during the substrate manufacturing process, after the subsequent wiring layers accumulate multiple layers, the solvent accumulated in the substrate will easily cause the substrate to bubble and explode. . Continuous large-area copper skin cannot be set in the wiring metal layer of the substrate, and air holes at a certain distance must be processed in the area where the copper skin is required, so that the gas in the ABF layer can pass through to avoid explosion.
发明内容Contents of the invention
鉴于上述问题,本发明提供了一种FCBGA基板的半加成工艺方法,避免大铜皮导致爆板。In view of the above problems, the present invention provides a semi-additive process method for FCBGA substrates, which avoids board explosion caused by large copper skins.
为达到上述目的,本发明提供了一种FCBGA基板的半加成工艺方法,包括:步骤S1,在封装基板的内层线路2表面,依次压合ABF层3和铜箔4;步骤S2,将压合后的ABF层3置于烘箱中烘烤,以完成预固化;步骤S3,对预固化的ABF层3进行真空加温加压,使ABF层3完全固化;步骤S4,去除铜箔4,在完全固化的ABF层3上制造外层线路9;步骤S5,重复上述步骤S1~S4,形成多层线路封装基板。In order to achieve the above object, the present invention provides a semi-additive process method for FCBGA substrates, comprising: Step S1, sequentially pressing
进一步地,步骤S1中,依次压合ABF层3和铜箔4之前,还包括:对内层线路2表面进行粗化处理。Further, in step S1 , before sequentially laminating the
进一步地,步骤S2中,将压合后的ABF层3置于烘箱中烘烤,包括:先于130℃下烘烤30min,再于180℃下烘烤60min。Further, in step S2, the laminated
进一步地,步骤S3中,对预固化的ABF层3进行真空加温加压,包括:将预固化的ABF层3置于真空条件,在层压机的镜面隔离钢板夹持下,通过加温和加压,使ABF层3完全固化。Further, in step S3, the
进一步地,加温后的温度为190℃~210℃,加压后的压力大于1MPa。Further, the temperature after heating is 190° C. to 210° C., and the pressure after pressurization is greater than 1 MPa.
进一步地,步骤S4中,去除铜箔4,在完全固化的ABF层3上制造外层线路9,包括:步骤S41,对完全固化的ABF层3和铜箔4进行激光钻孔,使ABF层3和铜箔4中形成与内层线路2连通的盲孔5;步骤S42,去除激光钻孔残留胶渣;步骤S43,去除表面铜箔4;步骤S44,在ABF层3和盲孔5中化学镀铜,形成电镀种子层6;步骤S45,在电镀种子层6上光刻形成图形电镀掩膜7;步骤S46,在电镀种子层6中未被图形电镀掩膜7覆盖的区域电镀形成电路图形8并填充盲孔5;步骤S47,去除图形电镀掩膜7;步骤S48,去除图形电镀掩膜7覆盖的电镀种子层6,形成外层线路9。Further, in step S4, the
进一步地,步骤S44中,电镀种子层6的厚度为0.3μm~1μm。Further, in step S44, the thickness of the electroplating seed layer 6 is 0.3 μm˜1 μm.
进一步地,步骤S5中,形成多层线路封装基板之后,还包括:在多层线路封装基板的最外层制作阻焊层10。Further, in step S5, after forming the multilayer circuit packaging substrate, it further includes: forming a
进一步地,制作阻焊层10之后,还包括:在多层线路封装基板的最外层未被阻焊层10覆盖的区域涂覆有机保护膜11。Further, after making the
进一步地,有机保护膜11材料包括NiAu、NiPdAu、OSP、Sn中的任意一种。Further, the material of the organic
与现有技术相比,本发明提供的FCBGA基板的半加成工艺方法,至少具有以下有益效果:Compared with the prior art, the semi-additive process method of the FCBGA substrate provided by the present invention has at least the following beneficial effects:
(1)大铜皮不爆板,保证基板的可靠性;(1) The large copper skin does not explode, ensuring the reliability of the substrate;
(2)减小工艺限制,提高设计自由度;(2) Reduce process restrictions and increase design freedom;
(3)降低工艺窗口,提高良率;(3) Reduce the process window and improve the yield rate;
(4)降低基板翘曲。(4) Reduce substrate warpage.
附图说明Description of drawings
通过以下参照附图对本发明实施例的描述,本发明的上述以及其他目的、特征和优点将更为清楚,在附图中:Through the following description of the embodiments of the present invention with reference to the accompanying drawings, the above-mentioned and other objects, features and advantages of the present invention will be more clear, in the accompanying drawings:
图1示意性示出了根据本发明实施例的FCBGA基板的半加成工艺方法的操作流程图;Fig. 1 schematically shows the operation flowchart of the semi-additive process method of the FCBGA substrate according to the embodiment of the present invention;
图2示意性示出了根据本发明实施例的FCBGA基板的半加成工艺方法的工艺流程图;Fig. 2 schematically shows the process flow chart of the semi-additive process method of the FCBGA substrate according to the embodiment of the present invention;
图3示意性示出了根据本发明实施例的外层线路的制造过程的操作流程图;Fig. 3 schematically shows the operation flowchart of the manufacturing process of the outer layer circuit according to the embodiment of the present invention;
图4示意性示出了根据本发明实施例的外层线路的制造过程的工艺流程图;FIG. 4 schematically shows a process flow diagram of the manufacturing process of the outer layer circuit according to an embodiment of the present invention;
图5示意性示出了根据本发明实施例的多层线路封装基板的结构图;FIG. 5 schematically shows a structural diagram of a multilayer circuit packaging substrate according to an embodiment of the present invention;
图6示意性示出了根据本发明实施例的阻焊层的结构图;FIG. 6 schematically shows a structural diagram of a solder resist layer according to an embodiment of the present invention;
图7示意性示出了根据本发明实施例的有机保护膜的结构图。Fig. 7 schematically shows a structure diagram of an organic protective film according to an embodiment of the present invention.
【附图标记说明】[Description of Reference Signs]
1-芯板;2-内层线路;3-ABF层;4-铜箔;5-盲孔;6-电镀种子层;7-图形电镀掩膜;8-电路图形;9-外层线路;10-阻焊层;11-有机保护膜。1-core board; 2-inner layer circuit; 3-ABF layer; 4-copper foil; 5-blind hole; 6-electroplating seed layer; 7-graphic plating mask; 8-circuit pattern; 9-outer layer circuit; 10-solder resist layer; 11-organic protective film.
具体实施方式Detailed ways
为使本发明的目的、技术方案和优点更加清楚明白,以下结合具体实施例,并参照附图,对本发明进一步详细说明。显然,所描述的实施例是本发明一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be described in further detail below in conjunction with specific embodiments and with reference to the accompanying drawings. Apparently, the described embodiments are some, but not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.
在此使用的术语仅仅是为了描述具体实施例,而并非意在限制本发明。在此使用的术语“包括”、“包含”等表明了所述特征、步骤、操作和/或部件的存在,但是并不排除存在或添加一个或多个其他特征、步骤、操作或部件。The terminology used herein is for the purpose of describing particular embodiments only, and is not intended to be limiting of the invention. The terms "comprising", "comprising", etc. used herein indicate the presence of stated features, steps, operations and/or components, but do not exclude the presence or addition of one or more other features, steps, operations or components.
在此使用的所有术语(包括技术和科学术语)具有本领域技术人员通常所理解的含义,除非另外定义。应注意,这里使用的术语应解释为具有与本说明书的上下文相一致的含义,而不应以理想化或过于刻板的方式来解释。All terms (including technical and scientific terms) used herein have the meaning commonly understood by one of ordinary skill in the art, unless otherwise defined. It should be noted that the terms used herein should be interpreted to have a meaning consistent with the context of this specification, and not be interpreted in an idealized or overly rigid manner.
图1示意性示出了根据本发明实施例的FCBGA基板的半加成工艺方法的操作流程图。图2示意性示出了根据本发明实施例的FCBGA基板的半加成工艺方法的工艺流程图。FIG. 1 schematically shows an operation flowchart of a semi-additive process method for an FCBGA substrate according to an embodiment of the present invention. FIG. 2 schematically shows a process flow diagram of a semi-additive process method for an FCBGA substrate according to an embodiment of the present invention.
请参阅图1和图2,根据该实施例的FCBGA基板的半加成工艺方法,可以包括步骤S1~步骤S5。Please refer to FIG. 1 and FIG. 2 , the semi-additive process method for the FCBGA substrate according to this embodiment may include steps S1 to S5.
步骤S1,在封装基板的内层线路2表面,依次压合ABF层3和铜箔4。In step S1, the ABF
封装基板的最内层材料为芯板1,在芯板1上制造铜线路,作为内层线路2。该内层线路2的制造方法和结构都与常规印刷线路板相同,例如图2所示,芯板1上开设有通槽,该通槽贯穿芯板1的上下表面。内层线路2填满于该通槽内并且延伸至该芯板1的上下表面。The innermost layer material of the packaging substrate is a core board 1 , on which a copper circuit is manufactured as an inner layer circuit 2 . The manufacturing method and structure of the inner layer circuit 2 are the same as those of a conventional printed circuit board. For example, as shown in FIG. The inner circuit 2 is filled in the slot and extends to the upper and lower surfaces of the core board 1 .
在依次压合ABF层3和铜箔4之前,还需要对内层线路2表面进行粗化处理,以提高内层线路2和ABF层3间的结合力。Before sequentially laminating the
本发明实施例采用ABF层制品为线路层间绝缘材料,可以用于在该材料表面采用半加成工艺制作精密的线路。The embodiment of the present invention adopts the ABF layered product as the circuit interlayer insulating material, which can be used to manufacture precise circuits on the surface of the material by using a semi-additive process.
接着,在内层线路2表面,可以采用真空压膜机在低于常规温度条件下,先压合ABF层3,再在ABF层3表面压合铜箔4。Next, on the surface of the inner circuit 2 , the ABF
步骤S2,将压合后的ABF层3置于烘箱中烘烤,以完成预固化。In step S2, the laminated
本步骤采用低温烘烤,其主要目的在于去除封装基板在加工中吸附的水汽。具体地,将压合后的ABF层3置于烘箱中烘烤,可以先于130℃下烘烤30min,再于180℃下烘烤60min。烘烤后,ABF层3的固化度略有增加。This step adopts low-temperature baking, the main purpose of which is to remove the water vapor absorbed by the packaging substrate during processing. Specifically, the laminated
步骤S3,对预固化的ABF层3进行真空加温加压,使ABF层3完全固化。In step S3, the
本发明实施例中,对预固化的ABF层3进行真空加温加压,可以包括:将预固化的ABF层3置于真空条件,在层压机的镜面隔离钢板夹持下,通过加温和加压,使ABF层3完全固化。In the embodiment of the present invention, vacuum heating and pressurizing the
进一步地,加温后的温度可以为190℃~210℃,加压后的压力可以大于1MPa。Further, the temperature after heating may be 190°C-210°C, and the pressure after pressurization may be greater than 1 MPa.
需要说明的是,常规ABF固化是在ABF表面线路制作之后,在烘箱中以130℃烘烤30分钟,再在190℃~210℃温度烘箱中烘烤1小时。而本发明实施例中,将预固化后的封装基板在层压机中镜面隔离钢板夹持下,在真空室中通过温度和压力作用将ABF完全固化。It should be noted that the conventional ABF curing is to bake in an oven at 130°C for 30 minutes after the ABF surface circuit is made, and then bake in an oven at a temperature of 190°C to 210°C for 1 hour. However, in the embodiment of the present invention, the pre-cured packaging substrate is clamped by the mirror isolation steel plate in the laminator, and the ABF is completely cured in a vacuum chamber under the action of temperature and pressure.
步骤S4,去除铜箔4,在完全固化的ABF层3上制造外层线路9。In step S4 , the
步骤S5,重复上述步骤S1~S4,形成多层线路封装基板。In step S5, the above steps S1-S4 are repeated to form a multilayer circuit packaging substrate.
由此,在完全固化的ABF层3表面制作外层线路9,将制造的外层线路9又作为内层线路2重复进行上述步骤,得到多层线路封装基板。Thus, the
为了具体说明外层线路9的制造过程,图3示意性示出了根据本发明实施例的外层线路的制造过程的操作流程图,图4示意性示出了根据本发明实施例的外层线路的制造过程的工艺流程图。In order to specifically illustrate the manufacturing process of the
请参阅图3和图4,本发明实施例中,在上述步骤S4中,去除铜箔4,在完全固化的ABF层3上制造外层线路9,可以进一步包括步骤S41~步骤S48。Please refer to Fig. 3 and Fig. 4, in the embodiment of the present invention, in the above step S4, the
步骤S41,对完全固化的ABF层3和铜箔4进行激光钻孔,使ABF层3和铜箔4中形成与内层线路2连通的盲孔5。Step S41 , laser drilling is performed on the fully cured
激光钻孔,使ABF层3和铜箔4中形成与内层线路2连通的盲孔5,由此形成层间互连通道。Laser drilling forms
需要说明的是,常规激光钻孔工艺是在经过预固化的ABF表面完成。与常规工艺不同的是,本发明实施例的激光钻孔工艺是在完全固化的ABF层3表面完成。It should be noted that the conventional laser drilling process is completed on the surface of the pre-cured ABF. Different from the conventional process, the laser drilling process in the embodiment of the present invention is completed on the surface of the fully cured
步骤S42,去除激光钻孔残留胶渣。Step S42, removing residual glue residue from laser drilling.
去除盲孔5内部由于激光钻孔携带的残留胶渣。与常规工艺不同,常规工艺是在预固化后的ABF孔表面进行除胶。Residual slag carried by the laser drilling inside the
步骤S43,去除表面铜箔4。Step S43 , removing the
由此,ABF层3和盲孔5裸露在外。Thus, the
步骤S44,在ABF层3和盲孔5中化学镀铜,形成电镀种子层6。Step S44 , electroless copper plating in the
化学镀铜可以为后续的电镀提供导电性。与常规化学镀铜在预固化的ABF表面沉积不同,本发明实施例的化学镀铜是在完全固化的ABF层3的表面沉积,而在ABF层3的非孔区域不做除胶粗化处理。Electroless copper plating provides conductivity for subsequent electroplating. Different from conventional electroless copper plating deposited on the surface of the pre-cured ABF, the electroless copper plating of the embodiment of the present invention is deposited on the surface of the fully cured
进一步地,电镀种子层6的厚度可以为0.3μm~1μm。Further, the thickness of the electroplating seed layer 6 may be 0.3 μm˜1 μm.
步骤S45,在电镀种子层6上光刻形成图形电镀掩膜7。Step S45 , forming a patterned
在电镀种子层6上压干膜,光刻显影形成图形电镀掩膜7。A dry film is pressed on the electroplating seed layer 6, and a
步骤S46,在电镀种子层6中未被图形电镀掩膜7覆盖的区域电镀形成电路图形8并填充盲孔5。Step S46 , forming
本步骤为图形电镀,用于将电路图形8镀出。This step is pattern electroplating, which is used to plate out the
步骤S47,去除图形电镀掩膜7。Step S47, removing the
步骤S48,去除图形电镀掩膜7覆盖的电镀种子层6,形成外层线路9。Step S48 , removing the electroplating seed layer 6 covered by the
通过快速蚀刻,去除被图形电镀掩膜7覆盖的电镀种子层,形成外层线路9。The electroplating seed layer covered by the
接着,图5示意性示出了根据本发明实施例的多层线路封装基板的结构图。Next, FIG. 5 schematically shows a structure diagram of a multilayer circuit packaging substrate according to an embodiment of the present invention.
如图5所示,本发明实施例中,将制造的外层线路9又作为内层线路2,重复进行上述步骤S1~S4,使内层线路2、ABF层3和外层线路9交替叠加,得到多层线路封装基板。As shown in Figure 5, in the embodiment of the present invention, the manufactured
图6示意性示出了根据本发明实施例的阻焊层的结构图。FIG. 6 schematically shows a structure diagram of a solder resist layer according to an embodiment of the present invention.
如图6所示,本发明实施例中,步骤S5中,形成多层线路封装基板之后,还可以包括:在多层线路封装基板的最外层制作阻焊层10。阻焊层作为一种保护层,可以涂覆在封装基板不需焊接的线路或基材上,也可以长期保护所形成的线路图形。As shown in FIG. 6 , in the embodiment of the present invention, in step S5 , after forming the multilayer circuit packaging substrate, it may further include: making a solder resist
图7示意性示出了根据本发明实施例的有机保护膜的结构图。Fig. 7 schematically shows a structure diagram of an organic protective film according to an embodiment of the present invention.
如图7所示,本发明实施例中,制作阻焊层10之后,还可以包括:在多层线路封装基板的最外层未被阻焊层10覆盖的区域涂覆有机保护膜11。有机保护膜的涂覆,既可以保护铜不被氧化,也提高了铜焊盘的可焊性。As shown in FIG. 7 , in the embodiment of the present invention, after making the solder resist
进一步地,有机保护膜11材料包括NiAu、NiPdAu、OSP、Sn中的任意一种。Further, the material of the organic
从以上的描述中,可以看出,本发明实施例提供的FCBGA基板的半加成工艺方法,至少实现了以下技术效果:From the above description, it can be seen that the semi-additive process method of the FCBGA substrate provided by the embodiment of the present invention at least achieves the following technical effects:
(1)大铜皮不爆板,保证基板的可靠性;(1) The large copper skin does not explode, ensuring the reliability of the substrate;
(2)减小工艺限制,提高设计自由度;(2) Reduce process restrictions and increase design freedom;
(3)降低工艺窗口,提高良率;(3) Reduce the process window and improve the yield rate;
(4)降低基板翘曲。(4) Reduce substrate warpage.
此外,术语“第一”、“第二”仅用于描述目的,而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。因此,限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本发明的描述中,“多个”的含义是至少两个,例如两个、三个等,除非另有明确具体的限定。此外,位于元件之前的单词“一”或“一个”不排除存在多个这样的元件。In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be interpreted as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features. Therefore, a feature defined as "first" and "second" may explicitly or implicitly include one or more of these features. In the description of the present invention, "plurality" means at least two, such as two, three, etc., unless otherwise specifically defined. Furthermore, the word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements.
以上所述的具体实施例,对本发明的目的、技术方案和有益效果进行了进一步详细说明,所应理解的是,以上所述仅为本发明的具体实施例而已,并不用于限制本发明,凡在本发明的精神和原则之内,所做的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。The specific embodiments described above have further described the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above descriptions are only specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.
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Cited By (3)
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CN117320332A (en) * | 2023-11-29 | 2023-12-29 | 福莱盈电子股份有限公司 | Manufacturing method of HDI inner layer circuit board and HDI circuit board |
WO2024103773A1 (en) * | 2022-11-15 | 2024-05-23 | 华为技术有限公司 | Wiring carrier board and manufacturing method therefor |
CN118899228A (en) * | 2024-10-09 | 2024-11-05 | 江门市和美精艺电子有限公司 | NBF-based FCBGA substrate manufacturing method and FCBGA substrate |
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
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WO2024103773A1 (en) * | 2022-11-15 | 2024-05-23 | 华为技术有限公司 | Wiring carrier board and manufacturing method therefor |
CN117320332A (en) * | 2023-11-29 | 2023-12-29 | 福莱盈电子股份有限公司 | Manufacturing method of HDI inner layer circuit board and HDI circuit board |
CN117320332B (en) * | 2023-11-29 | 2024-04-16 | 福莱盈电子股份有限公司 | Manufacturing method of HDI inner layer circuit board and HDI circuit board |
CN118899228A (en) * | 2024-10-09 | 2024-11-05 | 江门市和美精艺电子有限公司 | NBF-based FCBGA substrate manufacturing method and FCBGA substrate |
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