CN115360139A - Method for reducing contact resistance by etching high-depth-to-width-ratio connecting hole - Google Patents

Method for reducing contact resistance by etching high-depth-to-width-ratio connecting hole Download PDF

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Publication number
CN115360139A
CN115360139A CN202211031994.4A CN202211031994A CN115360139A CN 115360139 A CN115360139 A CN 115360139A CN 202211031994 A CN202211031994 A CN 202211031994A CN 115360139 A CN115360139 A CN 115360139A
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CN
China
Prior art keywords
etching
connecting hole
contact resistance
silicon substrate
aspect ratio
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Pending
Application number
CN202211031994.4A
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Chinese (zh)
Inventor
高宏
陈嘉彬
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Priority to CN202211031994.4A priority Critical patent/CN115360139A/en
Publication of CN115360139A publication Critical patent/CN115360139A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365

Abstract

The invention provides a method for reducing contact resistance by etching a connecting hole with a high depth-to-width ratio, which comprises the steps of providing a silicon substrate, and forming an oxide layer on the silicon substrate; etching the oxide layer to form a connecting hole with a high depth-to-width ratio, and stopping etching when the etching is nearly finished; introducing fluorocarbon and bombarding with inert gas to continuously etch the connecting hole until the oxide layer at the bottom of the connecting hole is completely removed; forming a titanium layer and a titanium nitride layer at the bottom of the connecting hole in sequence; and filling tungsten in the connecting hole. According to the invention, when the high aspect ratio connecting hole is about to finish oxide film etching, a step of etching step of fluorocarbon with high fluorocarbon ratio and low argon bombardment is added, so that the side wall appearance of the connecting hole is inclined, the coverage rate of a bottom step is improved, and the contact resistance is improved.

Description

Method for reducing contact resistance by etching high-depth-to-width-ratio connecting hole
Technical Field
The invention relates to the technical field of semiconductors, in particular to a method for reducing contact resistance by etching a connecting hole with a high depth-to-width ratio.
Background
In an 8-inch wafer factory, the phenomenon of poor coverage of a bottom step (namely the ratio of the total thickness of the titanium nitride and the titanium actually formed in the connecting hole to the total thickness of the titanium nitride and the titanium required to be achieved) and large contact resistance often occur in a special structure of the connecting hole with a high aspect ratio; in order to improve the defect, the bottom appearance of the connecting hole needs to be changed, so that the step coverage rate is high, and the larger contact resistance is improved.
Therefore, a new method is needed to solve the above problems.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a method for etching a high aspect ratio connection hole to reduce contact resistance, which is used to solve the problem of the prior art that the contact resistance is too large due to low coverage of the step at the bottom of the high aspect ratio connection hole.
In order to achieve the above and other related objects, the present invention provides a method for etching a high aspect ratio connection hole to reduce contact resistance, which at least comprises:
providing a silicon substrate, and forming an oxide layer on the silicon substrate;
etching the oxide layer to form a connecting hole with a high depth-to-width ratio, and stopping etching when the etching is nearly finished;
step three, introducing fluorocarbon and bombarding with inert gas to continuously etch the connecting hole until the oxide layer at the bottom of the connecting hole is completely removed;
step four, forming a titanium layer and a titanium nitride layer at the bottom of the connecting hole in sequence;
and step five, filling tungsten into the connecting hole.
Preferably, when the etching in the second step is nearly completed, the bottom of the connecting hole formed by etching is close to the silicon substrate, but the oxide layer on the silicon substrate is not yet completely etched.
Preferably, after the etching in the third step is completed, the width of the top opening of the connecting hole is greater than the width of the bottom of the connecting hole, and the included angle between the side wall of the connecting hole and the upper surface of the silicon substrate is 83.09 °.
Preferably, the fluorocarbon in step three is C5F8; the inert gas is argon.
Preferably, the flow rate of the C5F8 in the third step is 8-30sccm; the flow rate of the argon is 200-400sccm.
Preferably, the etching conditions in step three include: the etched radio frequency is 1200-1800W; the pressure was 40-55Torr.
Preferably, the titanium layer and the titanium nitride layer are formed at the bottom of the connection hole in the fourth step by sputtering.
Preferably, the step coverage rate of the titanium layer and the titanium nitride layer formed at the bottom of the connection hole in the fourth step is 61%.
As described above, the method for reducing contact resistance by etching a high aspect ratio connection hole of the present invention has the following beneficial effects: according to the invention, when the high-aspect-ratio connecting hole is etched with an oxide film, a step of etching with fluorocarbon with high fluorocarbon ratio and low argon bombardment is added, so that the side wall appearance of the connecting hole is inclined, the coverage rate of a bottom step is increased, and the contact resistance is improved.
Drawings
FIG. 1 is a schematic cross-sectional view illustrating a connection hole of the present invention before the connection hole is completely formed;
FIG. 2 is a schematic cross-sectional view of a connecting hole formed after etching is completed according to the present invention;
FIG. 3 is a flow chart of a method for etching a high aspect ratio contact hole to reduce contact resistance in accordance with the present invention.
Detailed Description
The following embodiments of the present invention are provided by way of specific examples, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 3. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
The invention provides a method for reducing contact resistance by etching a connecting hole with a high aspect ratio, as shown in fig. 3, fig. 3 is a flow chart of the method for reducing contact resistance by etching the connecting hole with the high aspect ratio, and the method at least comprises the following steps:
providing a silicon substrate, and forming an oxide layer on the silicon substrate; as shown in fig. 1, fig. 1 is a schematic cross-sectional view of the connection hole of the present invention before the connection hole is completely formed. In the first step, the silicon substrate 01 is provided, and the oxide layer 02 is formed on the silicon substrate 01.
Etching the oxide layer to form a connecting hole with a high depth-to-width ratio, and stopping etching when the etching is nearly finished;
further, when the etching is nearly completed in the second step of this embodiment, the bottom of the connection hole formed by etching is close to the silicon substrate, but the oxide layer on the silicon substrate is not yet completely etched.
As shown in fig. 1, in this step, two pairs of the oxide layers 02 are etched to form a connection hole with a high aspect ratio, and the etching is stopped when the etching is nearly completed; at this time, an unfinished connection hole 03 is formed, and in this embodiment, when the etching is nearly finished, it means that the bottom of the connection hole formed by etching is close to the silicon substrate, but the oxide layer on the silicon substrate is not yet completely etched. As shown in fig. 1, at this time, the oxide layer 02 at the bottom of the connection hole is not completely etched, and the silicon substrate at the bottom of the connection hole is not exposed. The included angle between the side wall of the unfinished connecting hole formed in the second step and the upper surface of the silicon substrate is 88.37 degrees. The width of the upper end opening of the unfinished connecting hole formed in the second step is larger than that of the bottom of the unfinished connecting hole.
Step three, introducing fluorocarbon and bombarding with inert gas to continuously etch the connecting hole until the oxide layer at the bottom of the connecting hole is completely removed; as shown in fig. 2, fig. 2 is a schematic cross-sectional structure diagram of a connection hole formed after etching is completed in the present invention.
Further, after the etching is completed in the third step of this embodiment, the width of the top opening of the formed connection hole is greater than the width of the bottom of the connection hole, and the included angle between the side wall of the connection hole and the upper surface of the silicon substrate is 83.09 ° (the included angle in fig. 2).
Further, the fluorocarbon compound in step three of this example is C5F8; the inert gas is argon.
Further, in the third step of the present embodiment, the flow rate of C5F8 is 8-30sccm; the flow rate of the argon gas is 200-400sccm.
Further, the etching conditions in the third step of this embodiment include: the etched radio frequency is 1200-1800W; the pressure was 40-55Torr.
Step four, forming a titanium layer and a titanium nitride layer at the bottom of the connecting hole in sequence; the titanium nitride layer is located on the upper surface of the titanium layer.
Further, in the fourth step of this embodiment, a titanium layer and a titanium nitride layer are formed at the bottom of the connection hole by a sputtering method.
Furthermore, in the fourth step of this embodiment, the step coverage of the titanium layer and the titanium nitride layer formed at the bottom of the connection hole is 61%. That is, the ratio of the total thickness of the actually formed titanium layer and titanium nitride layer to the total thickness of the titanium layer and titanium nitride layer to be formed.
And step five, filling tungsten into the connecting hole.
Compared with the connecting hole formed by the traditional method, the method provided by the invention has the advantages that the side wall of the connecting hole is more inclined, and the step coverage rate is higher, while the step coverage rate in the traditional method is 25%, and the step coverage rate in the invention is 61%. Therefore, the appearance of the connecting hole can be inclined, the coverage rate of the bottom step is improved, and the contact resistance is improved.
In summary, the invention increases a step of fluorocarbon with high fluorocarbon ratio and low argon bombardment etching when the high aspect ratio connecting hole is about to finish oxide film etching, so that the side wall appearance of the connecting hole is inclined, the coverage rate of the bottom step is improved, and the contact resistance is improved. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (8)

1. A method for reducing contact resistance by etching a high-aspect-ratio connecting hole is characterized by at least comprising the following steps:
providing a silicon substrate, and forming an oxide layer on the silicon substrate;
etching the oxide layer to form a connecting hole with a high depth-to-width ratio, and stopping etching when the etching is nearly finished;
step three, introducing fluorocarbon and bombarding with inert gas to continuously etch the connecting hole until the oxide layer at the bottom of the connecting hole is completely removed;
step four, forming a titanium layer and a titanium nitride layer at the bottom of the connecting hole in sequence;
and step five, filling tungsten into the connecting hole.
2. The method for etching a high aspect ratio via hole to reduce contact resistance as recited in claim 1, wherein: and step two, when the etching is nearly finished, the bottom of the connecting hole formed by etching is close to the silicon substrate, but the oxide layer on the silicon substrate is not completely etched.
3. The method for etching a high aspect ratio connection hole to reduce contact resistance according to claim 1, wherein: and after the etching in the third step is finished, the width of the top opening of the connecting hole is larger than the width of the bottom of the connecting hole, and the included angle between the side wall of the connecting hole and the upper surface of the silicon substrate is 83.09 degrees.
4. The method for etching a high aspect ratio connection hole to reduce contact resistance according to claim 1, wherein: the fluorocarbon in step three is C5F8; the inert gas is argon.
5. The method for etching a high aspect ratio connection hole to reduce contact resistance according to claim 4, wherein: the flow rate of C5F8 in the third step is 8-30sccm; the flow rate of the argon gas is 200-400sccm.
6. The method for etching a high aspect ratio connection hole to reduce contact resistance according to claim 5, wherein: the etching conditions in the third step comprise: the etched radio frequency is 1200-1800W; the pressure was 40-55Torr.
7. The method for etching a high aspect ratio via hole to reduce contact resistance as recited in claim 1, wherein: and step four, forming a titanium layer and a titanium nitride layer at the bottom of the connecting hole by a sputtering method.
8. The method for etching a high aspect ratio connection hole to reduce contact resistance according to claim 1, wherein: and step four, forming a titanium layer and a titanium nitride layer at the bottom of the connecting hole, wherein the step coverage rate is 61%.
CN202211031994.4A 2022-08-26 2022-08-26 Method for reducing contact resistance by etching high-depth-to-width-ratio connecting hole Pending CN115360139A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202211031994.4A CN115360139A (en) 2022-08-26 2022-08-26 Method for reducing contact resistance by etching high-depth-to-width-ratio connecting hole

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202211031994.4A CN115360139A (en) 2022-08-26 2022-08-26 Method for reducing contact resistance by etching high-depth-to-width-ratio connecting hole

Publications (1)

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CN115360139A true CN115360139A (en) 2022-11-18

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