CN115347456A - Preparation method of single-chip-stripped combined reflector type long wavelength VCSEL - Google Patents

Preparation method of single-chip-stripped combined reflector type long wavelength VCSEL Download PDF

Info

Publication number
CN115347456A
CN115347456A CN202211008408.4A CN202211008408A CN115347456A CN 115347456 A CN115347456 A CN 115347456A CN 202211008408 A CN202211008408 A CN 202211008408A CN 115347456 A CN115347456 A CN 115347456A
Authority
CN
China
Prior art keywords
vcsel
layer
chip
inp
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202211008408.4A
Other languages
Chinese (zh)
Inventor
鄢静舟
季晓明
薛婷
柯程
杨奕
吴建忠
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujian Huixin Laser Technology Co ltd
Original Assignee
Fujian Huixin Laser Technology Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujian Huixin Laser Technology Co ltd filed Critical Fujian Huixin Laser Technology Co ltd
Priority to CN202211008408.4A priority Critical patent/CN115347456A/en
Publication of CN115347456A publication Critical patent/CN115347456A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
    • H01S5/18—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities
    • H01S5/183—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
    • H01S5/18361—Structure of the reflectors, e.g. hybrid mirrors
    • H01S5/18369—Structure of the reflectors, e.g. hybrid mirrors based on dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/0206—Substrates, e.g. growth, shape, material, removal or bonding
    • H01S5/0215—Bonding to the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/0206—Substrates, e.g. growth, shape, material, removal or bonding
    • H01S5/0217—Removal of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
    • H01S5/18—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities
    • H01S5/183—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
    • H01S5/18386—Details of the emission surface for influencing the near- or far-field, e.g. a grating on the surface

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
  • Semiconductor Lasers (AREA)

Abstract

The invention discloses a preparation method of a single chip peeled combined reflector type long wavelength VCSEL (vertical cavity surface emitting laser), which relates to the technical field of semiconductor photoelectron and comprises the following steps: (1) growing an epitaxial layer on an InP substrate; (2) Manufacturing a first reflector on the surface of the epitaxial layer, and etching the epitaxial layer into a plurality of single independent VCSEL chips; (3) Bonding a final substrate on the surface of the first reflector, and selectively etching the sacrificial layer of each VCSEL chip so as to strip the VCSEL chip from the InP substrate; and (4) manufacturing a second reflector. The preparation method can greatly reduce the difficulty of substrate stripping and the processing time, realizes the recycling of InP substrates required by long-wavelength VCSE, greatly reduces the production cost of enterprises, and provides necessary technical support for arranging the combined reflectors at the upper end and the lower end of the VCSEL.

Description

Preparation method of single-chip-stripped combined reflector type long-wavelength VCSEL
Technical Field
The invention relates to the technical field of semiconductor photoelectron, in particular to a preparation method of a single-chip-stripped combined reflector type long-wavelength VCSEL.
Background
With the rapid development of the data communication era, vertical Cavity Surface Emitting Laser (VCSEL) chips are widely used in the optical communication fields, such as optical interconnection, optical sensing, optical storage, and application scenarios such as data center short-distance communication, 5G base station, HDMI ultra high definition video transmission, etc., due to their excellent characteristics, such as small chip volume, circular light spot output, low working threshold, high coupling efficiency, and convenient integration. The VCSEL has good economy, practicability and reliability, and brings great convenience for information exchange in various industries.
The structure of the existing VCSEL usually adopts a "sandwich" design, mainly including a top mirror, a bottom mirror, a conductive confinement region, an active region, a semiconductor substrate, etc., wherein a laser beam is emitted along a direction perpendicular to the substrate, the top mirror and the bottom mirror are semiconductor DBRs with a multilayer structure, and both form a resonant cavity of the laser with the active region, so that the reflectivity index determines the performance of the laser, such as lasing wavelength, gain, etc., of the laser. Long wavelength VCSELs, which are commonly referred to as VCSELs having a lasing wavelength between 1200-1900nm, have a worldwide technical difficulty in achieving long wavelengths in that the band VCSEL is based on an InP substrate, there is no suitable compound semiconductor material with large refractive index difference and lattice constant matching to design the DBR mirrors necessary for the VCSEL, and there is no material similar to AlAs for GaAs substrate systems to form an oxide aperture to improve the optical and electrical properties of the VCSEL. Taking the long wavelength 1550nm VCSEL grown on the InP substrate as an example, to achieve 99% reflectivity, the top semiconductor DBR needs to be 8 μm thick. However, the larger the thickness of the semiconductor DBR is, the larger the light absorption loss is, which easily causes problems of high threshold current and large insertion loss, and also causes a chip to have a large series resistance, resulting in poor heat dissipation of the chip. And the number of the films of the semiconductor DBR is large, the requirements on the thickness and the components of the films are strict, the manufacturing difficulty of the device is high, and the production is difficult.
In addition, the price of 3-inch InP substrates on the market today is $ 600 and $ 800-900 for 4-inch InP substrates, which is seen to be very expensive, further limiting the development and popularity of long wavelength VCSELs.
Disclosure of Invention
The invention provides a preparation method of a single-chip-stripped combined reflector type long-wavelength VCSEL (vertical cavity surface emitting laser), and mainly aims to solve the problems in the prior art.
The invention adopts the following technical scheme:
a method for preparing a single chip peeled combined reflector type long wavelength VCSEL comprises the following steps:
(1) Growing an epitaxial layer on the InP substrate, wherein the epitaxial layer comprises an InP first buffer layer, a sacrificial layer, an InP second buffer layer, a first N-type doped DBR (distributed Bragg reflector), an active region, a tunneling junction layer and a second N-type doped DBR; the tunneling junction layer is provided with a plurality of buried tunneling junctions which are arranged at intervals;
(2) Preparing a plurality of first reflectors which correspond to the buried tunneling junctions on the surface of the epitaxial layer, and etching the epitaxial layer into a single independent VCSEL chip; the first reflector is a grating layer or a medium layer DBR;
(3) Bonding a one-piece final substrate on the surface of the first reflector of each VCSEL chip, and selectively etching the sacrificial layer of each VCSEL chip by using an HF solution so as to strip the InP substrate from the bottom of each VCSEL chip;
(4) Manufacturing a second reflector on the surface of the InP second buffer layer of each VCSEL chip; the second reflecting mirror is a grating layer or a medium layer DBR.
Further, the step (3) comprises the following sub-steps:
(3.1) bonding a one-piece extensible adhesive tape on the first mirror surface of each VCSEL chip;
(3.2) selectively etching the sacrificial layer of each VCSEL chip by using an HF solution so as to strip the InP substrate from the bottom of each VCSEL chip;
(3.3) transferring each VCSEL chip onto a one-piece temporary substrate by means of a malleable tape and removing the malleable tape;
(3.4) transfer-bonding each VCSEL chip onto the final substrate through the temporary substrate, and removing the temporary substrate.
Further, in step (3.3), the stretchable adhesive tape is first spread by using a spreading device so that the position of each VCSEL chip corresponds to a predetermined chip position, then the VCSEL chips are transferred onto the temporary substrate, and finally the stretchable adhesive tape is removed.
Further, the dielectric layer DBR is made of SiO 2 /Si 3 N 4 The periodic stack is composed of mirrors with period number of 4-8 and thickness of 1800-3750nm.
Furthermore, the high refractive index material of the grating layer is SiO 2 Or Si 3 N 4 The low refractive index material is air or an oxide.
Furthermore, the grating period of the grating layer is 550nm < lambda < 800nm, the filling coefficient is 350nm < eta < 500nm, and the grating depth is 350nm < tg < 500nm.
Furthermore, the sacrificial layer is of an AlAs/InAlAs/AlAs/InAlAs/AlAs superlattice structure, the thickness of the AlAs is 1.5-2.1nm, and the thickness of the InAlAs is 1nm.
Further, the first N-type doped DBR and the second N-type doped DBR are mirrors formed by InAlGaAs/InP or InGaAsP/InP periodic stacking; the number of cycles of the first N-type doping DBR and the number of cycles of the second N-type doping DBR are both 5-20, and the thickness is 1000-5000nm.
Further, the final substrate is a silicon wafer with a thickness of 300-700 μm.
Compared with the prior art, the invention has the beneficial effects that:
1. the invention is based on the substrate stripping technology, firstly, the epitaxial layer is etched into a single VCSEL chip, and then the substrate stripping transfer is realized by adopting the lattice-matched sacrificial layer, so that the stripping difficulty and the processing time are greatly reduced, the required InP substrate for the long-wavelength VCSEL is recycled, the production cost of enterprises is greatly reduced, and necessary technical support is provided for arranging the combined reflectors at the upper end and the lower end of the VCSEL.
2. The invention adopts the design concept of the combined reflector, and utilizes the combined reflector of the dielectric layer DBR/grating layer + the first N-type doped DBR and the dielectric layer DBR/grating layer + the second N-type doped DBR to replace the single DBR reflector of InP/InAlGaAs with a large number of film layers and a large thickness in the traditional VCSEL, thereby solving the worldwide problem that the long-wavelength VCSEL has no proper semiconductor DBR, effectively reducing the optical and electrical loss of the VCSEL with long wavelength, reducing the series resistance, improving the electro-optical conversion efficiency of the VCSEL, greatly improving the heat conduction capability and high-temperature working performance of the VCSEL chip, reducing the manufacturing difficulty of devices, and meeting the characteristic requirements of the fields of laser radar, data communication and the like on the VCSEL with long wavelength.
Drawings
FIG. 1 is a schematic diagram of a single VCSEL structure according to the present invention.
Fig. 2 is a schematic view of the layered structure of the active region of the present invention.
Fig. 3 is a schematic structural diagram of a grating layer according to the present invention.
FIG. 4 is a schematic view of the epitaxial structure of a VCSEL before substrate stripping in the present invention.
FIG. 5 is a first process flow diagram of VCSEL fabrication according to the present invention.
FIG. 6 is a second schematic flow chart of VCSEL manufacturing process according to the present invention.
In the figure:
10. an InP substrate; 11. An InP first buffer layer;
12. a sacrificial layer; 13. An InP second buffer layer;
14. a first N-type doped DBR; 15. An active region;
16. a second N-type doped DBR; 17. A medium layer DBR;
18. burying a tunneling junction; 19. A grating layer;
113. a final substrate; 151. A confinement layer;
152. a waveguide layer; 153. A quantum well layer;
154. a symmetric waveguide layer; 155. A symmetric confinement layer.
Detailed Description
The following describes embodiments of the present invention with reference to the drawings. Numerous details are set forth below in order to provide a thorough understanding of the present invention, but it will be apparent to those skilled in the art that the present invention may be practiced without these details.
As shown in fig. 1, a combined mirror VCSEL includes a final substrate 113 and an epitaxial layer formed by stripping an InP substrate by a substrate lift-off technique, wherein the epitaxial layer is fixedly mounted on the final substrate 113, and the epitaxial layer sequentially includes, from bottom to top, a first mirror, a second N-doped DBR16, a buried tunneling junction 18, an active region 15, a first N-doped DBR14, an InP second buffer layer 13, and a second mirror. Wherein, the first reflector and the second reflector can be any one of a dielectric layer DBR and a grating layer. The first mirror in this embodiment is preferably a dielectric layer DBR17 and the second mirror is preferably a grating layer 19.
As shown in fig. 1 and fig. 3, the materials of the layers of the combined mirror VCSEL in this embodiment are designed as follows:
the final substrate 113 is made of silicon wafer with good heat conductivity or other materials or substrates with good heat dissipation, and has a thickness of 300-700 μm. Finally, the substrate 113 not only facilitates heat dissipation of the chip, but also plays a role in physical support, and can effectively replace an InP substrate.
The DBR17 of the medium layer is made of SiO 2 /Si 3 N 4 The periodic stack is composed of mirrors with period number of 4-8 and thickness of 1800-3750nm.
The first N-type doped DBR14 and the second N-type doped DBR16 are mirrors comprised of inalgas/InP or InGaAsP/InP periodic stacks. The first N-doped DBR14 and the second N-doped DBR16 of the present embodiment provide sufficient physical support and provide partial reflectivity, thereby ensuring reliable and stable mirror assembly of the epitaxial layers. The first N-type doped DBR14 and the second N-type doped DBR16 have the cycle number of 5-20 and the thickness of 1000-5000nm. When the reflectivity of the traditional 1550nm VCSEL InP/InAlGaAs DBR reflector is 99%, the thickness of the semiconductor DBR reaches 8 mu m; the first N-type semiconductor doping DBR (5-10 cycles) and the dielectric layer DBR reflecting unit are adopted to achieve the same reflectivity, and the thickness of the semiconductor DBR is only 1-2.5 mu m; the same reflectivity is achieved by doping the DBR with a second N-type semiconductor (5-20 cycles) + HCG reflector element, the semiconductor DBR thickness being only 1-5 μm. Therefore, the thickness of the DBR reflector can be effectively reduced by adopting the combined reflector of the dielectric layer DBR17+ the first N-type doped DBR14 and the grating layer 19+ the second N-type doped DBR16, so that the problems in the prior art are effectively solved.
The thickness of the InP second buffer layer 13 is 500-1000nm, the doping atom is Si, and the doping concentration is more than 10 18 cm -3 . Since the VCSEL provided in this embodiment needs to be fabricated by a substrate lift-off process, the InP second buffer layer 13 may be disposed to ensure the crystal quality.
The buried tunnel junction 18 includes a P-type heavily doped layer and an N-type heavily doped layer from bottom to top. The P-type heavily doped layer material can be, but is not limited to, inGaAsP, inGaAlAs, alInAs, inP, and the N-type heavily doped layer material can be, but is not limited to, gaInAs, inP, inGaAsP, inGaAlAs, alInAs; the thickness range of the P-type heavily doped layer is 8-50nm, and the thickness range of the N-type heavily doped layer is 10-50nm; the doping atoms of the P-type heavily doped layer can Be but are not limited to C, mg, zn and Be, and the doping atoms of the N-type heavily doped layer can Be but are not limited to Te, se, si and S; the doping concentration of the P-type heavily doped layer and the N-type heavily doped layer is 10 19 -10 20 cm -3 An order of magnitude; the buried tunnel junction 18 has an aperture in the range of 4-50 μm.
The grating layer 19 is preferably a high index contrast subwavelength grating of the type formed by subwavelength stripes of a high index material surrounded by a low index medium, wherein the high index material is SiO 2 Or Si 3 N 4 The low refractive index material can be air or oxide, and the grating period is 550nm<∧<800nm, fill factor 350nm<η<500nm, grating depth 350nm<tg<500nm。
The relevant design parameters of the epitaxial structure of each VCSEL are referenced in table 1.
TABLE 1 epitaxial Structure parameter Table for VCSELs
Figure BDA0003809908090000071
As shown in fig. 2, in the present embodiment, the active region 15 includes, from bottom to top, a confinement layer 151, a waveguide layer 152, a quantum well layer 153, a symmetric waveguide layer 154, and a symmetric confinement layer 155. Well layer/barrier layer of the quantum well layer 153 is In x Ga 1-x As y P 1-y /In x Ga 1- x AsyP 1-y Or AlInGaAs of different Ga/Al ratios.
The design parameters of the active region are referred to in table 2.
TABLE 2 Parametric table of active regions
Figure BDA0003809908090000072
In this embodiment, the above-mentioned combined reflector is prepared by a substrate lift-off technique, and in order to more clearly illustrate the preparation method, the VCSEL epitaxial structure before lift-off is described in detail below:
as shown in fig. 4, the epitaxial structure of the VCSEL before lift-off includes, from bottom to top, an InP substrate 10, an InP first buffer layer 11, a sacrificial layer 12, an InP second buffer layer 13, a first N-doped DBR14, an active region 15, a buried tunnel junction 18, a second N-doped DBR16, and a dielectric layer DBR 17.
The thickness of the InP substrate 10 is 300-700 μm, and the thickness of the epitaxial structure above the InP substrate 10 is 6-20 μm. The cyclic utilization of the InP substrate 10 can be realized through the substrate stripping process, the manufacturing cost of enterprises is greatly reduced, and necessary technical support is provided for the preparation of the VCSEL with the combined reflectors at two ends, namely the upper end and the lower end of the VCSEL can adopt the combined reflectors through the substrate stripping.
The sacrificial layer 12 is of a superlattice structure of AlAs/InAlAs/AlAs/InAlAs/AlAs, wherein the thickness of the AlAs is 1.5-2.1nm, and the thickness of the InAlAs is 1nm. The choice and thickness of the sacrificial layer composition is critical in the ELO process, with thicker layers leading to slower etch rates, and too thin layers (typically less than 5 nm) leading to a sudden etch stop, and studies have shown that reasonable thickness of the sacrificial layer should be controlled in the range of 5-10 nm. In the prior art, the ELO process based on the InP substrate usually uses AlAs as the sacrificial layer, but the lattice mismatch between AlAs material and InP material is as high as 3.6%. In the InP substrate peeling test using AlAs as a sacrificial layer, which has been carried out, the use of AlAs having a thickness exceeding 5nm causes the sacrificial layer to relax, causing crystal defects, thereby affecting the device performance. In order to overcome the thickness limitation of the AlAs layer, the present embodiment uses AlAs/InAlAs/AlAs superlattice instead of AlAs as the sacrificial layer, although there is a high degree of lattice mismatch between AlAs and InP, the AlAs/InAlAs/AlAs/InAlAs superlattice structure can be regarded as a single layer, exhibiting an effective average composition constituting the superlattice, and a thicker sacrificial layer can be deposited, and maintaining good material crystal quality. Therefore, the adoption of the AlAs/InAlAs/AlAs/InAlAs/AlAs superlattice structure can realize the stripping and recycling of the InP substrate while ensuring the quality of the thin film of the device, thereby reducing the production cost of enterprises.
The following description describes a method for fabricating the combined mirror VCSEL, which includes the following steps:
(1) An epitaxial layer is grown on an InP substrate 10, and the epitaxial layer includes an InP first buffer layer 11, a sacrificial layer 12, an InP second buffer layer 13, a first N-doped DBR14, an active region 15, a tunnel junction layer having a plurality of buried tunnel junctions 18 spaced apart from each other, and a second N-doped DBR 16. Specifically, firstly, depositing an InP first buffer layer 11, a sacrificial layer 12, an InP second buffer layer 13, a first N-type doped DBR14, an active region 15, and a tunnel junction layer on an InP substrate 10 in sequence by using an MOCVD process; the aperture of the VCSEL is then defined by masking and etching to form the mesa of the tunnel junction layer, then the tunnel junction is buried by second epitaxy and a second N-doped DBR16 is grown, as shown in fig. 4 and 5 (a).
(2) A plurality of first reflectors corresponding to the buried tunnel junctions 18 are prepared on the surface of the epitaxial layer, and the epitaxial layer is etched into a single independent VCSEL chip. The first reflector is preferably a dielectric layer DBR17, and the manufacturing method comprises the following steps: firstly, a dielectric layer DBR17 is deposited on the surface of the second N-type doped DBR16 by adopting a PECVD process, as shown in figure 5 (b); photolithography and chemical solution etching are then used to etch the epitaxial layer into individual VCSEL chips, as shown in fig. 5 (c).
(3) Bonding a one-piece final substrate 113 on the surface of the dielectric layer DBR17 of each VCSEL chip, and selectively etching the sacrificial layer 12 of each VCSEL chip by using an HF solution, thereby stripping the InP substrate 10 from the bottom of each VCSEL chip; the method specifically comprises the following substeps:
(3.1) adhering a piece of extensible adhesive tape on the surface of the dielectric layer DBR17 of each VCSEL chip, as shown in FIG. 5 (d);
(3.2) selectively etching the sacrificial layer 12 of each VCSEL chip by using an HF solution, thereby stripping the InP substrate 10 from the bottom of each VCSEL chip; specifically, the HF solution selectively etches each VCSEL chip to separate the sacrificial layer from the InP substrate 10 of the VCSEL chip, thereby peeling the entire epitaxial layer off the InP substrate 10, as shown in fig. 5 (e) and (f).
(3.3) transferring each VCSEL chip onto a one-piece temporary substrate by means of a malleable tape, and removing the malleable tape, as shown in fig. 6 (a) and (b). The method comprises the steps of firstly, adopting a film expanding device to expand the extensible adhesive tape so as to enable the position of each VCSEL chip to accord with the preset chip position, then transferring the VCSEL chip to a temporary substrate, and finally removing the extensible adhesive tape. In a specific implementation process, the extensible adhesive tape can be subjected to integral film expansion in a whole film extending mode so as to adjust the distance between the VCSEL chips, and the extensible adhesive tape can be subjected to partial film expansion in a partial extending mode so as to adjust the distance between two adjacent VCSEL chips in the corresponding positions.
(3.4) each VCSEL chip is transferred onto the final substrate 113 through the temporary substrate, and the temporary substrate is removed, as shown in fig. 6 (c) and (d). The temporary substrate provides sufficient physical support for the adhesion of the epitaxial layers to the final substrate. In practice, the temporary substrate or the final substrate may be mounted on the epitaxial layer by direct bonding or adhesive bonding, but its adhesion to the epitaxial layer should be relatively weak in order to facilitate removal of the temporary substrate.
(4) A second reflector is fabricated on the surface of the InP second buffer layer 13 of each VCSEL chip, and in this embodiment, the second reflector is preferably a grating layer, and the fabrication method is as follows: firstly, a PECVD process is adopted to deposit a plurality of SiO arranged at intervals on the surface of the InP second buffer layer 13 2 Layer or Si 3 N 4 A layer; the grating layer 19 is then formed by photolithography and chemical solution etching or partial oxidation, as shown in fig. 6 (e). And (4) cutting and separating the single independent VCSEL obtained in the step (4) to obtain the combined mirror type VCSEL shown in FIG. 1.
The above description is only an embodiment of the present invention, but the design concept of the present invention is not limited thereto. All insubstantial changes made by the design concepts of the present invention shall fall within the scope of the invention.

Claims (9)

1. A method for preparing a single chip peeled combined reflector type long wavelength VCSEL is characterized in that: the method comprises the following steps:
(1) Growing an epitaxial layer on the InP substrate, wherein the epitaxial layer comprises an InP first buffer layer, a sacrificial layer, an InP second buffer layer, a first N-type doped DBR, an active region, a tunneling junction layer and a second N-type doped DBR; the tunneling junction layer is provided with a plurality of buried tunneling junctions which are arranged at intervals;
(2) Preparing a plurality of first reflectors which correspond to the buried tunneling junctions on the surface of the epitaxial layer, and etching the epitaxial layer into a single independent VCSEL chip; the first reflector is a grating layer or a medium layer DBR;
(3) Bonding a one-piece final substrate on the surface of the first reflector of each VCSEL chip, and selectively etching the sacrificial layer of each VCSEL chip by using an HF solution so as to strip the InP substrate from the bottom of each VCSEL chip;
(4) Manufacturing a second reflecting mirror on the surface of the InP second buffer layer of each VCSEL chip; the second reflecting mirror is a grating layer or a medium layer DBR.
2. The method of claim 1, wherein the fabrication of the single chip lifted combined mirror long wavelength VCSEL comprises: the step (3) comprises the following substeps:
(3.1) bonding a one-piece extensible adhesive tape on the first mirror surface of each VCSEL chip;
(3.2) selectively etching the sacrificial layer of each VCSEL chip by using an HF solution so as to strip the InP substrate from the bottom of each VCSEL chip;
(3.3) transferring each VCSEL chip to a one-piece temporary substrate through a malleable adhesive tape, and removing the malleable adhesive tape;
(3.4) transfer-bonding each VCSEL chip onto the final substrate through the temporary substrate, and removing the temporary substrate.
3. The method of claim 2, wherein the method comprises the steps of: in step (3.3), the stretchable adhesive tape is first stretched using a stretching device so that the position of each VCSEL chip corresponds to a predetermined chip position, then the VCSEL chips are transferred onto the temporary substrate, and finally the stretchable adhesive tape is removed.
4. The method of claim 1, wherein the fabrication of the single chip lifted combined mirror long wavelength VCSEL comprises: the DBR of the medium layer is made of SiO 2 /Si 3 N 4 The period of the reflector is 4-8, and the thickness is 1800-3750nm.
5. The method of claim 1, wherein the fabrication of the single chip lifted combined mirror long wavelength VCSEL comprises: the high-refractive-index material of the grating layer is SiO 2 Or Si 3 N 4 The low refractive index material is air or an oxide.
6. The method of claim 1, wherein the fabrication of the single chip lifted combined mirror long wavelength VCSEL comprises: the grating period 550nm of the grating layer is less than ^ 800nm, the filling coefficient 350nm is less than eta and less than 500nm, and the grating depth 350nm is less than tg and less than 500nm.
7. The method of claim 1, wherein the fabrication of the single chip lifted combined mirror long wavelength VCSEL comprises: the sacrificial layer is of an AlAs/InAlAs/AlAs/InAlAs/AlAs superlattice structure, the thickness of the AlAs is 1.5-2.1nm, and the thickness of the InAlAs is 1nm.
8. The method of claim 1, wherein the method comprises the steps of: the first N-type doped DBR and the second N-type doped DBR are mirrors formed by InAlGaAs/InP or InGaAsP/InP periodic stacking; the number of cycles of the first N-type doping DBR and the number of cycles of the second N-type doping DBR are both 5-20, and the thickness is 1000-5000nm.
9. The method of claim 1, wherein the method comprises the steps of: the final substrate is a silicon wafer with a thickness of 300-700 μm.
CN202211008408.4A 2022-08-22 2022-08-22 Preparation method of single-chip-stripped combined reflector type long wavelength VCSEL Pending CN115347456A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202211008408.4A CN115347456A (en) 2022-08-22 2022-08-22 Preparation method of single-chip-stripped combined reflector type long wavelength VCSEL

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202211008408.4A CN115347456A (en) 2022-08-22 2022-08-22 Preparation method of single-chip-stripped combined reflector type long wavelength VCSEL

Publications (1)

Publication Number Publication Date
CN115347456A true CN115347456A (en) 2022-11-15

Family

ID=83954050

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202211008408.4A Pending CN115347456A (en) 2022-08-22 2022-08-22 Preparation method of single-chip-stripped combined reflector type long wavelength VCSEL

Country Status (1)

Country Link
CN (1) CN115347456A (en)

Similar Documents

Publication Publication Date Title
CN115085006B (en) Long wavelength VCSEL with combined reflectors at two ends and preparation method thereof
JP3425185B2 (en) Semiconductor element
KR100523484B1 (en) Method for fabricating semiconductor optical devices having current-confined structure
JPH03236295A (en) Vertical cavity semiconductor laser device
US20080093622A1 (en) Light-Emitter-Based Devices with Lattice-Mismatched Semiconductor Structures
US7680162B2 (en) Long wavelength vertical cavity surface emitting laser device and method of fabricating the same
JP2008503090A (en) II-VI / III-V layered structure on InP substrate
WO2002017361A1 (en) A method for aperturing vertical-cavity surface-emitting lasers (vscels)
JPH10215026A (en) Ultraviolet-visible-light-emitting vertical cavity surface emitting laser and its manufacturing device
JP2003258384A (en) LONG-WAVELENGTH PHOTONICS DEVICE INCLUDING GaAsSb QUANTUM WELL LAYER
CN111628410A (en) 1.55-micron wavelength silicon-based quantum dot laser epitaxial material and preparation method thereof
JP2628801B2 (en) Semiconductor laser structure
US20030086467A1 (en) DBR comprising GaP, and use thereof in a semiconductor resonant cavity device
JPWO2014167965A1 (en) Nitride semiconductor multilayer mirror and light emitting device using the same
JP2001093837A (en) Structure of semiconductor thin film and manufacturing method therefor
CN113725731B (en) Dual-wavelength vertical cavity surface emitting laser and preparation method thereof
CN114421283A (en) Double-doped quantum dot active region epitaxial structure and preparation method and application thereof
CN114865451A (en) Epitaxial structure of buried non-oxidized aperture VCSEL and preparation process thereof
CN217740981U (en) Human eye safe long wavelength VCSEL array chip for laser radar
CN113422295A (en) Multi-junction distributed feedback semiconductor laser and preparation method thereof
JP2004281559A (en) Semiconductor light emitting device
CN115347456A (en) Preparation method of single-chip-stripped combined reflector type long wavelength VCSEL
CN214255059U (en) Laser epitaxial structure and VCSEL chip
JP2011134967A (en) Semiconductor light emitting element
CN114976865A (en) High-efficiency vertical cavity surface EML chip with high-contrast grating

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination