CN115347090A - Preparation method of nanoscale patterned substrate and nanoscale patterned substrate - Google Patents

Preparation method of nanoscale patterned substrate and nanoscale patterned substrate Download PDF

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CN115347090A
CN115347090A CN202211057372.9A CN202211057372A CN115347090A CN 115347090 A CN115347090 A CN 115347090A CN 202211057372 A CN202211057372 A CN 202211057372A CN 115347090 A CN115347090 A CN 115347090A
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sacrificial layer
layer
substrate
forming
round hole
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林源为
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Beijing Naura Microelectronics Equipment Co Ltd
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Beijing Naura Microelectronics Equipment Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/22—Roughened surfaces, e.g. at the interface between epitaxial layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds

Abstract

The invention discloses a preparation method of a nanoscale patterned substrate and the nanoscale patterned substrate, and the method comprises the following steps: providing a substrate, and forming a photoresist layer on the substrate; patterning the photoresist layer, and forming a plurality of first round holes penetrating through the photoresist layer on the photoresist layer; forming a first sacrificial layer, wherein the first sacrificial layer covers the inner wall of the first round hole to form a second round hole with the diameter of a nanometer level; forming a first etching mask layer, wherein the first etching mask layer fills the second round hole and forms a cylinder with the diameter of a nanometer level in the second round hole; and etching the substrate to form a nanoscale conical array on the surface of the substrate. The invention can realize the manufacture of the nano-scale patterned substrate with conical appearance by adopting a micron-scale process.

Description

Preparation method of nanoscale patterned substrate and nanoscale patterned substrate
Technical Field
The invention relates to the field of LED substrate manufacturing, in particular to a preparation method of a nanoscale patterned substrate and the nanoscale patterned substrate.
Background
Patterned sapphire substrates in the field of Light Emitting Diodes (LEDs) are patterned by etching (dry etching/wet etching on sapphire C-plane) on a sapphire substrate, and a micron-scale or nano-scale pattern with a specific microstructure is designed and manufactured on the sapphire substrate, so as to control the output Light form of an LED device (the concave-convex pattern on the sapphire substrate can generate Light scattering or refraction effect to increase the Light extraction rate), and meanwhile, a GaN film grown on the patterned sapphire substrate can generate a lateral epitaxy effect, reduce the dislocation defect between GaN grown on the sapphire substrate, improve the epitaxy quality, improve the internal quantum efficiency of the LED, and increase the Light extraction efficiency. Compared with the LED of a common sapphire substrate, the brightness of the LED based on the PSS is increased by more than 70%.
With the continuous improvement of the display resolution of the LED, the pixel period (pixel pitch) of the LED device is continuously reduced, and the chip size is gradually reduced from the early millimeter level to the current micrometer level, and even reaches the nanometer level in the future. It has been proved that the performance of the LED device using the nano-scale patterned sapphire substrate, such as the light output power, is better than that of the flat sapphire substrate, but the existing method for preparing the micro-scale patterned sapphire substrate is limited by the factors such as the lithography exposure precision, and cannot be used for obtaining the nano-scale PSS substrate. The method for patterning the sapphire substrate in the nanometer scale has high requirements on the photoetching precision and high equipment cost, and has the problems that the microstructure distribution of the surface of the patterned sapphire is not uniform, or a microscopic conical structure with a sharp tip is difficult to generate.
Disclosure of Invention
The invention aims to provide a preparation method of a nanoscale patterned substrate and the nanoscale patterned substrate, and aims to realize the manufacturing of the nanoscale patterned substrate with conical appearance by adopting a micron-scale process.
In a first aspect, the present invention provides a method for preparing a nanoscale patterned substrate, comprising:
providing a substrate, and forming a photoresist layer on the substrate;
patterning the photoresist layer, and forming a plurality of first round holes penetrating through the photoresist layer on the photoresist layer;
forming a first sacrificial layer, wherein the first sacrificial layer covers the inner wall of the first round hole to form a second round hole with the diameter of a nanometer level;
forming a first etching mask layer, wherein the first etching mask layer fills the second round hole and forms a cylinder with the diameter of a nanometer level in the second round hole;
and etching the substrate to form a nanoscale conical array on the surface of the substrate.
Optionally, the forming the first sacrificial layer includes:
forming the first sacrificial layer on the photoresist layer, wherein the first sacrificial layer covers the surface of the photoresist layer, the side wall of the first round hole and the bottom of the first round hole;
the first sacrificial layer on the inner wall of the first round hole forms a side wall, and the side wall forms the second round hole in a surrounding manner;
and removing the first sacrificial layer at the bottom of the second round hole.
Optionally, the forming the first etching mask layer includes:
forming a second sacrificial layer on the substrate, wherein the second sacrificial layer fills the second round hole and covers the first sacrificial layer above the photoresist layer;
removing the first sacrificial layer and the second sacrificial layer above the photoresist layer and exposing the photoresist layer; forming a cylinder with the diameter of a nanometer level in the second round hole by remaining the second sacrificial layer;
removing the photoresist layer and exposing the side wall;
and removing the side wall, wherein the rest second sacrificial layer forms the first etching mask layer.
Optionally, before the removing the first sacrificial layer at the bottom of the first circular hole, the preparation method further includes:
forming a second sacrificial layer on the substrate, wherein the second sacrificial layer fills the second round hole and covers the first sacrificial layer above the photoresist layer;
removing the first sacrificial layer and the second sacrificial layer above the photoresist layer and exposing the photoresist layer;
removing the photoresist layer and exposing the side wall;
forming a third sacrificial layer, wherein the third sacrificial layer covers the substrate and surrounds the side wall, and the third sacrificial layer and the first sacrificial layer are made of the same material;
and removing the second sacrificial layer in the second round hole.
Optionally, after the removing the first sacrificial layer at the bottom of the second circular hole, the forming an etching mask layer includes:
forming a fourth sacrificial layer, wherein the fourth sacrificial layer fills the second round hole and forms a nanoscale cylinder in the second round hole;
and removing the third sacrificial layer and the side wall, and remaining the fourth sacrificial layer to form the first etching mask layer.
Optionally, before forming the photoresist layer on the substrate, the preparation method further includes: and forming a first dielectric layer on the surface of the substrate, wherein the first etching mask layer is formed on the first dielectric layer.
Optionally, the fourth sacrificial layer is made of photoresist, and the first dielectric layer is made of silicon dioxide.
Optionally, one of the first sacrificial layer and the second sacrificial layer is silicon nitride, and the other is silicon dioxide; or one of the metal and the silicon dioxide or the silicon nitride; or both may be different metallic materials.
Optionally, the substrate is a sapphire substrate.
In a second aspect, the present invention provides a nanoscale patterned substrate obtained by the method for preparing the nanoscale patterned substrate according to any one of the first aspects.
The invention has the beneficial effects that:
the method comprises the steps of firstly forming a photoresist layer on a substrate, then patterning the photoresist layer, forming a plurality of first round holes penetrating through the photoresist layer on the photoresist layer, then forming a first sacrificial layer to cover the inner walls of the first round holes, so that second round holes with the diameter of nanometer are formed in the photoresist layer, then filling the second round holes through the second sacrificial layer and forming cylinders with the diameter of nanometer in the second round holes, then removing the photoresist layer and side walls formed by the first sacrificial layer, so that the second sacrificial layer filling the second round holes forms a first etching mask layer of a cylinder array on the surface of the substrate, etching the substrate by using the first etching mask layer, and forming a nanometer conical array on the surface of the substrate.
The system of the present invention has other features and advantages which will be apparent from or are set forth in detail in the accompanying drawings and the following detailed description, which are incorporated herein, and which together serve to explain certain principles of the invention.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings, in which like reference numerals generally represent like parts.
Fig. 1 shows a characterization diagram of an etching process of a prior art micron-sized sapphire patterned substrate. Fig. 2 is a schematic view showing a photoresist patterned in a conventional method of patterning a substrate with a micro-sized sapphire.
Fig. 3 is a step diagram showing a method of manufacturing a nano-scale patterned substrate according to embodiment 1 of the present invention.
Fig. 4 is a schematic diagram showing structural changes corresponding to respective steps of a method for manufacturing a nano-scale patterned substrate according to embodiment 1 of the present invention.
Fig. 5 shows a schematic diagram after photoresist patterning in a method for manufacturing a nano-scale patterned substrate according to embodiment 1 of the present invention.
Fig. 6 is a schematic diagram showing structural changes corresponding to respective steps of a method for manufacturing a nano-scale patterned substrate according to embodiment 2 of the present invention.
Detailed Description
In the conventional method for preparing a micron-sized sapphire patterned substrate, as shown in fig. 1, profile characterization diagrams of each process of etching preparation are shown, and finally a conical patterned PSS substrate is obtained. The top view of the photoresist before etching is shown in fig. 2, wherein the black area represents the photoresist left on the wafer surface after the photolithography, and the white part represents the photoresist washed away after the photolithography, i.e., the wafer substrate exposed in the area, because the micron-scale process is adopted, the micron-scale process is limited by the factors such as the photolithography exposure precision, and the like, and the micron-scale process cannot be used for obtaining the nano-scale PSS substrate. Theoretically, to obtain a conical patterned substrate at the nanometer level, only the black part of the photoresist pattern needs to be made to be at the nanometer level, but this poses a challenge to the resolution of the lithography, especially in the case where a circular pattern is left and most of the area is washed away, and the uniformity of each circular pattern after being scaled down to the nanometer level is difficult to control.
In contrast, the present invention enables the fabrication of nano-scale patterned substrates using existing micro-scale processing equipment without increasing the resolution of the lithography machine, i.e., without increasing the cost of the equipment.
The invention will be described in more detail below with reference to the accompanying drawings. While the preferred embodiments of the present invention are illustrated in the accompanying drawings, it is to be understood that the invention may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.
Example 1
As shown in fig. 3 and 4, a method of fabricating a nano-scale patterned substrate includes:
s101: providing a substrate, and forming a photoresist layer 2 on the substrate;
specifically, the substrate in this embodiment is a sapphire substrate 1 (wafer), a photoresist may be spin-coated on the substrate to form the photoresist layer 2, preferably, the thickness of the photoresist layer 2 is 2 to 10 micrometers, and the spin-coating rotation speed may be determined according to the thickness value.
S102: patterning the photoresist layer 2, and forming a plurality of first round holes 3 penetrating through the photoresist layer 2 on the photoresist layer 2;
specifically, in this embodiment, a micron-sized lithography machine may be used to pattern the photoresist layer 2, the method for patterning the photoresist layer 2 includes lithography exposure and development, the mask plate for patterning the photoresist layer 2 in this step may be designed and processed in advance as required, and after the development, the photoresist pattern shown in fig. 5 is obtained, the diameter of the first circular hole 3 on the photoresist layer 2 is less than or equal to 1 micron, where the exposure time is 3 to 20s, in this embodiment, 6 seconds is preferred, the development time is 45 to 120s, in this embodiment, 75s is preferred, the fixing time is 60 to 300s, in this embodiment, 120s is preferred, so as to pattern the photoresist.
S103: forming a first sacrificial layer 4, wherein the first sacrificial layer 4 covers the inner wall of the first round hole 3 to form a second round hole 5 with the diameter of nanometer level;
in this embodiment, the method of forming the first sacrificial layer 4 includes:
forming a first sacrificial layer 4 on the photoresist layer 2, wherein the first sacrificial layer 4 covers the surface of the photoresist layer 2, the side wall of the first round hole 3 and the bottom of the first round hole 3;
the first sacrificial layer 4 on the inner wall of the first round hole 3 forms a side wall 7, and the side wall 7 encloses a second round hole 5;
the first sacrificial layer 4 at the bottom of the second circular hole 5 is removed.
Specifically, a plasma enhanced chemical vapor deposition process may be adopted to form the first sacrificial layer 4 on the photoresist layer 2, and the first sacrificial layer 4 covers the surface of the photoresist layer 2, the side wall of the first circular hole 3 and the bottom of the first circular hole 3; wherein, the first sacrificial layer 4 covering the inner wall of the round hole forms a side wall 7;
and finally, etching the first sacrificial layer 4 by adopting a dry etching process, removing the first sacrificial layer 4 at the bottom of the round hole and exposing the surface of the substrate.
In this embodiment, the material of the first sacrificial layer 4 is preferably silicon nitride, a layer of silicon nitride may be grown by plasma enhanced chemical vapor deposition, and the process conditions for forming the first sacrificial layer 4 are as follows:
the temperature of the chamber ranges from 300 ℃ to 500 ℃, preferably 400 ℃, the inflow gas flow ranges from 10 sccm to 10000sccm, preferably 1000sccm, the gas types comprise one or more of silane, ammonia gas and nitrogen gas, the chamber pressure ranges from 50mTorr to 50000mTorr, preferably 650mTorr, the radio frequency power ranges from 5W to 50000W, preferably 100W, the thickness is determined according to the diameter of the first photoetching round hole 3, so that the diameter of the rest round holes reaches the nanometer level, the range is 10nm to 1000nm, and the thickness of deposited silicon nitride is preferably 500nm.
And then, etching silicon nitride by adopting plasma, stopping on the sapphire substrate 1 to remove the first sacrificial layer 4 at the bottom of the first round hole 3, wherein the etching process conditions are as follows:
the cavity pressure range is 0.5-50 mTorr, the upper electrode power range is 600-3000W, the lower electrode power range is 50-3000W, the chuck temperature range is-15-50 ℃, the etching gas is fluorocarbon gas, and can be one or more of fluorocarbon gases such as octafluorocyclobutane, hexafluorobutadiene, carbon tetrafluoride, trifluoromethane, difluoromethane, fluoromethane and the like, hydrogen or oxygen can be added to adjust the selection ratio, the flow range of the etching gas is 10-1000 sccm, the pressure range of the wafer back helium is 1-20 Torr, and the process time is determined according to the thickness of the grown silicon nitride.
S104: forming a first etching mask layer, wherein the first etching mask layer fills the second round hole 5 and forms a cylinder with the diameter of nanometer in the second round hole 5;
wherein forming the first etch mask layer comprises:
forming a second sacrificial layer 6 on the substrate, wherein the second sacrificial layer 6 fills the second round hole 5 and covers the first sacrificial layer 4 above the photoresist layer 2;
removing the first sacrificial layer 4 and the second sacrificial layer 6 above the photoresist layer 2 and exposing the photoresist layer 2; the residual second sacrificial layer 3 forms a cylinder with the diameter of nanometer in the second round hole 5;
removing the photoresist layer 2 and exposing the side wall 7;
and removing the side wall 7, and forming a first etching mask layer on the residual second sacrificial layer 6.
Specifically, this step may employ a high density plasma chemical vapor deposition process to deposit a second sacrificial layer 6 on the substrate, where the second sacrificial layer 6 fills the second circular hole 5 and covers the first sacrificial layer 4 above the photoresist layer 2.
In this embodiment, the material of the second sacrificial layer 6 is preferably silicon dioxide, and the silicon dioxide may be filled by high density plasma chemical vapor deposition, where the deposition process conditions are as follows:
the temperature range is 300 ℃ to 1000 ℃, preferably 400 ℃, the inlet gas flow range is 10 to 10000sccm, preferably 1000sccm, the process gas species comprise one or more of silane, oxygen, hydrogen, argon, nitrogen trifluoride, the cavity pressure range is 5 to 500mTorr, preferably 7mTorr, the upper radio frequency power range is 500 to 50000W, preferably 5000W, and the lower radio frequency power range is 50 to 50000W, preferably 5000W.
Then, using chemical mechanical polishing to remove the first sacrificial layer 4 and the second sacrificial layer 6 above the photoresist layer 2 and expose the photoresist layer 2 until the top surface of the photoresist layer 2 is exposed, wherein the flow rate of the polishing solution in the chemical mechanical polishing process is 50-500 mL/min, preferably 200mL/min, and the pressure applied by the polishing head to the wafer is 0.1-10 psi, preferably 50g/cm 2 The rotation speed is 5 to 50rpm, preferably 10rpm.
Then, the photoresist is removed by a wet method, and a mixed solution of concentrated sulfuric acid and hydrogen peroxide can be used, or the photoresist can be washed away by an organic solvent such as acetone.
And then, removing the silicon nitride side wall 7 by adopting a plasma dry etching process, wherein the etching process conditions refer to the process conditions for etching the silicon nitride in the step S103.
After the photoresist and the silicon nitride side walls 7 are removed, only the nano-cylinder array formed by silicon dioxide remains on the sapphire substrate 1, and the photoresist nano-cylinder array is used as a mask layer for etching the sapphire substrate 1.
S105: and etching the substrate to form a nanoscale conical array on the surface of the substrate.
Specifically, in this embodiment, a cylindrical array formed by the second sacrificial layer 6 is used as the first etching mask layer, the sapphire substrate 1 is etched by using plasma, and the etching process conditions are as follows:
a chamber pressure in the range of 0.5 to 50mTorr, preferably 2.6mTorr, a top electrode power in the range of 600 to 3000W, preferably 1200W, a bottom electrode power in the range of 50 to 3000W, preferably 500W, a chuck temperature in the range of-15 to 50 ℃, preferably 20 ℃, BCl 3 The flow rate is in the range of 10 to 1000sccm, preferably 100sccm, the back helium pressure is in the range of 1 to 20Torr, and the process time is determined depending on the etching depth.
In this step, the silicon dioxide as the first etching mask layer is etched together, and a cone of sapphire material is etched below each nano-scale silicon dioxide cylinder, so that a nano-scale cone array morphology is formed on the surface of the sapphire substrate 1.
In this embodiment, after forming the nanoscale conical array, the method further includes:
step S106: a gallium nitride epitaxial layer 8 covering the cone array is formed on the substrate by an epitaxial process.
Specifically, the growth method of the gallium nitride epitaxial layer 8 of the present embodiment is: introducing trimethyl indium, trimethyl gallium and ammonia gas into the reaction chamber, heating to 700 ℃, controlling the growth rate at 0.05 mu m/h, and depositing an InGaN nucleating layer with the thickness of 5nm on the substrate; then, continuously keeping the introduction of trimethyl indium, trimethyl gallium and ammonia gas, increasing the temperature in the chamber to 800 ℃, and increasing the growth rate to 0.2 mu m/h to form an InGaN insertion layer; and then stopping introducing the trimethyl indium, continuously introducing trimethyl gallium and ammonia gas into the reaction chamber, heating to 1100 ℃, and continuously depositing the GaN epitaxial layer 8 on the reaction chamber.
It should be noted that, in this embodiment, the materials of the first sacrificial layer 4 and the second sacrificial layer 6 may be interchanged, the material of the first sacrificial layer 4 is silicon dioxide, the material of the second sacrificial layer 6 is silicon nitride, and the materials of the first sacrificial layer 4 and the second sacrificial layer 6 may also use a combination of metal (such as gold, silver, copper, aluminum, titanium, etc.)/silicon dioxide, metal (such as gold, silver, copper, aluminum, titanium, etc.)/silicon nitride, or metal/metal (such as copper/aluminum), besides the combination of silicon dioxide and silicon nitride, and if different combinations of the materials of the first sacrificial layer 4 and the second sacrificial layer 6 are selected, specific etching process conditions may be set according to the etching selection ratio of the two sacrificial materials.
Example 2
As shown in fig. 6, the present embodiment provides another method for manufacturing a nano-scale patterned substrate, including: step S201: providing a substrate, and forming a photoresist layer 2 on the substrate;
in this embodiment, before forming the photoresist layer 2 on the substrate, the preparation method further includes: a first dielectric layer 11 is formed on the surface of the substrate, and a first etching mask layer formed subsequently is formed on the first dielectric layer 11. In this embodiment, the first dielectric layer 11 is made of silicon dioxide.
Specifically, before step S201 is performed, a sapphire substrate 1 is provided, and then a layer of silicon dioxide is grown on the sapphire substrate 1 as a first dielectric layer 11, where the thickness of the first dielectric layer 11 is 1 to 5 microns, preferably 2 microns, and the first dielectric layer 11 may be formed by using processes such as low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, high-density plasma chemical vapor deposition, electron beam evaporation, magnetron sputtering, and the like.
Then, step S201 is performed, a photoresist is spin-coated on the first dielectric layer 11 to form a photoresist layer 2, the thickness of the photoresist layer 2 is 2 to 10 microns, the thickness of the photoresist layer 2 in this embodiment is preferably twice the thickness of the previously grown silicon dioxide (first dielectric layer 11), i.e. 6 microns, and the rotation speed of the spin coating is determined according to the thickness value of the photoresist.
Step S202: patterning the photoresist layer 2, and forming a plurality of first round holes 3 penetrating through the photoresist layer 2 on the photoresist layer 2;
specifically, the method of patterning the photoresist layer 2 refers to step S102 of embodiment 1.
Step S203: forming a first sacrificial layer 4, wherein the first sacrificial layer 4 covers the inner wall of the first round hole 3 to form a second round hole 5 with the diameter of nanometer level;
wherein forming the first sacrificial layer comprises:
forming a first sacrificial layer 4 on the photoresist layer 2, wherein the first sacrificial layer 4 covers the surface of the photoresist layer 2, the side wall of the first round hole 3 and the bottom of the first round hole 3;
the first sacrificial layer 4 on the inner wall of the first round hole 3 forms a side wall 7, and the side wall 7 encloses a second round hole 5;
the first sacrificial layer 4 at the bottom of the second circular hole 5 is removed.
In this embodiment, before removing the first sacrificial layer 4 at the bottom of the first circular hole 3, the preparation method of this embodiment further includes:
forming a second sacrificial layer 6 on the substrate, wherein the second sacrificial layer 6 fills the second round hole 5 and covers the first sacrificial layer 4 above the photoresist layer 2;
removing the first sacrificial layer 4 and the second sacrificial layer 6 above the photoresist layer 2 and exposing the photoresist layer 2;
removing the photoresist layer 2 and exposing the side wall 7;
forming a third sacrificial layer 9, wherein the third sacrificial layer 9 covers the substrate and surrounds the side wall 7, and the material of the third sacrificial layer 9 is the same as that of the first sacrificial layer 4;
the second sacrificial layer 6 in the second circular hole 5 is removed.
Specifically, the method of forming the first sacrificial layer 4 in this step includes:
and forming a first sacrificial layer 4 on the photoresist layer 2 by adopting a plasma enhanced chemical vapor deposition process, wherein the first sacrificial layer 4 covers the surface of the photoresist layer 2, the inner side wall of the first round hole 3 and the surface of the substrate exposed at the bottom of the first round hole 3, and the first sacrificial layer 4 covering the inner wall of the round hole forms a side wall 7.
Preferably, the first sacrificial layer 4 in this embodiment is silicon nitride, and the method for depositing and forming the first sacrificial layer 4 refers to step S103 in embodiment 1. The thickness range of the side wall 7 in this embodiment is 10nm to 1000nm, preferably 500nm, so that the diameter of the remaining circular hole reaches the nanometer level.
After the first sacrificial layer 4 is formed, a second sacrificial layer 6 is formed on the substrate, and the second sacrificial layer 6 fills the second round hole 5; a method of forming a second sacrificial layer 6, comprising:
and depositing a second sacrificial layer 6 on the substrate by adopting a high-density plasma chemical vapor deposition process, wherein the second sacrificial layer 6 fills the second round hole 5 and covers the first sacrificial layer 4 above the photoresist layer 2.
The second sacrificial layer 6 in this embodiment is preferably silicon dioxide, and the method of depositing the second sacrificial layer 6 is referred to embodiment 1.
After the second sacrificial layer 6 is formed, the first sacrificial layer 4 and the second sacrificial layer 6 over the photoresist layer 2 are removed using a chemical mechanical polishing process, and the photoresist layer 2 is exposed. Method of chemical mechanical polishing until the photoresist is exposed reference is made to example 1.
After the photoresist layer 2 is exposed, the photoresist is removed by a wet method, and a mixed solution of concentrated sulfuric acid and hydrogen peroxide or an organic solvent such as acetone is used.
After the photoresist layer is removed, a third sacrificial layer 9 is formed on the substrate by adopting a plasma enhanced chemical vapor deposition process, the material of the third sacrificial layer 9 is the same as that of the first sacrificial layer 4, and the third sacrificial layer 9 covers the substrate, the second sacrificial layer 6 and the side wall 7;
and then, removing the second sacrificial layer 6 and the third sacrificial layer 9 above the side wall 7 by adopting a chemical mechanical polishing process to expose the second sacrificial layer 6.
The material of the third sacrificial layer 9 in this embodiment is preferably silicon nitride, and a layer of silicon nitride may be grown by using plasma enhanced chemical vapor deposition, and the deposition process conditions refer to the process conditions for depositing the first sacrificial layer 4 in step S103 in embodiment 1.
After the third sacrificial layer 9 material is formed, it is planarized by chemical mechanical polishing until the second sacrificial layer 6 on top of the second circular hole 5 is exposed.
And then, removing the second sacrificial layer 6 in the second round hole 5 and the first sacrificial layer 4 at the bottom of the second round hole 5 by adopting a dry etching process. In other embodiments, removing the first sacrificial layer 4 at the bottom of the second circular hole 5 may also be completed before forming the second sacrificial layer 6.
In a specific implementation process, the second sacrificial layer 6 (silicon dioxide) in the second circular hole 5 may be removed by plasma etching, and the process conditions for etching the second sacrificial layer 6 are as follows:
the cavity pressure range is 0.5-50 mTorr, the upper electrode power range is 600-3000W, the lower electrode power range is 50-3000W, the chuck temperature range is-15-50 ℃, the etching gas is fluorocarbon gas (one or more of fluorocarbon gases such as octafluorocyclobutane, hexafluorobutadiene, carbon tetrafluoride, trifluoromethane, difluoromethane and fluoromethane, and hydrogen or oxygen can be added to adjust the selection ratio), the flow range is 10-1000 sccm, the back helium pressure range is 1-20 Torr, the process time is changed along with the thickness of the silicon dioxide, the step can also adopt hydrofluoric acid wet etching silicon dioxide, but the selection ratio between the silicon dioxide and the silicon nitride needs to be noticed no matter dry method or wet method; the etch selectivity of silicon nitride to silicon dioxide in this embodiment is greater than 10.
Then, continuing to etch the silicon nitride (the first sacrificial layer 4) exposed at the bottom of the second round hole 5 by using the plasma, and stopping on the second mask layer 11 (the silicon dioxide layer), wherein the process conditions for etching the silicon nitride (removing the first sacrificial layer 4 at the bottom of the second round hole 5) are as follows:
the cavity pressure range is 0.5-50 mTorr, the upper electrode power range is 600-3000W, the lower electrode power range is 50-3000W, the chuck temperature range is-15-50 ℃, the flow range of fluorocarbon gas (can be one or more of fluorocarbon gases such as octafluorocyclobutane, hexafluorobutadiene, carbon tetrafluoride, trifluoromethane, difluoromethane, fluoromethane and the like, and hydrogen or oxygen can be added to adjust the selection ratio) is 10-1000 sccm, the back helium pressure range is 1-20 Torr, and the process time is changed along with the thickness of the silicon nitride grown in the fourth step.
After this step is completed, only the nanopores (second circular holes 5) formed by the second circular holes 5 in the silicon nitride layer remain on the second mask layer 11.
Step S204: forming a first etching mask layer, wherein the first etching mask layer fills the second round hole and forms a cylinder with the diameter of a nanometer level in the second round hole;
the method specifically comprises the following steps: forming a fourth sacrificial layer 10, wherein the fourth sacrificial layer 10 fills the second round hole 5 and forms a nanoscale cylinder in the second round hole 5;
and removing the third sacrificial layer 9 and the side walls 7, and remaining the fourth sacrificial layer 10 to form a first etching mask layer.
In this embodiment, the material of the fourth sacrificial layer 10 is preferably photoresist, the photoresist can be filled with the nanopores (the second circular holes 5) formed by the silicon nitride by means of dropping the photoresist, or the photoresist can be spin-coated, and if the photoresist is too thick after this step, the chemical mechanical polishing can be continued until the silicon nitride is exposed.
And then, removing the third sacrificial layer 9 and the side wall 7 by adopting a wet etching process. Namely, wet etching is adopted to remove all the silicon nitride layer on the periphery of the photoresist nanometer cylinder formed by the fourth sacrificial layer 10 in the nanometer pore.
In this embodiment, the process conditions for wet etching silicon nitride are as follows: 85% concentrated phosphoric acid and 15% deionized water are adopted, and the etching temperature is 140-200 ℃.
After the silicon nitride is removed, only the nano-cylinder array formed by the fourth sacrificial layer 11 (photoresist) remains on the first dielectric layer 11 (silicon dioxide layer), and the photoresist nano-cylinder array serves as a first mask layer.
Step S205: and etching the substrate and the first dielectric layer to form a nanoscale conical array on the surface of the substrate.
Specifically, in this step, a plasma dry etching process may be used to etch the silicon dioxide material of the first dielectric layer 11, and the specific process conditions may be: the cavity pressure range is 0.5-50 mTorr, the upper electrode power range is 600-3000W, the lower electrode power range is 50-3000W, the chuck temperature range is-15-50 ℃, the flow range of fluorocarbon gas (can be one or more of fluorocarbon gases such as octafluorocyclobutane, hexafluorobutadiene, carbon tetrafluoride, trifluoromethane, difluoromethane, fluoromethane and the like, and hydrogen or oxygen can be added to adjust the selection ratio) is 10-1000 sccm, the back helium pressure range is 1-20 Torr, and the process time is changed along with the thickness of silicon dioxide.
In the step, the photoresist used as the mask layer is etched together, and a cone structure formed by silicon dioxide and sapphire together is etched below each nano-scale cylindrical photoresist, so that a nano-scale cone array shape is formed on the substrate.
In this embodiment, after forming the nanoscale conical array, the method further includes:
step S206: a gallium nitride epitaxial layer 8 covering the cone array is formed on the substrate by an epitaxial process.
A specific process for epitaxially growing the gallium nitride epitaxial layer 8 is referred to step S106 of example 1.
Example 3
The present embodiment provides a nanoscale patterned substrate manufactured by the method for manufacturing a nanoscale patterned substrate according to any one of the above embodiments.
The nanoscale patterned substrate of the embodiment adopts a micron-scale manufacturing process to realize the conical nanoscale patterned substrate, can utilize the existing lithography equipment to obtain the nanoscale patterned substrate, does not need to upgrade the lithography equipment, reduces the equipment cost, has clear tip of the nanoscale conical structure and regular arrangement of the conical nanoscale patterns, and can effectively improve the brightness of an LED device by adopting the nanoscale patterned substrate.
While embodiments of the present invention have been described above, the above description is illustrative, not exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments.

Claims (10)

1. A method of making a nanoscale patterned substrate, comprising:
providing a substrate, and forming a photoresist layer on the substrate;
patterning the photoresist layer, and forming a plurality of first round holes penetrating through the photoresist layer on the photoresist layer;
forming a first sacrificial layer, wherein the first sacrificial layer covers the inner wall of the first round hole to form a second round hole with the diameter of a nanometer level;
forming a first etching mask layer, wherein the first etching mask layer fills the second round hole and forms a cylinder with the diameter of a nanometer level in the second round hole;
and etching the substrate to form a nanoscale conical array on the surface of the substrate.
2. The method of manufacturing according to claim 1, wherein the forming a first sacrificial layer includes:
forming the first sacrificial layer on the photoresist layer, wherein the first sacrificial layer covers the surface of the photoresist layer, the side wall of the first round hole and the bottom of the first round hole;
the first sacrificial layer on the inner wall of the first round hole forms a side wall, and the side wall forms the second round hole in a surrounding mode;
and removing the first sacrificial layer at the bottom of the second round hole.
3. The method of claim 2, wherein the forming a first etch mask layer comprises:
forming a second sacrificial layer on the substrate, wherein the second sacrificial layer fills the second round hole and covers the first sacrificial layer above the photoresist layer;
removing the first sacrificial layer and the second sacrificial layer above the photoresist layer and exposing the photoresist layer; forming a cylinder with the diameter of a nanometer level in the second round hole by remaining the second sacrificial layer;
removing the photoresist layer and exposing the side wall;
and removing the side wall, wherein the rest second sacrificial layer forms the first etching mask layer.
4. The method of claim 2, wherein prior to the removing the first sacrificial layer at the bottom of the first circular hole, the method further comprises:
forming a second sacrificial layer on the substrate, wherein the second sacrificial layer fills the second round hole and covers the first sacrificial layer above the photoresist layer;
removing the first sacrificial layer and the second sacrificial layer above the photoresist layer and exposing the photoresist layer;
removing the photoresist layer and exposing the side wall;
forming a third sacrificial layer, wherein the third sacrificial layer covers the substrate and surrounds the side wall, and the third sacrificial layer and the first sacrificial layer are made of the same material;
and removing the second sacrificial layer in the second round hole.
5. The method according to claim 4, wherein after the removing the first sacrificial layer at the bottom of the second circular hole, the forming a first etching mask layer comprises:
forming a fourth sacrificial layer, wherein the fourth sacrificial layer fills the second round hole and forms a nanoscale cylinder in the second round hole;
and removing the third sacrificial layer and the side wall, and remaining the fourth sacrificial layer to form the first etching mask layer.
6. The method of claim 5, wherein prior to forming a photoresist layer on the substrate, the method further comprises: and forming a first dielectric layer on the surface of the substrate, wherein the first etching mask layer is formed on the first dielectric layer.
7. The method according to claim 6, wherein the fourth sacrificial layer is made of photoresist, and the first dielectric layer is made of silicon dioxide.
8. The manufacturing method according to any one of claims 1 to 7, wherein one of the first sacrificial layer and the second sacrificial layer is silicon nitride and the other is silicon dioxide; or one of the metal and the silicon dioxide or the silicon nitride; or both may be different metallic materials.
9. The production method according to claim 3 or 6, wherein the substrate is a sapphire substrate.
10. A nano-scale patterned substrate obtained by the method for producing a nano-scale patterned substrate according to any one of claims 1 to 9.
CN202211057372.9A 2022-08-31 2022-08-31 Preparation method of nanoscale patterned substrate and nanoscale patterned substrate Pending CN115347090A (en)

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