CN115346869A - Etching method and semiconductor structure - Google Patents

Etching method and semiconductor structure Download PDF

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Publication number
CN115346869A
CN115346869A CN202211021853.4A CN202211021853A CN115346869A CN 115346869 A CN115346869 A CN 115346869A CN 202211021853 A CN202211021853 A CN 202211021853A CN 115346869 A CN115346869 A CN 115346869A
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layer
etching
opening
hard mask
pattern
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杨谦
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Changxin Memory Technologies Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure

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Abstract

The embodiment of the application provides an etching method and a semiconductor structure, wherein the method comprises the following steps: providing a substrate, wherein the substrate at least comprises an etching layer and a first photoresist layer with a first opening, which is positioned on the etching layer; depositing a first protective layer on the side wall of the first opening to form a first photoresist layer with a second opening; and etching the etching layer through the second opening to form a first target pattern in the etching layer.

Description

Etching method and semiconductor structure
Technical Field
The present application relates to the field of semiconductor technology, and relates to, but is not limited to, an etching method and a semiconductor structure.
Background
The photolithography process is usually used to etch a desired pattern on the etching layer, and as the product is continuously upgraded, the Critical Dimension (CD) of the inner wall of the pattern is less and less required. Since the process window of the critical dimension of the photolithography process is generally larger than 38 nanometers (nm), the critical dimension cannot be further reduced, so the reduction of the critical dimension mainly depends on the etching process. As the critical dimension is further reduced, it becomes more difficult to reduce the critical dimension by the etching process; meanwhile, the etched process window is smaller and smaller, and the problems of hole disconnection, hole disappearance, short circuit, open circuit and the like are easy to occur. Therefore, it is desirable to provide a new etching method to increase the etching process window and reduce the critical dimension.
Disclosure of Invention
In view of the above, embodiments of the present application provide an etching method and a semiconductor structure.
In a first aspect, an embodiment of the present application provides an etching method, where the method includes: providing a substrate, wherein the substrate at least comprises an etching layer and a first photoresist layer with a first opening, which is positioned on the etching layer; depositing a first protective layer on the side wall of the first opening to form a first photoresist layer with a second opening; and etching the etching layer through the second opening to form a first target pattern in the etching layer.
In some embodiments, depositing a first protective layer on sidewalls of the first opening to form a first photoresist layer having a second opening includes: depositing an initial first protective layer on the first photoresist layer; and removing the initial first protective layer positioned on the upper surface of the first photoresist layer and at the bottom of the first opening, and reserving the initial first protective layer on the side wall of the first opening to form a first photoresist layer with a second opening.
In some embodiments, the providing a substrate comprises: forming the first photoresist layer on the etching layer; and patterning the first photoresist layer to form a first photoresist layer with the first opening.
In some embodiments, before forming the first photoresist layer on the etch layer, the method further comprises: sequentially forming a first hard mask layer, an etching stop layer, an etching penetrating layer and a second hard mask layer on the etching layer; correspondingly, the etching layer through the second opening to form a first target pattern in the etching layer includes: etching the second hard mask layer, the etching penetrating layer and the etching stopping layer through the second opening to form an etching stopping layer with a first middle pattern; and etching the first hard mask layer and the etching layer through the first middle pattern to form the first target pattern in the etching layer.
In some embodiments, the etching the second hard mask layer, the etch through layer, and the etch stop layer through the second opening to form an etch stop layer having a first intermediate pattern includes: etching the second hard mask layer through the second opening by adopting a first dry etching process to form a second hard mask layer with a second middle pattern; and etching the etching penetrating layer and the etching stopping layer through the second intermediate pattern by adopting a second dry etching process to form the etching stopping layer with the first intermediate pattern.
In some embodiments, the process parameters of the second dry etching process include: the flow rate of carbon hexafluoride is in a range of 22 to 26 standard milliliters per minute (sccm), the flow rate of argon is in a range of 160 to 200sccm, the flow rate of oxygen is in a range of 20 to 24sccm, the gas pressure is in a range of 13 to 17 millitorr (mTorr), the high frequency power is in a range of greater than 500 watts (W), the low frequency power is in a range of greater than 2000W, and the bias voltage is in a range of greater than 450V.
In some embodiments, after forming the etch stop layer having the first intermediate pattern, further comprising: forming a third intermediate pattern in the etch stop layer; and etching the first hard mask layer and the etching layer through the first intermediate pattern to form a second target pattern in the etching layer while forming a first target pattern in the etching layer and etching the first hard mask layer and the etching layer through the third intermediate pattern.
In some embodiments, forming a third intermediate pattern in the etch stop layer comprises: sequentially forming a third hard mask layer and a second photoresist layer with a third opening on the etching penetrating layer; depositing a second protective layer on the side wall of the third opening to form a second photoresist layer with a fourth opening; and etching the third hard mask layer, the etch through layer and the etch stop layer through the fourth opening to form the third intermediate pattern in the etch stop layer.
In some embodiments, before sequentially forming a third hard mask layer and a second photoresist layer having a third opening on the etch through layer, the method further includes: and removing all layers above the etching penetrating layer.
In some embodiments, the etch stop layer has an etch rate less than an etch rate of the etch-through layer under the same etch conditions.
In some embodiments, the initial first protection layer on the upper surface of the first photoresist layer and the bottom of the first opening is etched by a third dry etching process, and the initial first protection layer on the sidewall of the first opening is retained to form a first photoresist layer with a second opening, where the process parameters of the third dry etching process include: the flow rate of trifluoromethane is in the range of 25 to 35sccm, the flow rate of helium is in the range of 90 to 110sccm, the gas pressure is in the range of 4 to 6mTorr, and the bias voltage is in the range of greater than 200V.
In some embodiments, the material of the first protection layer and the etch through layer comprises an oxide, and the material of the etch stop layer comprises silicon oxynitride.
In some embodiments, the first intermediate pattern and the third intermediate pattern in the etch stop layer each have a depth ranging from 10nm to 30nm, and the etch stop layer has a thickness ranging from 25nm to 35nm.
In some embodiments, the initial first protective layer is deposited using an atomic vapor deposition process, the initial first protective layer having a thickness in a range from 5nm to 10nm.
In some embodiments, the first target pattern is used for forming a contact plug of a peripheral region in a semiconductor structure, and the contact plug is used for connecting a source electrode or a drain electrode in a transistor of the peripheral region with a metal interconnection layer of the peripheral region.
In a second aspect, embodiments of the present application provide a semiconductor structure, which is prepared according to the above etching method.
In the embodiment of the application, firstly, a first photoresist layer which at least comprises an etching layer and is provided with a first opening and positioned on the etching layer is provided; then depositing a first protective layer on the side wall of the first opening to form a first photoresist layer with a second opening; and finally, etching the etching layer through the second opening to form a first target pattern in the etching layer, so that the following effects can be realized:
in the first aspect, since the first passivation layer is deposited on the sidewall of the first opening, the horizontal dimension of the first opening is larger than the horizontal dimension of the second opening, that is, the horizontal dimension of the second opening is smaller than the horizontal dimension of the first opening, and the horizontal dimension of the second opening affects the critical dimension of the target pattern, so that the critical dimension of the first target pattern formed under the condition of the first opening with the same dimension can be reduced.
In the second aspect, since the first opening is formed by a photolithography process, and is affected by the photolithography process, the size of the first opening cannot be too small, and the size of the opening in the photoresist layer can be reduced and the process window of photolithography can be increased by depositing the first protective layer on the sidewall of the first opening.
In a third aspect, by depositing the first protective layer on the sidewall of the first opening, the verticality and the consistency of the first target pattern formed in the etching layer can be improved, and the occurrence of problems such as hole disconnection, hole disappearance, short circuit, disconnection, and the like can be reduced.
Drawings
Fig. 1A is a schematic view of an implementation process of an "LELE" process provided in an embodiment of the present application;
fig. 1B is a schematic flow chart of an etching method according to an embodiment of the present disclosure;
fig. 1C to fig. 1E, fig. 1G, and fig. 1H are schematic diagrams illustrating an implementation process of an etching method according to an embodiment of the present disclosure;
FIG. 1F is a schematic thickness diagram of an initial first protective layer deposited by an ALD process according to an embodiment of the present application;
fig. 2A to fig. 2C are schematic diagrams illustrating an implementation process for forming a second target pattern according to an embodiment of the present application;
fig. 3A, fig. 3B, fig. 3D to fig. 3F are schematic diagrams of another implementation process for forming a first target pattern and a second target pattern according to an embodiment of the present application;
fig. 3C is a schematic diagram of the etch stop layer including a first intermediate pattern according to the embodiment of the present disclosure;
fig. 4A to fig. 4G are schematic diagrams illustrating another implementation process for forming a first target pattern and a second target pattern according to an embodiment of the present application.
Detailed Description
Exemplary embodiments disclosed in the present application will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present application. It will be apparent, however, to one skilled in the art, that the present application may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present application; that is, not all features of an actual embodiment are described herein, and well-known functions and structures are not described in detail.
In the drawings, the size of layers, regions, elements, and relative sizes may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on … …," "adjacent … …," "connected to" or "coupled to" another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on … …," "directly adjacent … …," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application. And the discussion of a second element, component, region, layer or section does not imply that a first element, component, region, layer or section is necessarily present in the application.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Before introducing the solution of the present application, a method (denoted as POR) for improving the critical dimension of the etching process is introduced:
in the related art, since the CD of the etching process is small, the photoresist cannot be formed by one-time exposure, so that the etched pattern is split and double exposure, i.e., lithography, etching, lithography, and etching (LELE) is performed. Fig. 1A is a schematic diagram of an implementation process of the "LELE" process, in which fig. (a) is a first photolithography process for forming a first opening 103 on a first photoresist layer 102; FIG. (b) shows a first etching process for etching the etching layer 101 through the first opening 103 in FIG. (a) to form a first target pattern 107 on the etching layer 101; fig. c shows a second etching process, forming a fifth opening 202 in the third photoresist layer 201; fig. d is a second etching process for etching the etching layer 101 through the fifth opening 202 in fig. c to form a second target pattern 205 on the etching layer 101.
Due to the fact that the CD of an etching process is small, a photoetching process window is smaller and smaller, and the problems of poor uniformity of critical dimension, hole disconnection, hole disappearance, short circuit, open circuit and the like are prone to occurring.
Based on this, an embodiment of the present application provides an etching method, as shown in fig. 1B, the method includes the following steps S101 to S103:
step S101: providing a substrate, wherein the substrate at least comprises an etching layer and a first photoresist layer with a first opening, which is positioned on the etching layer;
as shown in fig. 1C, the substrate 10 is provided at least including an etch layer 101 and a first photoresist layer 102 having a first opening 103 on the etch layer 101.
Here, the etch layer refers to a layer for etching to form a target pattern, which refers to a pattern that needs to be formed in the etch layer by an etching process.
The photoresist layer refers to a layer where a photoresist is located, and the photoresist is also called a photoresist, and refers to a resist etching film material whose solubility is changed by irradiation or radiation of ultraviolet light, electron beams, ion beams, X-rays, and the like. The photoresist is sensitive to light and comprises components such as photosensitive resin, a sensitizer, a solvent and the like. Used as a corrosion-resistant coating material during a photolithography process. The first opening means an opening for forming a target pattern, and the photoresist layer having the first opening means that the photoresist layer has been subjected to exposure and development processes to form a first photoresist layer having the first opening.
In some embodiments, in order to protect the etching layer, reduce the stress effect of the etching process, and the like, a hard mask layer is formed on the etching layer, and then a first photoresist layer having a first opening is formed on the hard mask layer. Wherein, the material of the hard mask layer may include at least one of carbon, silicon nitride, titanium nitride and silicon oxide.
In some embodiments, the implementation of step S101 may include steps S1011 and S1012 as follows:
step S1011: forming the first photoresist layer on the etching layer;
here, the photoresist may be classified into a positive photoresist and a negative photoresist according to polarity, and the difference is that: the exposed areas of the negative photoresist become hard and remain after exposure and development, and the unexposed parts are dissolved by a developer; after the positive photoresist is exposed, the connected polymers in the exposed area can be broken and softened due to the photo-dissolution effect and are finally dissolved by a developer, and the unexposed part is remained.
Step S1012: and patterning the first photoresist layer to form a first photoresist layer with the first opening.
Here, patterning the first photoresist layer refers to performing an exposure and development process on the first photoresist layer, in which a portion of the first photoresist layer is dissolved away to form a first opening, thereby forming a first photoresist layer having the first opening.
Step S102: depositing a first protective layer on the side wall of the first opening to form a first photoresist layer with a second opening;
as shown in fig. 1D, a first protection layer 104 is deposited on the sidewall of the first opening 103, and a first photoresist layer 102 having a second opening 105 is formed.
Here, the material of the first protective layer may include an oxide such as zinc oxide, silicon oxide, or the like. The first protective layer may be formed by a deposition process including any one of: chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), and any other suitable Deposition process. Among them, the deposited layer formed by ALD has an extremely uniform thickness and excellent uniformity. In some embodiments, in order to deposit the first protection layer with a certain thickness and uniformity on the sidewall of the first opening, the first protection layer may be deposited by using an ALD process.
In step S102, a first photoresist layer having a second opening is formed by depositing a first protective layer on the sidewall of the first opening, which has the following effects:
in the first aspect, since the first protective layer is deposited on the sidewall of the first opening, the horizontal dimension D1 (the dimension parallel to the substrate as shown in fig. 1C) of the first opening is greater than the horizontal dimension D2 (as shown in fig. 1D) of the second opening by the thickness of the sidewall, that is, the horizontal dimension D2 of the second opening is smaller than the horizontal dimension D1 of the first opening. The target pattern is obtained by etching the second opening on the photoresist layer, so that the key size of the target pattern can be influenced by the horizontal size of the second opening, and the key size of the target pattern can be reduced by reducing the horizontal size of the second opening; and under the condition that the photoresist layer has the same opening size, the photoetching process window can be enlarged, namely the size of the first opening is increased, and the difficulty of the photoetching process is reduced. The critical dimension refers to a dimension that affects the performance of the graphic and needs to be controlled in a critical manner, and may be determined according to the shape and the generation process of the target graphic. For example, for an etching process, when the target pattern is cylindrical, the diameter of the surface circle is a critical dimension; when the target graph is a cube, the side length is the key size.
In a second aspect, the uniformity of the second opening is improved by depositing a first protective layer on the sidewalls of the first opening.
Table 1: statistical table of critical dimension, standard deviation (Sigma) and deviation (Delta CD) of the first opening and the second opening
Figure BDA0003814340750000091
Table 1 shows the critical dimensions of the first and second openings and the magnitude of the sigma value, where CD is the dimension at the bottom up to 30%. As can be seen from table 1, the CD of the second opening is reduced and the Sigma value is reduced compared to that of the first opening, so that the uniformity of the second opening is better after the first passivation layer is deposited on the sidewall of the first opening.
In some embodiments, the step S102 "depositing a first protection layer on the sidewall of the first opening to form a first photoresist layer having a second opening" may include the following steps S1021 and S1022:
step S1021: depositing an initial first protective layer on the first photoresist layer;
as shown in fig. 1E, an initial first protective layer 106 is deposited over the first photoresist layer 102.
Here, the performing of the step S1021 may form an initial first protective layer through a deposition process. The deposition process comprises any one of the following: chemical vapor deposition, physical vapor deposition, atomic layer deposition, and any other suitable deposition process. Among them, the deposited layer thickness that ALD formed is extremely even and the uniformity is extremely excellent, and the step coverage is better. In some embodiments, in order to deposit the initial first protection layer with a uniform thickness on the sidewall of the first opening, the step S1021 may be performed by depositing the initial first protection layer by using an ALD process.
In some embodiments, the initial first protective layer has a thickness in the range of 5nm to 10nm. On one hand, the thickness of the initial first protective layer cannot be too thick, and the first protective layer is not easy to form and has certain challenges for the process; on the other hand, the thickness of the first protective layer cannot be too thin initially, and the effect of reducing the critical dimension of the target pattern and improving the verticality of the second opening cannot be achieved in the later stage of being too thin. The initial first protective layer is, for example, silicon oxide. In some embodiments, the initial first protective layer may be preferentially silicon oxide due to the poor contact with the first photoresist layer 102 due to the greater stress of silicon nitride.
FIG. 1F illustrates the thickness of an initial first protective layer deposited using an ALD process. As can be seen from fig. 1F, fig. (a) and fig. (b), the initial first protective layer has a thickness of 9.346nm, 9.034nm, 9.346nm, 7.788nm, 9.034nm, 8.723nm, 8.723nm, 8.723nm, which are between 7.5 and 9.5nm and are uniformly deposited on the sidewalls and bottom of the first opening.
Step S1022: and removing the initial first protective layer positioned on the upper surface of the first photoresist layer and at the bottom of the first opening, and reserving the initial first protective layer on the side wall of the first opening to form a first photoresist layer with a second opening.
As shown in fig. 1E, the initial first protection layer 106 includes three portions, a first portion 1061 is located on the upper surface of the first photoresist layer, a second portion 1062 is located on the sidewall of the first opening, and a third portion 1063 is located at the bottom of the first opening. The initial first protection layer (i.e., the first portion 1061 of the initial first protection layer) on the upper surface of the first photoresist layer and the initial first protection layer (i.e., the third portion 1063 of the initial first protection layer) at the bottom of the first opening are removed, and the initial first protection layer (i.e., the second portion 1062 of the initial first protection layer) on the sidewall of the first opening is remained, to form the first photoresist layer 102 having the second opening 105 as shown in fig. 1D.
Here, the step S1022 may be performed by etching away the initial first protective layer on the upper surface of the first photoresist layer and at the bottom of the first opening by using a third dry etching process, wherein the third dry etching process may include a reactive ion etching technique, a plasma etching technique, a deep reactive ion etching technique, and xenon difluoride (XeF) 2 ) And isotropic etching and the like, and the type of the third dry etching process is not limited in the embodiment of the application.
In some embodiments, in order to retain the initial first protective layer of the first opening sidewall, the process parameters of the third dry etching process may include: the flow rate of trifluoromethane is in the range of 25 to 35sccm, the flow rate of helium is in the range of 90 to 110sccm, the gas pressure is in the range of 4 to 6mTorr, and the bias voltage is in the range of greater than 200V. For example, the flow rate of trifluoromethane is 30sccm, the flow rate of helium is 100sccm, the gas pressure is 5mTorr, and the bias voltage is 250V. Under the process parameters, the initial first protection layer on the side wall of the first opening can be protected while the initial first protection layer on the upper surface of the first photoresist layer and the bottom of the first opening is etched.
In the embodiment of the present application, the deposition of the first protection layer on the sidewall of the first opening is achieved by depositing the initial first protection layer on the first photoresist layer, then removing the initial first protection layer on the upper surface of the first photoresist layer and the bottom of the first opening, and retaining the initial first protection layer on the sidewall of the first opening, so as to form the first photoresist layer with the second opening.
Step S103: and etching the etching layer through the second opening to form a first target pattern in the etching layer.
As shown in fig. 1D, the etch layer 101 is etched through the second opening 105 to form a first target pattern 107 shown in fig. 1G in the etch layer 101.
In some embodiments, as shown in fig. 1H, the substrate 10 includes an etch layer 101, a hard mask layer 108 on the etch layer 101, and a first photoresist layer 102 having a second opening 105 on the hard mask layer 108. The implementation of step S103 may include: the hard mask layer 108 and the etch layer 101 are etched through the second opening 105 to form a first target pattern 107 in the etch layer 101 as shown in fig. 1H. Wherein a seventh opening 109 is formed in the hard mask layer 108.
Here, since the horizontal size of the second opening is smaller and the uniformity is better, the critical dimension of the first target pattern formed in the etch layer is also smaller and the uniformity is better by etching the etch layer through the second opening.
Table 2: statistical table of top and bottom critical dimension of seventh and eighth openings
Detecting items Seventh opening The eighth opening
TCD (Top CD) 36.5nm 28.3nm
BCD (bottom CD) 18.1nm 16.7nm
B/T (bottom CD/top CD) 0.49 0.59
Table 2 shows the top and bottom critical dimension sizes of the seventh and eighth openings. The eighth opening is an opening formed in the hard mask layer 108 by etching the hard mask layer 108 and the etching layer 101 shown in fig. 1H directly through the first opening without depositing the first protective layer on the sidewall of the first opening. That is, the seventh opening is different from the eighth opening in that: the seventh opening is an opening formed in the hard mask layer after the first protective layer is deposited on the side wall of the first opening; the eighth opening is an opening formed in the hard mask layer without depositing the first protective layer on the sidewall of the first opening. As can be seen from Table 2, the TCD and BCD of the eighth opening are reduced and the B/T is increased compared to the seventh opening, i.e. after the first passivation layer is deposited on the sidewall of the first opening, the critical dimension of the opening in the hard mask layer can be reduced and the B/T is increased, so that the sidewall of the seventh opening is more vertical. Since the seventh opening has a smaller critical dimension and is more vertical than the eighth opening, the critical dimension of the first target pattern finally formed in the etching layer can be made smaller and the verticality is better when the etching layer is continuously etched through the seventh opening.
Table 3: sigma value and deviation statistical table of first target graph critical dimension
Figure BDA0003814340750000121
Table 3 shows the Sigma values and deviations for the first target feature critical dimension. As can be seen from table 3, the solutions provided in the embodiments of the present application both have a reduced Sigma value and a reduced skew (test point 3 skew is substantially equal) compared to the related art solution (POR). For example, for test point 1, the sigma value is reduced from 1.44 to 1.06, and the deviation is reduced from 2.73 to 1.62, indicating that the first target pattern formed in the etch layer has better critical dimension uniformity.
In summary, by etching the etching layer through the second opening, the critical dimension of the first target pattern formed in the etching layer can be made smaller, and the verticality and the consistency are better.
In the embodiment of the application, firstly, a first photoresist layer which at least comprises an etching layer and is provided with a first opening is provided on the etching layer; then depositing a first protective layer on the side wall of the first opening to form a first photoresist layer with a second opening; and finally, etching the etching layer through the second opening to form a first target pattern in the etching layer. In this way, the following effects can be achieved:
in the first aspect, since the first passivation layer is deposited on the sidewall of the first opening, the horizontal dimension of the first opening is larger than the horizontal dimension of the second opening, that is, the horizontal dimension of the second opening is smaller than the horizontal dimension of the first opening, and the horizontal dimension of the second opening affects the critical dimension of the target pattern, so that the critical dimension of the first target pattern formed under the condition of the first opening with the same dimension can be reduced.
In the second aspect, since the first opening is formed by a photolithography process, and is affected by the photolithography process, the size of the first opening cannot be too small, and the size of the opening in the photoresist layer can be reduced and the process window of photolithography can be increased by depositing the first protective layer on the sidewall of the first opening.
In a third aspect, by depositing the first protective layer on the sidewall of the first opening, the verticality and the consistency of the first target pattern formed in the etching layer can be improved, and the occurrence of problems such as hole disconnection, hole disappearance, short circuit, disconnection, and the like can be reduced.
In some embodiments, after the "forming the first target pattern in the etch layer" at step S103, the method further includes the following step S104:
step S104: and forming a second target pattern in the etching layer.
Here, as the size of the semiconductor structure is continuously reduced, the density of the patterns in the semiconductor structure is higher and higher, and a single exposure cannot meet the requirement, so that the patterns need to be split into two parts and double exposure, i.e., "LELE". The first target pattern is a pattern subjected to first exposure etching, and the second target pattern is a pattern subjected to second exposure etching.
In some embodiments, the method of forming the second target pattern in the etching layer in step S104 and the method of forming the first target pattern in the etching layer may be implemented by steps S1041 to S1043 as follows:
step S1041: as shown in fig. 2A, a third photoresist layer 201 having a fifth opening 202 is formed on the etch layer 101;
step S1042: as shown in fig. 2A, a third protective layer 203 shown in fig. 2B is deposited on the sidewall of the fifth opening 202 to form a third photoresist layer 201 having a sixth opening 204;
step S1043: as shown in fig. 2B, the etch layer 101 is etched through the sixth opening 204 to form a second target pattern 205 shown in fig. 2C in the etch layer 101.
Here, after the etch layer is etched through the sixth opening, all layers above the etch layer may be removed to form the first target pattern 107 and the second target pattern 205 as shown in fig. 2C.
In the embodiment of the application, after the first target pattern is formed in the etching layer, the second target pattern can be formed in the etching layer, so that an etching method for forming two target patterns is provided for a double exposure process, and the method can be well applied to a semiconductor structure with a smaller size.
In some embodiments, before forming the first photoresist layer on the etch layer in step S1011", the method may further include: sequentially forming a first hard mask layer, an etching stop layer, an etching penetrating layer and a second hard mask layer on the etching layer;
as shown in fig. 3A, a first hard mask layer 301, an etch stop layer 302, an etch through layer 303, and a second hard mask layer 304 are sequentially formed on the etch layer 101.
Correspondingly, the implementation of step S103 "etching the etch layer through the second opening to form the first target pattern in the etch layer" may include steps S1031 and S1032a as follows:
step S1031: etching the second hard mask layer, the etching penetrating layer and the etching stopping layer through the second opening to form an etching stopping layer with a first middle pattern;
as shown in fig. 3A, the second hard mask layer 304, the etch through layer 303, and the etch stop layer 302 are etched through the second opening 105, forming the etch stop layer 302 having the first intermediate pattern 305 as shown in fig. 3B. Fig. 3B is a schematic structural diagram of removing all layers above the etch stop layer after etching the second hard mask layer 304, the etch through layer 303, and the etch stop layer 302 through the second opening 105.
Here, the second Hard Mask layer may include a Bottom Anti-reflection Coating (BARC) layer and a Spin-On Hard Mask (SOH) layer, wherein the BARC layer may function to better absorb the exposure light reaching the initial photoresist layer (the photoresist layer before the unexposed developing process), and reduce the reflection of the exposure light at the interface between the initial photoresist layer and the Spin-On Hard Mask layer after passing through the initial photoresist layer, thereby enabling the initial photoresist layer to be more uniformly exposed. The bottom antireflective layer may include a silicon oxynitride layer; the spin-on hard mask layer may include at least one of: spin-coating a silicon dioxide layer, spin-coating a silicon nitride layer, spin-coating an organic dielectric layer, and Spin-coating a Carbon layer (SOC), the embodiments of the present application do not limit the types of the bottom anti-reflection layer and the Spin-coating hard mask layer.
In some embodiments, in the implementation of step S1031, another hard mask layer may be further formed on the etching layer to reduce stress during the etching process or to enable a target pattern formed in the etching layer to meet a requirement of a size, for example, a fourth hard mask layer is formed before the first hard mask layer, and a material of the fourth hard mask layer may be silicon nitride.
The etch through layer refers to a layer that can be penetrated by an etching process, and the etch stop layer refers to a layer that can stop an etching process, wherein the etch through layer and the etch stop layer have opposite meanings. In some embodiments, the etch through layer and the etch stop layer may be etched using the same etch process conditions. In order to enable the etch penetration layer to penetrate and the etch stop layer to stop under the same etching process condition, the etching rate of the etch stop layer may be smaller than that of the etch penetration layer.
In some embodiments, the etch stop layer may have a thickness in the range of 25nm to 35nm. If the thickness of the etching stop layer is too thin, the etching stop layer is not easy to stop the etching process, and if the deposition thickness of the first protection layer has deviation in the former deposition process, the etching stop layer is easy to etch through. If the thickness of the etching stop layer is too thick, the deposition process is difficult and waste is caused. Therefore, the thickness of the etch stop layer is preferably in the range of 25nm to 35nm.
Since the thickness of the etch stop layer is in the range of 25nm to 35nm, in order to stop the etching process at the etch stop layer, in some embodiments, the depth of the first intermediate pattern in the etch stop layer may be in the range of 10nm to 30nm.
As shown in fig. 3C, which is a schematic view of the etch stop layer including the first intermediate pattern, it can be seen that the thickness of the etch stop layer 302 is 33.40nm and the depth of the first intermediate pattern in the etch stop layer 302 is 11.94nm.
Since the etching stop layer has a stopping function on the etching process, the bottom size of the first intermediate pattern can be made larger than that without the etching stop layer, thereby improving the B/T of the first intermediate pattern. And because the first target pattern is formed by the first intermediate pattern etching subsequently, the B/T of the first target pattern is improved under the condition that the B/T of the first intermediate pattern is improved.
In some embodiments, the step S1031 "etching the second hard mask layer, the etch through layer, and the etch stop layer through the second opening to form the etch stop layer with the first intermediate pattern" may include the following steps S131a and S131b:
step S131a: etching the second hard mask layer through the second opening by adopting a first dry etching process to form a second hard mask layer with a second intermediate pattern;
here, the second intermediate pattern is a pattern formed by etching away a portion of the second hard mask layer using the first dry etching process.
Because the material of the second hard mask layer may be different from the material of the etch penetrating layer and the etch stop layer, in order to facilitate control under the same etching process condition, under the same etching condition, the etching rate of the etch stop layer may be smaller than the etching rate of the etch penetrating layer, and the second hard mask layer may be etched, the first dry etching process may be used for the second hard mask layer, and the second dry etching process may be used for the etch penetrating layer and the etch stop layer, that is, the second hard mask layer, the etch penetrating layer and the etch stop layer are etched step by step. Of course, if an etching process condition is adopted, the second hard mask layer can be completely etched, and the etching rate of the etching stop layer can be smaller than that of the etching penetration layer, and an etching process condition can also be adopted, which is not limited in the embodiment of the present application.
Step S131b: and etching the etching penetrating layer and the etching stopping layer through the second intermediate pattern by adopting a second dry etching process to form the etching stopping layer with the first intermediate pattern.
Here, in the second dry etching process, the etch stop layer may have an etch rate less than that of the etch through layer so that the etching process can penetrate the etch through layer while stopping at the etch stop layer.
In some embodiments, the process parameters of the second dry etching process may include: the flow rate of carbon hexafluoride is in the range of 22 to 26sccm, the flow rate of argon is in the range of 160 to 200sccm, the flow rate of oxygen is in the range of 20 to 24sccm, the gas pressure is in the range of 13 to 17mTorr, the high frequency power is in the range of greater than 500W, the low frequency power is in the range of greater than 2000W, and the bias voltage is in the range of greater than 450V. For example: the flow rate of carbon hexafluoride was 24sccm, the flow rate of argon was 180sccm, the flow rate of oxygen was 22sccm, the gas pressure was 15mTorr, the high frequency power was 550W, the low frequency power was 2100W, and the bias voltage was 500V.
Step S1032a: and etching the first hard mask layer and the etching layer through the first middle pattern to form a first target pattern in the etching layer.
As shown in fig. 3B, the first hard mask layer 301 and the etch layer 101 are etched through the first intermediate pattern 305 to form the first target pattern 107 shown in fig. 1G in the etch layer 101.
In the embodiment of the application, before the first photoresist layer is formed on the etching layer, a first hard mask layer, an etching stop layer, an etching penetrating layer and a second hard mask layer are sequentially formed on the etching layer; etching the second hard mask layer, the etching penetrating layer and the etching stopping layer through the second opening to form an etching stopping layer with a first middle pattern; and finally, etching the first hard mask layer and the etching layer through the first middle pattern to form a first target pattern in the etching layer. In this way, the bottom size of the first intermediate pattern is larger than that of the first intermediate pattern without the etching stop layer by utilizing the stopping effect of the etching stop layer on the etching process, so that the B/T of the first intermediate pattern is improved; and because the first target pattern is formed by etching the first intermediate pattern, the B/T of the first target pattern is improved under the condition that the B/T of the first intermediate pattern is improved, so that the verticality of the first target pattern is better.
In some embodiments, step S1031 "after forming the etch stop layer having the first intermediate pattern" further includes steps S1032b and S1033b as follows:
step S1032b: forming a third intermediate pattern in the etching stop layer;
as shown in fig. 3D, a third intermediate pattern 306 is formed in the etch stop layer 302.
Here, the method of forming the third intermediate pattern in the etch stop layer in step S1032b may be the same as the method of forming the first intermediate pattern in the etch stop layer, except that all layers above the etch through layer may be removed first, and then a new hard mask layer and a photoresist layer having an opening are deposited on the etch through layer, and the third intermediate pattern is formed in the etch stop layer by opening etching. The etching through layer is remained, so that the B/T of the third intermediate pattern is improved by stopping the etching process by the etching stop layer in the process of forming the third intermediate pattern.
Also, since the thickness of the etch stop layer is in the range of 25nm to 35nm, in order to stop the etching process at the etch stop layer, in some embodiments, the depth of the third middle pattern in the etch stop layer is in the range of 10nm to 30nm.
Step S1033b: and etching the first hard mask layer and the etching layer through the first intermediate pattern to form a second target pattern in the etching layer while forming a first target pattern in the etching layer and etching the first hard mask layer and the etching layer through the third intermediate pattern.
Here, as shown in fig. 3D, step S1033b may be performed by simultaneously etching the first hard mask layer 301 and the etch layer 101 through the first intermediate pattern 305 and the third intermediate pattern 306 to form the first target pattern 107 and the second target pattern 205 in the etch layer 101 as shown in fig. 2C.
The embodiment of the application provides an etching method for forming two target patterns on an etching layer for the condition that a first hard mask layer, an etching stop layer, an etching penetrating layer and a second hard mask layer are sequentially formed on the etching layer, and the etching method can be well applied to a double exposure process. By forming the first intermediate pattern and the third intermediate pattern in the etching stop layer, the etching stop layer is used for stopping the etching process in the forming process of each target pattern, so that the B/T of the first intermediate pattern and the third intermediate pattern is improved, and the B/T of the final target pattern is improved.
In some embodiments, the step S1032b "forming a third intermediate pattern in the etch stop layer" may include:
step S13b1: sequentially forming a third hard mask layer and a second photoresist layer with a third opening on the etching penetrating layer;
as shown in fig. 3E, a third hard mask layer 309 and a second photoresist layer 307 having a third opening 308 are sequentially formed on the etch through layer 303;
here, the third hard mask layer may include a bottom anti-reflection layer and a spin-on hard mask layer, and the material of the third hard mask layer may be the same as or different from the material of the first hard mask layer.
In some embodiments, step S13b1 is preceded by: and removing all layers above the etching penetrating layer.
Removing all layers above the etch-through layer to form a new third hard mask layer and a second photoresist layer on the etch-through layer, thereby forming an opening for forming a third intermediate pattern by etching on the second photoresist layer; in addition, the etching penetrating layer is reserved, and the stopping effect of the etching stopping layer on the etching process can be utilized in the process of forming the third intermediate pattern, so that the B/T of the third intermediate pattern is improved.
Step S13b2: depositing a second protective layer on the side wall of the third opening to form a second photoresist layer with a fourth opening;
as shown in fig. 3E, a second protection layer 311 as shown in fig. 3F is deposited on the sidewalls of the third opening 308, and a second photoresist layer 307 having a fourth opening 310 is formed.
Step S13b3: and etching the third hard mask layer, the etching penetrating layer and the etching stopping layer through the fourth opening to form the third middle pattern in the etching stopping layer.
As shown in fig. 3F, the third hard mask layer 309, the etch through layer 303 and the etch stop layer 302 are etched through the fourth opening 310 to form a third intermediate pattern 306 as shown in fig. 3D in the etch stop layer 302.
In the embodiment of the application, a third hard mask layer and a second photoresist layer with a third opening are sequentially formed on the etching penetrating layer; then depositing a second protective layer on the side wall of the third opening to form a second photoresist layer with a fourth opening; and finally, etching the third hard mask layer, the etching penetrating layer and the etching stopping layer through the fourth opening, so that a third middle pattern is formed in the etching stopping layer.
The embodiment of the present application further provides an etching method, configured to form a first target pattern and a second target pattern by etching, where the first target pattern and the second target pattern are used to form a contact plug in a peripheral region in a semiconductor structure, and the contact plug is used to connect a source or a drain in a transistor in the peripheral region to a metal interconnection layer in the peripheral region, where the method includes steps S201 to S208 as follows:
step S201: sequentially forming a fourth hard mask layer, a first hard mask layer, an etching stop layer, an etching penetrating layer, a second hard mask layer and a first photoresist layer with a first opening on the etching layer;
as shown in fig. 4A, a fourth hard mask layer 401, a first hard mask layer 301, an etch stop layer 302, an etch through layer 303, a second hard mask layer 304, and a first photoresist layer 102 having a first opening 103 are sequentially formed on the etch layer 101. The etching layer 101 is a layer covering a dielectric layer of the transistor 402 in the peripheral region; the fourth hard mask layer 401 is a silicon nitride layer for making the formed first target pattern have a desired size; the etching stop layer 302 is a silicon oxynitride layer, and the etching penetration layer 303 is an oxide layer, wherein the etching rate of the etching stop layer is less than that of the etching penetration layer; the second hard mask layer 304 includes a BARC layer 3042 and a SOH layer 3041, the BARC layer is a silicon oxynitride layer, and the SOH layer is a spin-on carbon layer; the first opening is used for etching to form a first target pattern, and the first opening is formed by patterning the first photoresist layer.
Step S202: depositing a first protective layer on the side wall of the first opening to form a first photoresist layer with a second opening;
as shown in fig. 4A, a first protective layer 104 as shown in fig. 4B is deposited on the sidewall of the first opening 103, forming a first photoresist layer 102 having a second opening 105.
Step S203: etching the second hard mask layer, the etching penetrating layer and the etching stopping layer through the second opening to form an etching stopping layer with a first middle pattern;
as shown in fig. 4B, the second hard mask layer 304, the etch through layer 303, and the etch stop layer 302 are etched through the second opening 105, forming the etch stop layer 302 having the first intermediate pattern 305 as shown in fig. 4C.
Step S204: removing all layers above the etch-through layer;
all layers above etch-through layer 303 are removed to form the structure shown in figure 4C.
Step S205: sequentially forming a third hard mask layer and a second photoresist layer with a third opening on the etching penetrating layer;
as shown in fig. 4D, a third hard mask layer 309 and a second photoresist layer 307 having a third opening 308 are sequentially formed on the etch through layer 303, wherein the third hard mask layer 309 comprises a BARC layer 3092 and a SOH layer 3091.
Step S206: depositing a second protective layer on the side wall of the third opening to form a second photoresist layer with a fourth opening;
as shown in fig. 4D, a second protection layer 311 as shown in fig. 4E is deposited on the sidewalls of the third opening 308, and a second photoresist layer 307 having a fourth opening 310 is formed.
Step S207: etching the third hard mask layer, the etching penetration layer and the etching stop layer through the fourth opening to form the third intermediate pattern in the etching stop layer;
as shown in fig. 4E, the third hard mask layer 309, the etch through layer 303 and the etch stop layer 302 are etched through the fourth opening 310, and a third intermediate pattern 306 as shown in fig. 4F is formed in the etch stop layer 302, where fig. 4F is the structure obtained after removing all layers above the etch stop layer 302.
Step S208: and etching the first hard mask layer, the fourth hard mask layer and the etching layer through the first middle pattern to form a first target pattern in the etching layer, and simultaneously etching the first hard mask layer, the fourth hard mask layer and the etching layer through the third middle pattern to form a second target pattern in the etching layer.
As shown in fig. 4F, the first hard mask layer 301, the fourth hard mask layer 401, and the etch layer 101 are etched at the same time through the first intermediate pattern 305 and the third intermediate pattern 306, and the first target pattern 107 and the second target pattern 205 shown in fig. 4G are formed in the etch layer 101.
Here, in the case where the first target pattern and the second target pattern are used to form a contact plug of a peripheral region in the semiconductor structure, an insulating layer, a buffer layer, and a conductive layer may be deposited on inner walls of both the first target pattern and the second target pattern to form the contact plug of the peripheral region. One end of the contact plug is connected with the source electrode or the drain electrode of the transistor in the peripheral area, and the other end of the contact plug is connected with the metal interconnection layer in the peripheral area, so that signal transmission can be realized, and logic operation can be carried out.
Embodiments of the present application also provide a semiconductor structure formed by the method of any of the above embodiments.
The semiconductor structure provided by the embodiment of the present application is similar to the method for forming the semiconductor structure provided by the above embodiment, and for technical features not disclosed in detail in the embodiment of the present application, please refer to the above embodiment for understanding, and details are not described herein again.
In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in a non-target manner. The above-described device embodiments are merely illustrative, for example, the division of the unit is only a logical functional division, and there may be other division ways in actual implementation, such as: multiple units or components may be combined, or may be integrated into another system, or some features may be omitted, or not implemented. Additionally, the various components shown or discussed are coupled or directly coupled to each other.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed on a plurality of network units; some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment. The features disclosed in the several method or apparatus embodiments provided in this disclosure may be combined in any combination to arrive at a new method or apparatus embodiment without conflict.
The above descriptions are only some embodiments of the disclosed embodiments, but the scope of the disclosed embodiments is not limited thereto, and any person skilled in the art can easily think of the changes or substitutions within the technical scope of the disclosed embodiments, and all those are covered by the scope of the disclosed embodiments. Therefore, the protection scope of the embodiments of the present application shall be subject to the protection scope of the claims.

Claims (15)

1. An etching method, comprising:
providing a substrate, wherein the substrate at least comprises an etching layer and a first photoresist layer with a first opening, which is positioned on the etching layer;
depositing a first protective layer on the side wall of the first opening to form a first photoresist layer with a second opening;
and etching the etching layer through the second opening to form a first target pattern in the etching layer.
2. The etching method according to claim 1, wherein depositing a first protection layer on a sidewall of the first opening to form a first photoresist layer having a second opening comprises:
depositing an initial first protective layer on the first photoresist layer;
and removing the initial first protective layer positioned on the upper surface of the first photoresist layer and at the bottom of the first opening, and reserving the initial first protective layer on the side wall of the first opening to form a first photoresist layer with a second opening.
3. The etching method according to claim 2, wherein the providing a substrate comprises:
forming the first photoresist layer on the etching layer;
and patterning the first photoresist layer to form a first photoresist layer with the first opening.
4. The etching method according to claim 3, further comprising, before forming the first photoresist layer on the etch layer:
sequentially forming a first hard mask layer, an etching stop layer, an etching penetrating layer and a second hard mask layer on the etching layer;
correspondingly, the etching layer through the second opening to form a first target pattern in the etching layer includes:
etching the second hard mask layer, the etching penetrating layer and the etching stopping layer through the second opening to form an etching stopping layer with a first middle pattern;
and etching the first hard mask layer and the etching layer through the first middle pattern to form the first target pattern in the etching layer.
5. The etching method according to claim 4, wherein the etching the second hard mask layer, the etch through layer, and the etch stop layer through the second opening to form the etch stop layer having the first intermediate pattern comprises:
etching the second hard mask layer through the second opening by adopting a first dry etching process to form a second hard mask layer with a second middle pattern;
and etching the etching penetrating layer and the etching stopping layer through the second intermediate pattern by adopting a second dry etching process to form the etching stopping layer with the first intermediate pattern.
6. The etching method according to claim 5, wherein the process parameters of the second dry etching process comprise: the flow rate of carbon hexafluoride is in the range of 22 to 26sccm, the flow rate of argon is in the range of 160 to 200sccm, the flow rate of oxygen is in the range of 20 to 24sccm, the gas pressure is in the range of 13 to 17mTorr, the high frequency power is in the range of greater than 500W, the low frequency power is in the range of greater than 2000W, and the bias voltage is in the range of greater than 450V.
7. The etching method according to any one of claims 4 to 6, further comprising, after forming the etch stop layer having the first intermediate pattern:
forming a third intermediate pattern in the etch stop layer;
and etching the first hard mask layer and the etching layer through the first intermediate pattern to form a second target pattern in the etching layer while forming a first target pattern in the etching layer and etching the first hard mask layer and the etching layer through the third intermediate pattern.
8. The etching method according to claim 7, wherein forming a third intermediate pattern in the etch stop layer comprises:
sequentially forming a third hard mask layer and a second photoresist layer with a third opening on the etching penetrating layer;
depositing a second protective layer on the side wall of the third opening to form a second photoresist layer with a fourth opening;
and etching the third hard mask layer, the etching penetrating layer and the etching stopping layer through the fourth opening to form the third middle pattern in the etching stopping layer.
9. The etching method according to claim 8, wherein before sequentially forming a third hard mask layer and a second photoresist layer having a third opening on the etch penetration layer, the method further comprises:
and removing all layers above the etching penetrating layer.
10. The etching method according to any one of claims 4 to 6, 8 and 9, wherein the etching rate of the etching stop layer is smaller than that of the etching penetration layer under the same etching condition.
11. The etching method according to claim 2,
etching the initial first protective layer on the upper surface of the first photoresist layer and the bottom of the first opening by adopting a third dry etching process, and reserving the initial first protective layer on the side wall of the first opening to form a first photoresist layer with a second opening;
wherein, the process parameters of the third dry etching process comprise: the flow rate of trifluoromethane is in the range of 25 to 35sccm, the flow rate of helium is in the range of 90 to 110sccm, the gas pressure is in the range of 4 to 6mTorr, and the bias voltage is in the range of greater than 200V.
12. The etching method according to any one of claims 4 to 6, 8 and 9, wherein the material of the first protective layer and the etch-through layer comprises an oxide, and the material of the etch stop layer comprises silicon oxynitride.
13. The etching method according to claim 7, wherein the depth range of the first intermediate pattern and the third intermediate pattern in the etching stop layer is 10nm to 30nm, and the thickness range of the etching stop layer is 25nm to 35nm;
depositing the initial first protective layer by an atomic vapor deposition process, wherein the thickness of the initial first protective layer ranges from 5nm to 10nm.
14. The etching method according to any one of claims 1, 2, 4 to 6, 8 and 9, wherein the first target pattern is used for forming a contact plug of a peripheral region in a semiconductor structure, and the contact plug is used for connecting a source or a drain in a transistor of the peripheral region with a metal interconnection layer of the peripheral region.
15. A semiconductor structure prepared by the etching method according to any one of claims 1 to 14.
CN202211021853.4A 2022-08-24 2022-08-24 Etching method and semiconductor structure Pending CN115346869A (en)

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