CN115333516A

CN115333516A - POR circuit

Info

Publication number: CN115333516A
Application number: CN202210987402.XA
Authority: CN
Inventors: 李国勇; 霍俊杰; 郭增良
Original assignee: Ziguang Tongxin Microelectronics Co Ltd
Current assignee: Ziguang Tongxin Microelectronics Co Ltd
Priority date: 2022-08-17
Filing date: 2022-08-17
Publication date: 2022-11-11

Abstract

The application discloses POR circuit, this POR circuit includes: the starting unit, the trigger unit, the first inverter unit, the delay unit and the second inverter unit are sequentially connected; the input end of the starting unit is connected with a power supply VCC, and the output end of the second phase inverter unit is connected with the digital module; the starting unit is used for controlling the opening of the POR circuit; the trigger unit is used for outputting equivalent voltage of VCC input voltage of a power supply; the first inverter unit is used for inverting the equivalent voltage to generate a first voltage; the time delay unit is used for charging by using the current input by the current generation circuit controlled by the current mirror, so as to control the power-on time of the POR circuit and turn over the first voltage to generate a second voltage; the second inverter unit is used for continuously inverting the second voltage to generate and output a third voltage. The traditional RC charge-discharge delay module is changed into a charge-discharge delay module controlled by a loading current mirror, so that the areas of capacitors and resistors of the RC charge-discharge part are reduced, and the area of the POR circuit is smaller.

Description

POR circuit

Technical Field

The application relates to the technical field of circuit testing, in particular to a POR circuit.

Background

With the rapid development of science and technology, more and more electronic products appear in the life of people. There are many different circuit systems in different electronic products, and there are many different component circuits in different circuit systems.

A power on reset circuit (POR circuit for short) is widely used in power supply systems. The power-on reset circuit is used for starting the single chip microcomputer to start working in the control system. However, when the power supply is powered on and the voltage is abnormal or disturbed during normal operation, the power supply may have some unstable factors, which may bring serious influence to the stability of the operation of the single chip microcomputer. Therefore, the reset signal is output to the chip when the power supply is powered on and delayed. In order to meet the market demand, POR circuits are gradually developed toward small area, low power consumption and high stability. The power-on delay module of the conventional POR circuit is usually realized by charging an RC (resistor-capacitor) of a capacitor resistor, and the area of the POR circuit is increased due to the introduction of a larger capacitor and resistor.

Therefore, how to make the area of the POR circuit smaller is a problem that needs to be solved urgently by those skilled in the art.

Disclosure of Invention

The embodiment of the application provides a POR circuit, and the POR circuit that utilizes the charge-discharge time delay module of loading current mirror control to realize detecting the voltage that voltage generation circuit produced and reduce the area of traditional RC partial capacitance of charge-discharge and resistance part to POR circuit's too big problem in the area among the prior art has been solved.

In order to solve the above technical problem, the present application discloses a POR circuit, including:

the starting unit, the trigger unit, the first inverter unit, the delay unit and the second inverter unit are sequentially connected;

the input end of the starting unit is connected with a power supply VCC, and the output end of the second inverter unit is connected with the digital module;

the starting unit is used for receiving an input voltage of a power supply VCC and starting the POR circuit when the input voltage reaches a starting threshold value;

the trigger unit is used for responding to a signal sent by the starting unit for starting the POR circuit and outputting equivalent voltage of the input voltage of the power supply VCC;

the first inverter unit is used for receiving the equivalent voltage output by the trigger unit; the equivalent voltage is turned over to generate a first voltage, and the first voltage is output;

the time delay unit is used for charging by using the current input by the current generation circuit controlled by the current mirror; receiving the first voltage and turning over when the accumulated charge reaches a set threshold value, generating a second voltage and outputting the second voltage;

and the second inverter unit is used for receiving the second voltage, continuously inverting the second voltage, generating a third voltage and outputting the third voltage.

Optionally, the starting unit includes:

the NMOS transistor comprises a first resistor, a second resistor, a first NMOS transistor, a second NMOS transistor and a third NMOS transistor;

one end of the second resistor is connected with the drain electrode of the first NMOS tube, and the other end of the second resistor is connected with the power supply VCC;

the source electrode of the first NMOS tube is connected with the drain electrode of the second NMOS tube;

the source electrode of the second NMOS tube is connected with the drain electrode of the third NMOS tube;

the source electrode of the third NMOS tube is grounded;

the grids of the first NMOS transistor to the third NMOS transistor are connected with the first resistor and are connected to the power supply VCC; the first resistor is used for protecting the first NMOS tube to the third NMOS tube.

Optionally, the trigger unit is a schmitt trigger unit.

Optionally, the trigger unit includes:

the first PMOS tube, the second PMOS tube, the third PMOS tube, the fourth NMOS tube and the third resistor are connected in series;

the source electrode of the first PMOS tube is connected with a power supply VCC, and the drain electrode of the first PMOS tube is connected with the source electrode of the second PMOS tube;

the drain electrode of the second PMOS tube is connected with the drain electrode of the fourth NMOS tube;

the source electrode of the fourth NMOS tube is grounded;

the third resistor is connected with the drain electrode of the third PMOS tube;

the source electrode of the third PMOS tube is connected with the drain electrode of the first PMOS tube and the source electrode of the second PMOS tube, and the grid electrode of the third PMOS tube is connected with the drain electrode of the second PMOS tube and the drain electrode of the fourth NMOS tube;

the grid electrodes of the first PMOS tube, the second PMOS tube and the fourth NMOS tube are connected with the drain electrode of the first NMOS tube of the starting unit.

Optionally, the first inverter unit includes:

a fourth PMOS tube and a fifth NMOS tube;

the source electrode of the fourth PMOS tube is connected with the power supply VCC, and the drain electrode of the fourth PMOS tube is connected with the fifth NMOS tube;

the source electrode of the fifth NMOS tube is grounded;

and the grid electrode of the fourth PMOS tube is connected with the grid electrode of the fifth NMOS tube and is connected to the drain electrode of the fourth NMOS tube of the trigger unit.

Optionally, the delay unit includes:

a fifth PMOS tube, a sixth NMOS tube and a first capacitor;

the source electrode of the fifth PMOS tube is connected with a current generation circuit controlled by the current mirror;

the drain electrode of the sixth NMOS tube is connected with the drain electrode of the fifth PMOS tube, and the source electrode of the sixth NMOS tube is grounded;

one end of the first capacitor is connected with the drain electrode of the sixth NMOS tube, and the other end of the first capacitor is grounded;

and the grid electrode of the fifth PMOS tube is connected with the grid electrode of the sixth NMOS tube and is connected to the drain electrode of the fifth NMOS tube of the first phase inverter unit.

Optionally, the second inverter unit includes:

a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube and a tenth NMOS tube;

the sixth PMOS tube and the seventh NMOS tube form a first phase inverter;

a source electrode of the sixth PMOS tube is connected to a power supply VCC;

the drain electrode of the seventh NMOS tube is connected with the drain electrode of the sixth PMOS tube, and the source electrode of the seventh NMOS tube is grounded;

the grid electrodes of the sixth PMOS tube and the seventh NMOS tube are connected and connected to the drain electrode of the sixth NMOS tube of the delay unit;

the seventh PMOS tube and the eighth NMOS tube form a second phase inverter;

a source electrode of the seventh PMOS tube is connected to a power supply VCC;

the drain electrode of the eighth NMOS tube is connected with the drain electrode of the seventh PMOS tube, and the source electrode of the eighth NMOS tube is grounded;

the grid electrodes of the eighth NMOS tube and the seventh PMOS tube are connected and connected to the drain electrode of the seventh NMOS tube;

the eighth PMOS tube and the ninth NMOS tube form a third phase inverter;

a source electrode of the eighth PMOS tube is connected to a power supply VCC;

the drain electrode of the ninth NMOS tube is connected with the drain electrode of the eighth PMOS tube, and the source electrode of the ninth NMOS tube is grounded;

the grid electrodes of the ninth NMOS tube and the eighth PMOS tube are connected and connected to the drain electrode of the eighth NMOS tube;

the ninth PMOS tube and the tenth NMOS tube form a fourth phase inverter;

a source electrode of the ninth PMOS tube is connected to a power supply VCC;

the drain electrode of the tenth NMOS tube is connected with the drain electrode of the ninth PMOS tube and is connected into the digital module, and the source electrode of the tenth NMOS tube is grounded;

and the grid electrodes of the tenth NMOS tube and the ninth PMOS tube are connected with the drain electrode of the ninth NMOS tube.

Optionally, the current mirror controlled current generating circuit includes:

a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, a fourteenth PMOS transistor, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, and a fourth resistor;

the source electrode of the tenth PMOS tube is connected with a power supply VCC, and the drain electrode of the tenth PMOS tube is connected with one end of the fourth resistor;

the other end of the fourth resistor is connected with one end of the first switch;

the other end of the first switch is connected with the current mirror;

the source electrodes of the eleventh PMOS tube, the twelfth PMOS tube, the thirteenth PMOS tube and the fourteenth PMOS tube are connected with the power supply VCC, and the drain electrodes are respectively connected with the second switch, the third switch, the fourth switch and the fifth switch and are connected to the source electrode of the fifth PMOS tube of the delay unit;

and the grids of the eleventh PMOS tube, the twelfth PMOS tube, the thirteenth PMOS tube and the fourteenth PMOS tube are connected with and connected to the connection end of the fourth resistor and the first switch.

Optionally, the POR circuit further includes:

a fifteenth PMOS tube;

a source electrode of the fifteenth PMOS tube is connected to a power supply VCC;

the drain electrode of the fifteenth PMOS tube is connected with the drain electrode of the sixth NMOS tube of the delay unit;

the grid electrode of the fifteenth PMOS tube is connected with the grid electrodes of the seventh PMOS tube and the eighth NMOS tube of the second phase inverter.

According to the technical scheme, the embodiment of the application has the following advantages:

in the embodiments of the present application, it may be determined that the present application provides a POR circuit formed by sequentially connecting a start unit, a flip-flop unit, a first inverter unit, a delay unit, and a second inverter unit. The input end of the starting unit is connected with a power supply VCC, and the output end of the second phase inverter unit is connected with the digital module. When the input voltage of the power supply VCC received by the starting unit reaches a starting threshold value, the POR is started, then the trigger unit circuit responds to a signal sent by the starting unit for starting the POR circuit, the equivalent voltage of the input voltage of the power supply VCC is output to the first inverter unit and is overturned to generate a first voltage, and the first voltage is sent to the delay unit. And then the charge-discharge time delay unit controlled by the loading current mirror charges by using the current input by the current generation circuit controlled by the current mirror, and receives and overturns the first voltage when the accumulated charge reaches a set threshold value to generate a second voltage. And then the time delay module sends the generated second voltage to the second inverter unit, so that the second inverter unit continuously overturns the second voltage to generate a third voltage, and finally the third voltage is output. Because the traditional RC charge-discharge time delay module is changed into a charge-discharge time delay unit controlled by a loading current mirror, the area of a capacitor and a resistor of an RC charge-discharge part is reduced, and the area of the POR circuit is smaller.

Drawings

Fig. 1 is a block diagram of a POR circuit disclosed in an embodiment of the present application;

fig. 2 is a circuit structure diagram of a starting unit according to an embodiment of the disclosure;

fig. 3 is a circuit structure of a flip-flop unit according to an embodiment of the present application;

fig. 4 is a circuit structure diagram of a first inverter unit according to an embodiment of the present disclosure;

fig. 5 is a circuit structure diagram of a delay unit according to an embodiment of the present application;

fig. 6 is a circuit structure diagram of a second inverter unit according to an embodiment of the disclosure;

FIG. 7 is a schematic diagram of a current mirror controlled current generating circuit according to an embodiment of the present disclosure;

fig. 8 is a circuit structure diagram of a POR circuit disclosed in the embodiment of the present application;

fig. 9 is a block diagram of an application scenario structure of a POR circuit disclosed in the embodiment of the present application.

Detailed Description

As mentioned above, the power-on delay block of the POR circuit in the prior art usually occupies a large area. Particularly, in the prior art, the power-on delay module of the POR circuit is usually realized by charging the RC of the capacitor resistor, and as the RC charging and discharging delay module is used and a large capacitor and resistor are introduced, the occupied area of the POR circuit is too large, so that the requirement of the market on the POR circuit with a small area cannot be met.

In order to solve the above problems, the present application provides a POR circuit including: the starting unit, the trigger unit, the first inverter unit, the delay unit and the second inverter unit are sequentially connected. The input end of the starting unit is connected with a power supply VCC, and the output end of the second phase inverter unit is connected with the digital module. When the input voltage of the power supply VCC received by the starting unit reaches a starting threshold value, the POR is started, then the trigger unit circuit responds to a signal sent by the starting unit for starting the POR circuit, the equivalent voltage of the input voltage of the power supply VCC is output to the first inverter unit and is overturned to generate a first voltage, and the first voltage is sent to the delay module. And then the charge-discharge time delay module controlled by the loading current mirror charges by using the current input by the current generation circuit controlled by the current mirror, and receives and overturns the first voltage when the accumulated charge reaches a set threshold value to generate a second voltage. And then the time delay module sends the generated second voltage to the second inverter unit, so that the second inverter unit continuously overturns the second voltage to generate a third voltage, and finally the third voltage is output.

Therefore, the traditional RC charge-discharge time delay module is changed into a charge-discharge time delay module controlled by a loading current mirror, and the area of the capacitor and the resistor of the RC charge-discharge part is reduced, so that the area of the POR circuit is smaller.

It should be noted that the POR circuit provided in the present application can be widely applied to various system chips.

In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Fig. 1 is a block diagram of a POR circuit disclosed in an embodiment of the present application, including:

the circuit comprises a starting unit (101), a trigger unit (102), a first inverter unit (103), a delay unit (104) and a second inverter unit (105);

the trigger unit is used for responding to a signal sent by the starting unit for starting the POR circuit and outputting equivalent voltage of the input voltage of the power VCC;

the time delay unit is used for charging by using the current input by the current generation circuit controlled by the current mirror; receiving the first voltage and overturning when the accumulated charge reaches a set threshold value, generating a second voltage and outputting the second voltage;

In practical application, the starting unit, the trigger unit, the first inverter unit, the delay unit and the second inverter unit are sequentially connected to form a POR circuit, the input end of the starting unit is connected with a power VCC and is responsible for receiving an input voltage VCC, when the received input voltage of the power VCC reaches a starting threshold value, a POR is started, then the trigger unit circuit responds to a signal sent by the starting unit to start the POR circuit, the equivalent voltage of the input voltage of the power VCC is output to the first inverter unit and is overturned to generate a first voltage, and the first voltage is sent to the delay unit. And then the charge-discharge time delay module controlled by the loading current mirror charges by using the current input by the current generation circuit controlled by the current mirror, and receives and overturns the first voltage when the accumulated charge reaches a set threshold value to generate a second voltage. And then the time delay module sends the generated second voltage to the second inverter unit, so that the second inverter unit continuously overturns the second voltage to generate a third voltage, and finally the third voltage is output. Wherein a current mirror is a circuit block whose function is to generate a copy of the current flowing into or out of an input terminal by copying the current in an output terminal. The current mirror is characterized in that the input and output current is kept constant, and when a power supply system or a voltage to be detected is electrified slowly and exceeds the power-on delay of the POR circuit, the power-on time of the POR circuit can be reduced by controlling the switch of the current mirror and reducing the input current. Because the traditional RC charge-discharge time delay module is changed into a charge-discharge time delay unit controlled by a loading current mirror, the area of a capacitor and a resistor of an RC charge-discharge part is reduced, and the area of the POR circuit is smaller.

Fig. 2 is a structural diagram of a circuit with a starting unit disclosed in an embodiment of the present application, specifically, the starting unit includes:

the NMOS transistor comprises a first resistor (R1), a second resistor (R2), a first NMOS transistor (MN 1), a second NMOS transistor (MN 2) and a third NMOS transistor (MN 3);

the source electrode of the third NMOS tube is grounded;

In practical application, the magnitude of the input voltage of the power supply VCC determines whether the NMOS transistors MN1, MN2, and MN3 are turned on or off. In the process of fast power-up of the power supply VCC, the MN1, MN2, MN3 are initially in a disconnected state, and the POR circuit is not activated. The node voltage between MN1 and R2 at this time is equal to the input voltage of the power supply VCC at this time. When the input voltage reaches the opening threshold values of the NMOS tubes MN1, MN2 and MN3, the POR circuit is started, wherein the NMOS tubes MN1, MN2 and MN3 are conducted, and at the moment, the voltage difference occurs because the node voltage between the NMOS tubes MN1 and R2 is not equal to the input voltage due to the partial pressure of the NMOS tubes. In order to protect the NMOS transistors MN1, MN2, and MN3, a resistor R1 is connected to the gates of the NMOS transistors MN1, MN2, and MN3 for protection.

As an embodiment, the trigger unit in this application is specifically a schmitt trigger unit for different trigger units in different systems.

In practical application, for a standard schmitt trigger, when the input voltage is higher than the forward threshold voltage, the output is high; when the input voltage is lower than the negative threshold voltage, the output is low; when the input is between the positive and negative threshold voltages, the output does not change.

Fig. 3 is a circuit structure diagram of a flip-flop unit disclosed in an embodiment of the present application, specifically, the flip-flop unit includes:

a first PMOS (P-channel metal oxide semiconductor) tube (MP 1), a second PMOS tube (MP 2), a third PMOS tube (MP 3), a fourth NMOS tube (MN 4) and a third resistor (R3);

the source electrode of the fourth NMOS tube is grounded;

In practical application, after the NMOS transistors MN1, MN2, and MN3 are turned on, when a difference between a voltage of a node between MN1 and R2 and an input voltage of the power source VCC reaches a threshold of MP1 or MP2, the schmitt trigger unit is turned on. At this time, MP1 and MP2 pull the drain voltage of MN4 from 0 to the same level as the input voltage of the power supply VCC, i.e., to a high level, generate an equivalent voltage equal to the input voltage, and output it to the next cell. The Schmitt trigger unit with the structure can also play a role of a hysteresis voltage. For example, the turn-on threshold of a flip-flop unit is 10mA, when the input voltage fluctuates between 9-11mA, a glitch occurs, which causes the flip-flop to be turned on and off repeatedly and affects normal use, and the schmitt trigger unit with the structure has different threshold voltages when the voltage output by the power VCC fluctuates, that is, the output is turned from a high potential to a low potential, or from the low potential to the high potential. The output will change only if the input voltage changes sufficiently. This dual threshold action is known as hysteresis, indicating that the schmitt trigger has memory.

Fig. 4 is a circuit structure diagram of a first inverter unit disclosed in an embodiment of the present application, specifically, the first inverter unit includes:

a fourth PMOS (MP 4) tube and a fifth NMOS (MN 5) tube;

the source electrode of the fifth NMOS tube is grounded;

In practical applications, the inverter may flip the phase of the input signal by 180 degrees, that is, when the input signal is at a high level, the output signal of the inverter is at a low level; when the input signal is at a low voltage, the output signal of the inverter is at a high potential.

Fig. 5 is a circuit structure diagram of a delay unit disclosed in an embodiment of the present application, specifically, the delay unit includes:

a fifth PMOS tube (MP 5), a sixth NMOS tube (MN 6) and a first capacitor (C1);

In practical applications, when the gate voltage of the PMOS transistor is at a low level, the PMOS transistor is turned on, and at this time, the MP5 charges the capacitor C1 with the current input by the current generating circuit controlled by the current mirror. When the capacitor C1 is fully charged, the input signal is inverted, and the low level is inverted to the high level, so that a delay effect is achieved.

Fig. 6 is a circuit structure diagram of a second inverter unit according to an embodiment of the present application, specifically, the second inverter unit includes:

a sixth PMOS transistor (MP 6), a seventh PMOS transistor (MP 7), an eighth PMOS transistor (MP 8), a ninth PMOS transistor (MP 9), a seventh NMOS transistor (MN 7), an eighth NMOS transistor (MN 8), a ninth NMOS transistor (MN 9), and a tenth NMOS transistor (MN 10);

the sixth PMOS tube and the seventh NMOS tube form a first phase inverter;

a source electrode of the sixth PMOS tube is connected to a power supply VCC;

the seventh PMOS tube and the eighth NMOS tube form a second phase inverter;

a source electrode of the seventh PMOS tube is connected to a power supply VCC;

the eighth PMOS tube and the ninth NMOS tube form a third phase inverter;

a source electrode of the eighth PMOS tube is connected to a power supply VCC;

the grid electrode of the ninth NMOS tube is connected with the grid electrode of the eighth PMOS tube and is connected to the drain electrode of the eighth NMOS tube;

the ninth PMOS tube and the tenth NMOS tube form a fourth phase inverter;

a source electrode of the ninth PMOS tube is connected to a power supply VCC;

In practical applications, since the input signal to the second inverter unit may have a ripple, the input signal may be inverted in a structure in which a plurality of inverters are connected in order to make the ripple smaller or disappear. In the present application, the first inverter inverts an input signal by 180 degrees and then outputs it to the second inverter. The second inverter inverts the received signal by 180 degrees again and outputs the inverted signal to the third inverter. The third inverter inverts the received signal by 180 degrees again and outputs the inverted signal to the fourth inverter, and finally the fourth inverter inverts the received signal by 180 degrees again and outputs the inverted signal.

Fig. 7 is a current mirror controlled current generating circuit disclosed in an embodiment of the present application, and specifically, the current mirror controlled current generating circuit includes:

a tenth PMOS (P-channel metal oxide semiconductor) tube (MP 10), an eleventh PMOS tube (MP 11), a twelfth PMOS tube (MP 12), a thirteenth PMOS tube (MP 13), a fourteenth PMOS tube (MP 14), a first switch (S1), a second switch (S2), a third switch (S3), a fourth switch (S4), a fifth switch (S5) and a fourth resistor (R4);

a source electrode of the tenth PMOS tube is connected with a power supply VCC, and a drain electrode of the tenth PMOS tube is connected with one end of the fourth resistor;

the other end of the first switch is connected with the current mirror;

In practical application, the current mirror can keep the input and output currents constant, and the area of the current mirror is far smaller than that of the capacitor and the resistor in the traditional RC delay module. When the power-on delay of the power supply system exceeds the power-on delay of the POR circuit, the magnitude of the input current of the current generation circuit can be adjusted through the gear to adjust the delay, and when the function of the power supply system is completely established, high level voltage is output. For example, when the power system or the voltage to be detected is powered on slowly and exceeds the power-on delay of the POR circuit, the power-on time of the POR circuit can be reduced by controlling the switch of the current mirror and reducing the TRIM current.

Fig. 8 is a circuit structure diagram of a POR circuit disclosed in the embodiment of the present application, in order to stabilize the second voltage output by the delay unit, specifically, the POR circuit further includes:

a fifteenth PMOS transistor (MP 15);

In practical applications, since the second voltage output by the delay unit is not stable and the first glitch may be generated, a PMOS transistor MP15 may be connected to the rear of the delay circuit, so that the second voltage can be stably output.

Fig. 9 is a structural block diagram of an application scenario of a POR circuit disclosed in the embodiment of the present application, and the POR circuit provided by the present invention receives an output voltage of a voltage generation circuit (e.g., LDO), and when a voltage of the voltage generation circuit has a large glitch to affect normal operation of the circuit, the POR circuit needs to generate a low level reset signal and send the low level reset signal to a digital module to tell that a system voltage is abnormal and needs to stop operation.

In summary, it is determined that the present application provides a POR circuit, which is formed by sequentially connecting a start unit, a flip-flop unit, a first inverter unit, a delay unit, and a second inverter unit. The input end of the starting unit is connected with a power supply VCC, and the output end of the second phase inverter unit is connected with the digital module. When the input voltage of the power supply VCC received by the starting unit reaches a starting threshold value, the POR is started, then the trigger unit circuit responds to a signal sent by the starting unit for starting the POR circuit, the equivalent voltage of the input voltage of the power supply VCC is output to the first inverter unit and is overturned to generate a first voltage, and the first voltage is sent to the delay module. And then the charge-discharge time delay module controlled by the loading current mirror charges by using the current input by the current generation circuit controlled by the current mirror, and receives the first voltage and turns over the first voltage to generate a second voltage when the accumulated charge reaches a set threshold value. And then the time delay module sends the generated second voltage to the second inverter unit, so that the second inverter unit continuously inverts the second voltage to generate a third voltage, and finally the third voltage is output. Because the traditional RC charge-discharge time delay module is changed into the charge-discharge time delay module controlled by the loading current mirror, the areas of capacitors and resistors of the RC charge-discharge part are reduced, and the area of the POR circuit is smaller.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A POR circuit, comprising:

the input end of the starting unit is connected with a power supply VCC, and the output end of the second phase inverter unit is connected with the digital module;

2. The POR circuit according to claim 1, wherein the start-up unit comprises: the NMOS transistor comprises a first resistor, a second resistor, a first NMOS transistor, a second NMOS transistor and a third NMOS transistor;

the source electrode of the third NMOS tube is grounded;

3. The POR circuit according to claim 1, wherein the flip-flop cell is a schmitt trigger cell.

4. The POR circuit according to claim 3, wherein the flip-flop cell comprises: the first PMOS tube, the second PMOS tube, the third PMOS tube, the fourth NMOS tube and the third resistor are connected in series;

the source electrode of the fourth NMOS tube is grounded;

5. The POR circuit according to claim 1, wherein the first inverter unit comprises: a fourth PMOS tube and a fifth NMOS tube;

the source electrode of the fifth NMOS tube is grounded;

6. The POR circuit according to claim 1, wherein the delay unit comprises: a fifth PMOS tube, a sixth NMOS tube and a first capacitor;

7. The POR circuit according to claim 1, wherein the second inverter unit comprises: a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube and a tenth NMOS tube;

the sixth PMOS tube and the seventh NMOS tube form a first phase inverter;

a source electrode of the sixth PMOS tube is connected to a power supply VCC;

the seventh PMOS tube and the eighth NMOS tube form a second phase inverter;

a source electrode of the seventh PMOS tube is connected to a power supply VCC;

the grid electrodes of the eighth NMOS tube and the seventh PMOS tube are connected and are connected to the drain electrode of the seventh NMOS tube;

the eighth PMOS tube and the ninth NMOS tube form a third phase inverter;

a source electrode of the eighth PMOS tube is connected to a power supply VCC;

the ninth PMOS tube and the tenth NMOS tube form a fourth phase inverter;

a source electrode of the ninth PMOS tube is connected to a power supply VCC;

8. The POR circuit according to claim 6, wherein the current mirror controlled current generating circuit comprises: a tenth PMOS tube, an eleventh PMOS tube, a twelfth PMOS tube, a thirteenth PMOS tube, a fourteenth PMOS tube, a first switch, a second switch, a third switch, a fourth switch, a fifth switch and a fourth resistor;

the other end of the first switch is connected with the current mirror;

9. The POR circuit according to claim 1, wherein said POR circuit further comprises: a fifteenth PMOS tube;