CN115332430A - LED chip structure and preparation method - Google Patents
LED chip structure and preparation method Download PDFInfo
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- CN115332430A CN115332430A CN202211000763.7A CN202211000763A CN115332430A CN 115332430 A CN115332430 A CN 115332430A CN 202211000763 A CN202211000763 A CN 202211000763A CN 115332430 A CN115332430 A CN 115332430A
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- 238000002360 preparation method Methods 0.000 title abstract description 19
- 238000000034 method Methods 0.000 claims abstract description 25
- 238000004519 manufacturing process Methods 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims description 24
- 229920002120 photoresistant polymer Polymers 0.000 claims description 22
- 238000005530 etching Methods 0.000 claims description 18
- 239000010949 copper Substances 0.000 claims description 13
- 239000010408 film Substances 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 8
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 238000001259 photo etching Methods 0.000 claims description 6
- 239000010409 thin film Substances 0.000 claims description 5
- 238000009713 electroplating Methods 0.000 claims description 4
- 239000004642 Polyimide Substances 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 230000007797 corrosion Effects 0.000 claims description 3
- 238000005260 corrosion Methods 0.000 claims description 3
- 238000005516 engineering process Methods 0.000 claims description 3
- 229920001721 polyimide Polymers 0.000 claims description 3
- 239000011347 resin Substances 0.000 claims description 3
- 229920005989 resin Polymers 0.000 claims description 3
- 238000007788 roughening Methods 0.000 claims description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 2
- 238000007747 plating Methods 0.000 claims description 2
- 229910002601 GaN Inorganic materials 0.000 description 19
- 229910052594 sapphire Inorganic materials 0.000 description 15
- 239000010980 sapphire Substances 0.000 description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 238000010586 diagram Methods 0.000 description 7
- 239000003292 glue Substances 0.000 description 7
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 239000013078 crystal Substances 0.000 description 2
- 230000005496 eutectics Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- JVPLOXQKFGYFMN-UHFFFAOYSA-N gold tin Chemical compound [Sn].[Au] JVPLOXQKFGYFMN-UHFFFAOYSA-N 0.000 description 1
- 230000005484 gravity Effects 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0093—Wafer bonding; Removal of the growth substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0025—Processes relating to coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
- H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Led Devices (AREA)
Abstract
The invention provides an LED chip structure and a preparation method thereof, belonging to the field of chip preparation. Because the height of the supporting layer and the height of the conductive columns are controllable through the process, micro LEDs with smaller volumes can be manufactured by using the manufacturing method, the supporting layer can adapt to be shorter as the LED base layer is smaller, and the supporting layer can adapt to be longer as the LED base layer is larger, so that the process has strong universality.
Description
Technical Field
The invention relates to the technical field of chip preparation, in particular to an LED chip structure and a preparation method thereof.
Background
The preparation of blue-green LED chips of GaN on a conventional sapphire substrate belongs to the mature industry, white light products are widely applied to markets of white light illumination, high-end car lamps and the like, the device structure of the white light products is roughly divided into a forward mounting structure and a flip-chip structure with a sapphire substrate, and a thin film flip-chip for removing sapphire is also provided, but the application is obviously characterized by pursuing high current density, high brightness and the like.
In a novel display industry, when a product usually pursues high definition (i.e. high PPI) under the condition of satisfying brightness, the essential requirements of the product include small pixel pitch and small pixel light source, and then mini and Micro LED chips are derived.
The sapphire substrate LED is limited to the difficulty of sapphire processing, the thickness of the chip is difficult to grind and thin, 4 inches of sapphire is now ground to 60 μm, the scratch of the ground diamond and the stress of the processing process can cause the fracture of the 4 inches of chip, and the processing limit can limit the length and width dimensions of the chip to 60 μm (thickness) 60 μm (width) 60 μm (length):
1. if the length and the width are smaller than the thickness, a column with unstable gravity center is formed, and the chip is easy to turn laterally.
2. The length and width of the chip are smaller than the thickness of the chip, so that the cutting and splitting processing of the sapphire is very difficult.
3. When the sapphire substrate is stripped, the remaining GaN _ LED is extended to be about 5 μm thick, the mechanical resistance is poor, the length and the width cannot be less than 20 μm, and otherwise the GaN _ LED is easy to crack.
The mini to micro chips with sapphire substrate have a sudden change in size. For a silicon wafer, although sapphire is easy to process on a silicon substrate, the silicon substrate is opaque and cannot be used as a flip chip, so that the light emitting efficiency (external quantum efficiency) of the chip is influenced, and the processes of gold-tin eutectic crystal, tin paste crystal fixation and the like cannot be used only by using a bonding wire process.
Disclosure of Invention
Aiming at the limitations of the sapphire, silicon-based mini and Micro LED, the invention provides an LED chip structure and a preparation method thereof, wherein the substrate of the structure can be a sapphire substrate, a silicon substrate or other substrates, and can be a mini LED chip and a Micro LED.
In order to realize the purpose, the invention adopts the technical scheme that:
in one aspect, the present invention provides an LED chip structure, including an LED base layer structure, characterized in that: the LED base structure is provided with conductive columns corresponding to P/N positions, a supporting layer is arranged between the conductive columns and the LED base structure, and the supporting layer and the conductive columns are highly adapted to the size of the LED base structure.
Specifically, the height of the support layer ranges from 5 to 60 μm.
Particularly, the light-transmitting part of the LED base layer structure is provided with an N-type GaN layer with a roughened surface.
Specifically, one end of the conductive post is connected to a P/N electrode of the LED base layer structure, and a conductive bonding layer is formed at the other end of the conductive post.
Preferably, the conductive column is a copper column.
Preferably, the support layer may be one or more mixed materials of PI photoresist, PBO photoresist, photosensitive dry film, non-photosensitive polyimide, ABF dry film or resin.
Specifically, the LED base layer structure is an N-type GaN layer, a light emitting layer, an Al GaN thin film layer, a P-type GaN layer, an ITO layer and a DBR insulating layer from bottom to top.
On the other hand, the invention also provides a manufacturing method of the LED chip, which comprises the following steps:
the method comprises the following steps: generating a plating seed layer and a photoresist layer on the LED base layer structure on the substrate;
step two: developing the photoresist layer into an opening at the P/N pole position through a developing process;
step three: electroplating Cu columns in the openings;
step four: electroplating a metal bonding layer on the top of the Cu column;
step five: removing the photoresist layer by a photoresist removing process, and then removing the exposed seed layer by corrosion;
step six: forming a supporting layer at the position of the photoresist layer in the fifth step;
step seven: and removing the substrate to expose the bottom N-type GaN layer.
Specifically, the manufacturing method further includes:
step eight: and roughening the surface of the exposed N-type GaN layer by photoetching and etching technologies.
The LED chip structure in this application adopts the mode that upwards increases to promote and to make the focus of chip can obtain control, has avoided turning on one's side of chip, also can realize flip-chip simultaneously, because the increase in height makes the bottom get rid of the operation of basement just become more convenient, the silicon substrate just not to say even the peeling off of sapphire base can not lead to the chip to break yet.
Because the heights of the supporting layer and the conductive posts are controllable in process, micro LEDs with smaller volumes can be manufactured by using the manufacturing method, the smaller the LED base layer is, the shorter the supporting layer can adapt to, and conversely, the larger the LED base layer is, the longer the supporting layer can adapt to, so that the process has strong universality.
Drawings
The invention and its features, aspects and advantages will become more apparent from the following detailed description of non-limiting embodiments, which is to be read in connection with the accompanying drawings. Like reference symbols in the various drawings indicate like elements. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention.
FIG. 1 is a diagram illustrating a manufacturing process of a sputtered seed layer in a method for manufacturing an LED chip according to the present invention;
FIG. 2 is a diagram illustrating the formation of a photoresist layer in a method for fabricating an LED chip according to the present invention;
FIG. 3 is a preparation diagram of an electroplated Cu pillar and a metal bonding layer in the preparation method of the LED chip provided by the invention;
FIG. 4 is a manufacturing diagram of removing the photoresist layer and the exposed seed layer in the method for manufacturing an LED chip according to the present invention;
FIG. 5 is a preparation diagram of forming a supporting layer and exposing a metal bonding layer by photolithography in a preparation method of an LED chip according to the present invention;
FIG. 6 is a preparation diagram of a method for peeling off an original substrate in the preparation method of an LED chip provided by the invention;
FIG. 7 is a preparation diagram of surface roughening of an N-type GaN layer in the preparation method of the LED chip provided by the invention.
Detailed Description
The invention will be further described with reference to the following drawings and specific examples, which are not intended to limit the invention thereto.
The LED chip structure manufactured by the preparation method provided by the invention comprises the following steps: the N-type GaN layer, the light emitting layer, the AIGaN thin film layer, the P-type GaN layer and the ITO layer are arranged from bottom to top in sequence; a first target area and a second target area are arranged on the ITO layer; the first target area is provided with a first groove, the bottom surface of the first groove is positioned in the N-type GaN layer, and the opening surface of the first groove is coplanar with the upper surface of the ITO layer; etching stop layers are arranged on the bottom of the first groove and the surface of the second target region, and DBR insulating layers are arranged in a region without the etching stop layer on the ITO layer and a region without the etching stop layer in the first groove; a second groove is formed between the DBR insulating layer on the outer side of the second target region and the etching stop layer on the second target region; seed layers are also arranged on the first groove and the second groove; a Cu column is arranged on the seed layer, and a metal bonding layer is arranged on the Cu column; and the areas without the Cu columns on the DBR insulating layer are provided with supporting layers.
As shown in fig. 1, the invention provides a method for preparing an LED chip, which comprises the steps of firstly, using one of sapphire, silicon carbide, silicon, gallium nitride and aluminum nitride as an original substrate, and sequentially preparing an N-type GaN layer, a light-emitting layer, an AIGaN thin film layer, a P-type GaN layer and an ITO layer on the original substrate to form a first structure; defining a first target area for preparing a first groove and a second target area for preparing a second groove on the first structure; preparing a first target area needing to expose the N-type GaN layer through photoetching, etching the first target area to the N-type GaN layer through an etching process to form a first groove, and preparing an etching stop layer in the first groove and the second target area; growing a DBR insulating layer, preparing a first groove bottom and a second target area which need to expose the etching stop layer through photoetching, etching the groove to the etching stop layer in the first groove through an etching process, etching the groove to the etching stop layer in the second target area, and making a second groove to form a second structure.
Then sputtering a Ti and Cu seed layer on the second structure, as shown in FIG. 1; forming a photoresist layer on the seed layer, as shown in fig. 2; carrying out exposure treatment on the photoresist layer, developing the exposed photoresist layer by using a developing solution, etching the photoresist above the first groove to form a first opening, and etching the photoresist above the second groove to form a second opening; the width of the first opening is greater than that of the first groove, and the width of the second opening is greater than that of the second groove; 5-60 μm Cu posts are electroplated on the seed layer of the first opening and the second opening, and a metal bonding layer is electroplated on the Cu posts, as shown in FIG. 3.
Then, the photoresist layer and the exposed seed layer are sequentially removed to form a third structure, as shown in fig. 4; and (3) uniformly coating PI glue on the third structure or pressing a photosensitive dry film to form a supporting layer, and photoetching the supporting layer on the metal bonding layer until the metal bonding layer is exposed, as shown in figure 5. If the PI glue is used, the PI glue can be cured at high temperature, so that the glue film property is more stable. In addition, a supporting layer can be formed by directly pressing non-photosensitive materials such as polyimide, resin liquid or ABF dry film on the third structure. The PI glue and the dry film have good fluidity, so that gaps among chips can be completely filled, and the product reliability of the chips is improved; the cured PI glue/dry film and the like have good supporting force, and the subsequent processes of transfer, absorption, welding and the like of the LED chip are guaranteed; the thickness of the PI glue/dry film is selective, controllability is special, the patterning precision is high, the thickness size of the LED chip can be developed in the direction of being thinner and smaller, finally the original substrate is stripped, as shown in figure 6, the surface of the exposed N-type GaN layer is roughened through photoetching and etching technologies, as shown in figure 7, and the light extraction efficiency is increased to the maximum extent.
In summary, the preparation method provided by the invention has the advantages that the flip-chip PN junction is directly bonded with the positive and negative electrodes on the substrate in the eutectic way, the stress damage to the active layer possibly caused in the preparation and packaging process is avoided, and the thickness of the supporting layer is controllable, so that the chip can be made smaller and thinner as required.
The LED chip structure in this application adopts the mode that increases the supporting layer to make the anti mechanical capability of chip increase, and highly come the focus of control chip through the supporting layer, has avoided turning on one's side of chip, also can realize flip-chip simultaneously, it is just more convenient just to become because the operation that the base was got rid of to the increase in height makes the bottom, silicon substrate chemical corrosion is ripe and simple relatively, the peeling off of sapphire base has also been because of the buffering of supporting layer to the peeling off yield of chip has been improved.
Because the height of the supporting layer and the height of the conductive columns are controllable through the process, micro LEDs with smaller volumes can be manufactured by using the manufacturing method, the supporting layer can adapt to be shorter as the LED base layer is smaller, and the supporting layer can adapt to be longer as the LED base layer is larger, so that the process has strong universality.
The above description is that of the preferred embodiment of the present invention; it is to be understood that the invention is not limited to the particular embodiments described above, in which devices and structures not described in detail are understood to be implemented in a manner that is conventional in the art; any person skilled in the art can make many possible variations and modifications, or amendments to equivalent embodiments without departing from the technical solution of the invention, without affecting the essence of the invention; therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.
Claims (9)
1. An LED chip structure, includes LED basic structure, its characterized in that: the LED base structure is provided with conductive columns corresponding to P/N positions, a supporting layer is arranged between the conductive columns and the LED base structure, and the height of the supporting layer and the conductive columns is adapted to the size of the LED base structure.
2. The LED chip structure of claim 1, wherein the height of said supporting layer is in the range of 5-60 μm.
3. The LED chip structure of claim 1, wherein the light-transmitting portion of the LED substrate structure is provided with a roughened N-type GaN layer.
4. The LED chip structure of claim 1, wherein one end of the conductive pillar is connected to the P/N pole of the LED base structure, and the other end of the conductive pillar is formed with a conductive bonding layer.
5. The LED chip structure of claim 4, wherein the conductive posts are copper posts.
6. The LED chip structure of claim 1, wherein the supporting layer is one or more of PI photoresist, PBO photoresist, photosensitive dry film, non-photosensitive polyimide, ABF dry film, and resin.
7. The LED chip structure according to claim 1, wherein the LED substrate structure comprises an N-type GaN layer, a light emitting layer, an Al GaN thin film layer, a P-type GaN layer, an ITO layer and a DBR insulating layer from bottom to top.
8. An LED chip manufacturing method applied to the LED chip structure according to any one of claims 1 to 7, comprising the steps of:
the method comprises the following steps: generating a plating seed layer and a photoresist layer on the LED base layer structure on the substrate;
step two: developing the photoresist layer into an opening at the P/N pole position through a developing process;
step three: electroplating Cu columns in the openings;
step four: electroplating a metal bonding layer on the top of the Cu column;
step five: removing the photoresist layer by a photoresist removing process, and then removing the exposed seed layer by corrosion;
step six: forming a supporting layer at the position of the photoresist layer in the fifth step;
step seven: and removing the substrate to expose the bottom N-type GaN layer.
9. The method of claim 6, further comprising:
step eight: and roughening the surface of the exposed N-type GaN layer by photoetching and etching technologies.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211000763.7A CN115332430A (en) | 2022-08-19 | 2022-08-19 | LED chip structure and preparation method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211000763.7A CN115332430A (en) | 2022-08-19 | 2022-08-19 | LED chip structure and preparation method |
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| Publication Number | Publication Date |
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| CN115332430A true CN115332430A (en) | 2022-11-11 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202211000763.7A Pending CN115332430A (en) | 2022-08-19 | 2022-08-19 | LED chip structure and preparation method |
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| CN (1) | CN115332430A (en) |
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