CN115332191A - Low-K wafer structure and process method thereof - Google Patents
Low-K wafer structure and process method thereof Download PDFInfo
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- CN115332191A CN115332191A CN202110505340.XA CN202110505340A CN115332191A CN 115332191 A CN115332191 A CN 115332191A CN 202110505340 A CN202110505340 A CN 202110505340A CN 115332191 A CN115332191 A CN 115332191A
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- 238000000034 method Methods 0.000 title claims abstract description 33
- 238000005520 cutting process Methods 0.000 claims abstract description 32
- 238000012360 testing method Methods 0.000 claims abstract description 15
- 230000001681 protective effect Effects 0.000 claims abstract description 9
- 238000005530 etching Methods 0.000 claims abstract description 6
- 238000004806 packaging method and process Methods 0.000 claims abstract description 6
- 239000004642 Polyimide Substances 0.000 claims abstract description 3
- 229920001721 polyimide Polymers 0.000 claims abstract description 3
- 239000010410 layer Substances 0.000 claims description 68
- 239000010408 film Substances 0.000 claims description 29
- 239000002184 metal Substances 0.000 claims description 21
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 239000010409 thin film Substances 0.000 claims description 5
- 238000001259 photo etching Methods 0.000 claims description 4
- 238000004140 cleaning Methods 0.000 claims description 2
- 239000011248 coating agent Substances 0.000 claims description 2
- 238000000576 coating method Methods 0.000 claims description 2
- 238000009713 electroplating Methods 0.000 claims description 2
- 239000011241 protective layer Substances 0.000 claims description 2
- 238000004381 surface treatment Methods 0.000 claims description 2
- 239000011146 organic particle Substances 0.000 claims 1
- 239000002957 persistent organic pollutant Substances 0.000 claims 1
- 239000000126 substance Substances 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 9
- 238000012545 processing Methods 0.000 description 6
- 238000011946 reduction process Methods 0.000 description 6
- 238000013461 design Methods 0.000 description 4
- 238000002955 isolation Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000032798 delamination Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000011165 process development Methods 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Formation Of Insulating Films (AREA)
Abstract
The invention discloses a Low-K wafer structure and a process method thereof, which can be used for realizing mechanical cutting, namely pure double-knife or single-knife scribing reduction. The structure is characterized in that: 1) Compared with the existing wafer structure, the wafer structure supports the addition of a new process on the basis of the existing flow sheet manufacturing process, and a layer of new structure is added on the surface of the wafer, namely: after the wafer finishes normal flow sheet and before or after the electrical test, the surface of the wafer is coated or deposited for many times to cover the part of a film (such as polyimide) with a certain thickness (0-100 um) containing a cutting channel, and the film on a pattern required by subsequent packaging and test is removed by combining the processes of exposure, etching, baking and the like to form a new protective film layer, namely a PI layer. 2) The novel Low-K wafer structure with the added PI layer can realize mechanical cutting, namely pure double-blade or single-blade scribing reduction.
Description
Technical Field
The invention relates to the field of low-K wafer processing and manufacturing, in particular to a wafer processing method which is within 90nm and comprises 90nm such as 90nm,
65nm, 55nm, 40nm, 28nm, 14nm and 7 nm.
Background
The traditional wafer structure is a non-low-k wafer with nodes above 90nm or a low-k wafer with nodes within 90nm, and comprises a three-layer structure of a chip protection layer, a metal layer and a silicon-based circuit layer. Compared with the traditional non-Low-K wafer structure with the nodes above 90nm, the Low-K wafer structure with the nodes within 90nm is added with the Low-K metal of the through hole structure in the metal layer to form the chip Low-K and the metal layer, and is completely different from the traditional metal layer. The structure difference enables the mechanical cutting of the traditional non-Low-K wafer scribing reduction process of the node above 90nm, namely pure double-blade or single-blade scribing reduction, and the Low-K wafer with the chip Low-K and the metal layer inside the node above 90nm is not suitable for the Low-K wafer with the chip Low-K and the metal layer due to the fact that the Low-K and the metal layer are fragile in materials and poor in stress tolerance degree compared with a pure metal layer.
At present, mechanical cutting, namely a pure double-blade or single-blade scribing reduction process, a laser invisible cutting process, a laser grooving process, an EBG process and a DBG process are mainly adopted in the scribing reduction process. Wherein: the EBG process and the DBG process are in a process development stage and do not enter a mass production stage; the laser invisible cutting and EBG cutting process is mainly used for products with 20um narrow cutting channels; the DBG process is mainly used for the scratch reduction process of ultrathin chip products; the mechanical cutting, namely the pure double-blade or single-blade scribing reduction process is mainly used for common products with cutting blade width more than or equal to 62um and non-low-K wafer structure more than 90 nm.
At present, pure double-blade scribing is mainly adopted in mechanical cutting, namely pure double-blade or single-blade scribing reducing technology, wherein the thickness of the first blade is reduced by 1/3 of the wafer thickness, the thickness of the second blade is reduced by 2/3 of the wafer thickness, and the thickness of the UV film is about ten microns or more.
At present, the mainstream reducing and scribing process of low-K wafer structure products within 90nm (such as 65nm/55nm/40nm/28nm/14nm/7nm and the like) on the market is a combination form of laser grooving and mechanical cutting, namely a pure double-blade or single-blade reducing and scribing process, namely, firstly, special laser grooving equipment is used for scanning and gasifying chip low-K and a metal layer in a cutting channel in the wafer cutting channel through laser beams to form an isolation groove, and then, mechanical cutting, namely, pure double-blade or single-blade reducing and scribing process is used for reducing and scribing.
As mentioned above, because the LOW-K chip of the LOW-K wafer with a node within 90nm and the metal layer of the metal layer are weaker and have poor stress tolerance compared with the metal layer of the traditional non-LOW-K wafer with a node above 90nm, the LOW-K layer in the LOW-K wafer needs to be burned and gasified by using a laser grooving process, and after the chip LOW-K in the cutting track is isolated from the channel of the metal layer, the stress caused by subsequent mechanical cutting, namely pure double-blade or single-blade scribing reduction, can be released, so that the risk of failure of the functional characteristics of the chip caused by edge breakage, LOW-K layer delamination and the like caused by the mechanical cutting, namely pure double-blade or single-blade scribing reduction can be reduced. The laser grooving process generally uses two beams of laser, and scans in the X and Y directions of the wafer cutting track according to different thicknesses of the metal layer and under the conditions of different working powers, frequencies, cutting speeds and the like to respectively form an isolation groove with the groove depth of about 5um and above.
In summary, in order to ensure the scribing reduction quality, the LOW-K wafer with an inner node of 90nm or less needs to be processed by combining laser grooving and mechanical cutting, i.e., a pure double-blade or single-blade scribing reduction process, so that special laser grooving equipment needs to be equipped for processing. At present, the number of enterprises with the production capacity of the laser grooving process in China is limited, and due to the factors of high input cost of laser grooving equipment, low productivity and the like, the scratch reduction quality and the production and processing capacity of the Low-K wafer are quite limited, and the production and processing cost is high.
In order to solve the problems of processing quality and high production cost, a novel Low-K wafer structure is constructed, namely a chip surface protective film layer (PI layer) is added on the basis of the traditional three-layer structure, and the novel Low-K wafer with the PI protective film layer is provided.
Disclosure of Invention
The invention can realize a novel Low-K wafer structure with mechanical scratch reduction, and the structure can solve the problem of scratch reduction limitation by adding a chip surface protective film layer (PI layer) on the basis of the traditional three-layer structure (a chip protective layer, a chip Low-K and metal layer and a silicon-based circuit layer). After the novel Low-K wafer structure finishes normal flow sheet and before or after electrical test, the wafer surface is coated or deposited for many times to cover the part of a film (such as polyimide) with a certain thickness (0-100 um) containing a cutting channel, and the film on the pattern required by subsequent packaging and test is removed by combining the processes of exposure, etching, baking and the like, so that the film in the cutting channel is kept as much as possible, and finally a new protective film layer, namely a PI layer is formed. The novel Low-K wafer with the PI protective film layer is softer than the existing Low-K wafer, so that stress release can be realized, and mechanical cutting, namely pure double-knife or single-knife scratch reduction machining can be directly used under the condition of not using laser grooving. The structure has the characteristics and implementation means that:
1) Before or after the wafer finishes the electrical test of the normal flow sheet, a thin film layer is formed by coating, and the thickness of the formed thin film layer is required to meet the specification requirement (0-100 um); and then, carrying out surface cleaning on the wafer surface by adopting a Pre-clean plasma surface to remove organic pollution and particles on the wafer surface, etching out a required pattern such as an electrical characteristic test area by a photoetching process, carrying out surface treatment on a photoetching CD opening by descum electroplating, removing an opening surface oxide and residues, leading out the testing pattern, and forming a complete PI film protection layer.
2) The PI layer is combined with the processes of multiple exposure, etching, baking and the like, the thin film used on the pattern required by subsequent packaging and testing is removed, and the thin film in the cutting channel is reserved as much as possible. The film in the newly-added cutting path can relieve the stress and edge breakage caused by mechanical cutting.
The novel low k wafer structural design replaces the existing laser grooving and mechanical cutting process, mechanical cutting can be directly adopted, namely pure double-knife or single-knife scratch reduction is achieved, the cost investment of enterprise production and processing equipment is reduced, and scratch reduction capacity is improved.
The novel Low K wafer structure is free from restriction of process nodes, and can be suitable for Low K wafer reduction of each node (28nm, 40nm,55nm,65nm,90nm and the like)
The Low-K wafer structure can change the existing Low-K wafer downscaling mainstream process. The Low-K wafer structure ensures that the scratch reducing production process of the product is more reliable, the scratch reducing quality and the productivity are improved, and the cost is reduced.
Drawings
As shown in FIG. 1, the front surface of the new low-K wafer structure is schematically shown
As shown in FIG. 2, the cross-sectional view of the new low-K wafer structure
Detailed Description
The process of the present invention is further described below with reference to the accompanying drawings.
As shown in the front surface schematic diagram of the chip illustrated in FIG. 1, through the design of the present invention, the bonding pads on the chip surface and the images required for testing are exposed (i.e., the pad portion for testing the black small square frame), the electrical connection of the original design of the chip is maintained, the original functional characteristics of the chip are maintained, and new films are covered on other places.
The schematic cross-sectional structure of the scribe line as illustrated in fig. 2 includes a chip surface protection film (PI protection film layer in the illustration) and a chip protection layer (PA layer in the illustration), a chip low-K and a metal layer (low-K layer in the illustration), and a silicon-based circuit layer (Si layer in the illustration). The chip surface protection film layer (PI protection film layer in the figure) is the new process of the utility model, the chip protection layer (PA layer in the figure), the chip Low-K and metal layer (Low-K layer in the figure) and the chip substrate base layer Si layer are the existing process of the existing foundry practice of the current foundry practice. By adopting the structural design, the Low-K wafer can directly adopt mechanical reduction and scribing (pure double-knife reduction and scribing or single-knife reduction and scribing), stress when the mechanical reduction and scribing is released is relieved due to the PI protective film on the surface of the chip, a mechanical cutting mode is directly adopted without laser grooving, and quality problems such as layering and edge breakage after the reduction and scribing are avoided.
The foregoing has described in detail an embodiment of the present invention and the detailed concepts of its implementation. It is to be understood by those skilled in the art that the present invention is not limited to the embodiments described above, which are presented in the context of a single embodiment or a combination of embodiments. The present invention is susceptible to various changes and modifications without departing from the spirit and scope of the invention, and such changes and modifications are intended to be within the scope of the invention as claimed.
Claims (4)
1. A low-K wafer structure is characterized in that a chip surface protection film layer is added on the basis of a three-layer structure of a traditional chip protection layer, a chip low-K metal layer and a silicon-based circuit layer, wherein the chip surface protection film layer is positioned on the chip protection layer, the chip protection layer is positioned on the chip low-K metal layer, and the chip low-K metal layer is positioned on the silicon-based circuit layer.
2. The Low-K wafer structure as claimed in claim 1, wherein the chip surface protecting film layer is a film layer made of polyimide, and the thickness of the film layer is required to be 0-100 um.
3. The Low-K wafer structure of claim 1, wherein the chip surface protection film layer includes a portion of the scribe line, and the film on the pattern required for the subsequent packaging and testing is removed by combining the processes of exposure, etching and baking, so that as much film as possible remains in the scribe line to realize the subsequent packaging and testing.
4. A low-K wafer structure process method is characterized by comprising the following steps:
1) Before or after the wafer finishes the electrical test of the normal flow sheet, a thin film layer is formed on a wafer chip protective layer through coating, then organic pollutants and particles on the surface of the wafer are removed through Pre-clean plasma surface chemical cleaning, then a required pattern is etched through a photoetching process, surface treatment is carried out on an opening of a photoetching CD through descum electroplating, oxide and residues on the surface of the opening are removed, the pattern for test is led out, and a chip surface protective film layer is formed;
2) The chip surface protective film layer is combined with multiple exposure, etching and baking processes to remove the film on the pattern required by subsequent packaging and testing, and the film in the cutting channel is reserved as much as possible.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110505340.XA CN115332191A (en) | 2021-05-10 | 2021-05-10 | Low-K wafer structure and process method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110505340.XA CN115332191A (en) | 2021-05-10 | 2021-05-10 | Low-K wafer structure and process method thereof |
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| Publication Number | Publication Date |
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| CN115332191A true CN115332191A (en) | 2022-11-11 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110505340.XA Pending CN115332191A (en) | 2021-05-10 | 2021-05-10 | Low-K wafer structure and process method thereof |
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| Country | Link |
|---|---|
| CN (1) | CN115332191A (en) |
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2021
- 2021-05-10 CN CN202110505340.XA patent/CN115332191A/en active Pending
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