CN115331633A

CN115331633A - Pixel circuit, silicon-based display panel and display device

Info

Publication number: CN115331633A
Application number: CN202211106071.0A
Authority: CN
Inventors: 钱栋; 周志伟; 李嘉灵; 沈永财
Original assignee: Hefei Shiya Display Technology Co ltd
Current assignee: Hefei Shiya Display Technology Co ltd
Priority date: 2022-09-09
Filing date: 2022-09-09
Publication date: 2022-11-11

Abstract

The embodiment of the invention discloses a pixel circuit, a silicon-based display panel and a display device, comprising: the source electrode of the driving transistor is coupled to a first power supply end, the drain electrode of the driving transistor is electrically connected with the anode of the light-emitting element, and the cathode of the light-emitting element is electrically connected with a second power supply end; the pixel circuit further comprises at least one first transistor, the first transistor is an at least four-terminal device, the source electrode of the first transistor is electrically connected with the drain electrode of the driving transistor, and the substrate end of the first transistor is electrically connected with the source electrode of the first transistor. The technical scheme provided by the embodiment of the invention solves the problem of abnormal display luminescence caused by threshold voltage drift in the conventional pixel circuit, improves the display quality, saves the pixel area and is favorable for high-resolution design of a display device.

Description

Pixel circuit, silicon-based display panel and display device

Technical Field

The embodiment of the invention relates to the technical field of display, in particular to a pixel circuit, a silicon-based display panel and a display device.

Background

With the continuous development and improvement of display technology, people have higher and higher requirements on display. Among them, the organic light emitting display device realizes image display by a plurality of pixels arranged in a matrix form, each pixel including a light emitting element and a pixel circuit driving the light emitting element to emit light. In the conventional pixel circuit, when the threshold voltage of a transistor electrically connected to the anode of the light emitting element is shifted, stable light emission of the light emitting element is affected, and display quality is deteriorated.

Disclosure of Invention

The invention provides a pixel circuit, a silicon-based display panel and a display device, which are used for solving the problem of abnormal display luminescence caused by threshold voltage drift in the conventional pixel circuit.

In a first aspect, an embodiment of the present invention provides a pixel circuit, including: the light-emitting device comprises a driving transistor and a light-emitting element, wherein the source electrode of the driving transistor is coupled to a first power supply end, the drain electrode of the driving transistor is electrically connected with the anode of the light-emitting element, and the cathode of the light-emitting element is electrically connected with a second power supply end;

the pixel circuit further comprises at least one first transistor, the first transistor is an at least four-terminal device, the source electrode of the first transistor is electrically connected with the drain electrode of the driving transistor, and the substrate end of the first transistor is electrically connected with the source electrode of the first transistor.

In a second aspect, an embodiment of the present invention further provides a silicon-based display panel, including: a plurality of pixel circuits as described in the first aspect arranged in an array.

In a third aspect, an embodiment of the present invention further provides a display device, including: the silicon-based display panel of the second aspect.

According to the technical scheme, the source electrode of the driving transistor in the pixel circuit is coupled to a first power supply end, and the drain electrode of the driving transistor is coupled to the anode of the light-emitting element, so that the driving transistor generates driving current according to a data signal of the grid electrode of the driving transistor and a voltage difference between the first power supply end to drive the light-emitting element to emit light; the drain electrode of the driving transistor is also electrically connected with the source electrode of at least one first transistor, the first transistor is an at least four-terminal device, the substrate end of the first transistor is electrically connected with the source electrode of the first transistor, so that the source electrode and the substrate end of the first transistor are always at the same electric potential, the electric potential difference between the grid electrode and the source electrode of the first transistor is kept stable, the influence on the threshold voltage of the first transistor due to the fluctuation state of the electric potential of the drain electrode of the driving transistor is avoided, the on or off of the first transistor cannot be accurately controlled, the anode electric potential of the light-emitting element can be kept stable, the light-emitting element can accurately and stably emit light, and the display quality is improved; meanwhile, the substrate end of the first transistor is electrically connected with the source electrode of the first transistor, extra wiring electrically connected with the substrate end of the first transistor is not needed, the structure of a pixel circuit is simplified, the occupied area of the pixel circuit is reduced, and the high-resolution design of the display device is facilitated.

It should be understood that the statements in this section do not necessarily identify key or critical features of the embodiments of the present invention, nor do they necessarily limit the scope of the invention. Other features of the present invention will become apparent from the following description.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the description below are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention;

fig. 2 is a schematic cross-sectional view of a pixel circuit according to an embodiment of the invention;

fig. 3 is a schematic diagram of a partial cross-sectional structure of another pixel circuit according to an embodiment of the invention;

fig. 4 is a schematic diagram of a partial top view structure of a pixel circuit according to an embodiment of the invention;

fig. 5 is a schematic cross-sectional view of a portion of another pixel circuit according to an embodiment of the invention;

fig. 6 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention;

fig. 7 is a schematic diagram of a partial cross-sectional structure of another pixel circuit according to an embodiment of the invention;

fig. 8 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention;

fig. 9 is a driving timing diagram of a pixel circuit according to an embodiment of the invention;

fig. 10 is a schematic structural diagram of another pixel circuit according to an embodiment of the disclosure;

fig. 11 is a driving timing diagram of another pixel circuit according to an embodiment of the invention;

FIG. 12 is a schematic diagram of a silicon-based display panel according to an embodiment of the present invention;

fig. 13 is a schematic structural diagram of a display device according to an embodiment of the present invention.

Detailed Description

In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

At present, the light emitting device is a current-type driving device, and a driving transistor is required to be disposed in a pixel circuit, so that the driving transistor converts a data signal written to a gate thereof into a driving current, and then drives the light emitting device to emit light.

When different data signals are written into the grid electrode of the driving transistor, the driving transistor can generate different driving currents, so that the light-emitting element has different light-emitting brightness; in addition, since the overall light-emitting brightness of the light-emitting element is also related to the light-emitting duration of the light-emitting element, in some application scenarios, the light-emitting brightness of the display panel can be controlled by controlling the time length for which the driving transistor supplies the driving current to the light-emitting element.

In the prior art, a light-emitting control module is arranged between the drain of a driving transistor and the anode of a light-emitting element and/or between the source of the driving transistor and a first power supply, and the light-emitting control module periodically controls a current path from the first power supply to the light-emitting element, so that the time for supplying the driving current to the light-emitting element can be controlled. In this way, the drain potential of the driving transistor is in a fluctuating state due to the intermittent supply of the driving current to the light emitting element, which causes the source of another transistor electrically connected to the drain of the driving transistor to change in accordance with the fluctuation of the drain potential of the driving transistor, causing the threshold voltage of the transistor electrically connected to the drain of the driving transistor to drift repeatedly without using the control of the transistor. Meanwhile, the drain of the driving transistor is also electrically connected to the anode of the light emitting element, which affects the anode potential of the light emitting element and thus the light emitting accuracy of the light emitting element when the transistor electrically connected to the drain of the driving transistor cannot be accurately controlled.

In order to solve the above-mentioned problems, embodiments of the present invention provide a pixel circuit capable of preventing a threshold voltage of a first transistor electrically connected to a drain of a driving transistor from repeatedly drifting, thereby accurately controlling the first transistor and further ensuring stability of an anode potential of a light emitting element.

Fig. 1 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention, and as shown in fig. 1, the pixel circuit includes: a driving transistor M1 and a light emitting element 20, a source S of the driving transistor M1 being coupled to a first power source terminal ELVDD, a drain D of the driving transistor M1 being electrically connected to an anode of the light emitting element 20, a cathode of the light emitting element 20 being electrically connected to a second power source terminal ELVSS; the pixel circuit further includes at least one first transistor 10, the first transistor 10 is an at least four-terminal device, a source of the first transistor 10 is electrically connected to the drain D of the driving transistor M1, and a substrate end of the first transistor 10 is electrically connected to the source of the first transistor 10.

The light emitting element 20 includes, but is not limited to, a current driven element such as an OLED or a Micro OLED. The driving transistor M1 may be a P-channel transistor, and at this time, when the voltage difference between the gate of the driving transistor M1 and the source S thereof is smaller than the threshold voltage thereof, the driving transistor M1 is turned on; the driving transistor M1 may also be an N-channel transistor, and when the voltage difference between the gate of the driving transistor M1 and the source S thereof is greater than the threshold voltage, the driving transistor M1 is turned on. For convenience of description, the embodiment of the present invention is exemplarily illustrated by taking the driving transistor M1 as a P-channel transistor.

Specifically, the source S of the driving transistor M1 is coupled to the first power source terminal ELVDD, and the drain D of the driving transistor M1 is electrically connected to the anode of the light emitting device 20, so that the driving transistor M1 can generate a driving current according to the data signal written by the gate thereof and the voltage difference of the first power source terminal ELVDD, and transmit the driving current to the anode of the light emitting device 20 to drive the light emitting device 20 to emit light, and the potential of the drain D of the driving transistor M1 is in a fluctuating state during the driving of the light emitting device 20 by the driving transistor M1. At this time, since the drain D of the driving transistor M1 is also electrically connected to the source of the first transistor 10, which may be, for example, the first light emitting control transistor M2 and/or the reset transistor M3, when the potential of the drain D of the driving transistor M1 fluctuates, the potential of the source of the first transistor 10 fluctuates accordingly, and if the substrate end of the first transistor 10 is at a fixed potential, the potential difference between the substrate and the source of the first transistor 10 repeatedly jumps, so that the threshold voltage of the first transistor 10 repeatedly drifts, thereby affecting the performance of the first transistor 10 and further affecting the stability of the anode potential of the light emitting element 20.

In the embodiment of the present invention, the substrate end of the first transistor 10, the source of the first transistor 10 and the drain D of the driving transistor M1 are all electrically connected at the same node, so that even if the potential of the drain D of the driving transistor M1 fluctuates, the source and the substrate end of the first transistor can be guaranteed to be always at the same potential, and the potential difference between the gate and the source of the first transistor 10 is kept stable, thereby preventing the threshold voltage of the first transistor from being affected when the potential of the drain D of the driving transistor M1 fluctuates, and preventing the first transistor from being turned on or off accurately. Thus, the stability of the anode potential of the light-emitting element 20 can be improved, and stable light emission of the light-emitting element 20 can be ensured.

It is understood that the first transistor 10 in the embodiment of the present invention may be any transistor electrically connected to the drain D of the driving transistor M1, including but not limited to the structure shown in fig. 1.

For example, as shown in fig. 1, the pixel circuit may further include a write block 30 and a memory block 40, the gate of the driving transistor M1, the write block 30 and the memory block 40 are coupled to the second node N2, wherein the write block 30 is further electrically connected to the input signal terminal DATA, the source S of the driving transistor M1, the memory block 40 and the first power supply terminal ELVDD are coupled to the fourth node N4, the drain D of the driving transistor M1 is electrically connected to the anode of the light emitting element 20, the cathode of the light emitting element 20 is electrically connected to the second power supply terminal ELVSS, and the first power supply terminal ELVDD generally provides the first power supply signal ELVDD as a positive power supply signal and the second power supply terminal ELVSS provides the second power supply signal ELVSS as a negative power supply signal. Therefore, when a conductive path is formed from the first power signal Elvdd to the second power signal Elvss, the driving transistor M1 is driven to generate a driving current according to the data signal written into the gate thereof and the voltage difference between the first power terminal Elvdd, so as to drive the light emitting element 20 to emit light.

In an alternative embodiment, with continued reference to fig. 1, when the pixel circuit includes a reset transistor M3 and a first light-emitting control transistor M2, the first light-emitting control transistor M2 and the reset transistor M3 may both be a first transistor 10; the grid electrode of the RESET transistor M3 is electrically connected with a RESET signal control end RESET, and the drain electrode of the RESET transistor M3 is electrically connected with a RESET signal end VREF; a gate of the first light-emitting control transistor M2 is electrically connected to the light-emitting control signal terminal EMIT, and a drain of the first light-emitting control transistor M2 is electrically connected to an anode of the light-emitting element 20; the source of the reset transistor M3, the substrate end of the reset transistor M3, the source of the first light emission controlling transistor M2, the substrate end of the first light emission controlling transistor M2, and the drain D of the driving transistor M1 are electrically connected to the first node N1.

Wherein, in one driving cycle, the pixel circuit can sequentially perform an initialization phase, a threshold compensation phase, a data writing phase, and a light emitting phase. In the initialization stage, the write module 30 is configured to write the initialization signal Vof to the second node N2 to initialize the gate of the driving transistor M1 electrically connected to the second node N2 and the memory module 40, and by making a difference between the initialization signal Vof and the first power signal ELVDD of the first power source terminal ELVDD smaller than a threshold voltage of the driving transistor M1, the driving transistor M1 can be ensured to be in a conducting state to prepare for a subsequent threshold compensation stage. In the threshold compensation stage T2, the write module 30 continues to write the initialization signal Vof to the second node N2, and makes the driving transistor M1 in the on-critical state, so as to detect the threshold voltage of the driving transistor M1 and store the threshold voltage in the storage module 40. In the data writing phase, the writing module 20 writes the data signal Vdata into the second node N2 and stores the data signal Vdata in the storage module 80, so that the potential of the second node N2 is changed from Vof to Vdata. In the light emitting phase, the light emitting control signal terminal EMIT may periodically control the first light emitting control transistor M2 to be turned on, so that the source of the first light emitting control transistor M2 and the drain D of the driving transistor M1 are coupled to the potential of the first node N1 to be in a dynamic change process, that is, the driving transistor M1 may periodically provide a driving current to the light emitting element 20 under the control of the first light emitting control transistor M2 to control the light emitting duration of the light emitting element 20, and since the luminance exhibited by the light emitting element 20 is related to the integral of the light emitting luminance with respect to time, the light emitting luminance of the light emitting element 20 can be accurately controlled by controlling the light emitting duration of the light emitting element 20.

In addition, a RESET control signal RESET provided from a RESET signal control terminal RESET in the pixel circuit can control the on or off of the RESET transistor M3. A Reset phase may be further included in one driving period, and in the Reset phase, when the Reset control signal Reset controls the Reset transistor M3 to be turned on, the Reset signal VREF provided from the Reset signal terminal VREF is written to the first node N1 through the turned-on Reset transistor M3 to Reset the anode potential of the light emitting element 20.

Specifically, when the first transistor 10 is the first light-emitting control transistor M2, the substrate end of the first transistor 10 is electrically connected to the source of the first transistor 10, and the drain D of the driving transistor M1 is coupled to the first node N1, so that the source of the first light-emitting control transistor M2 and the substrate end thereof are always at the same potential, and the potential difference between the gate and the source of the first light-emitting control transistor M2 is kept in a stable state. Even if the light emission control signal terminal EMIT periodically controls the first light emission control transistor M2 to be turned on or off, the threshold voltage of the first light emission control transistor M2 will not be shifted due to the fluctuation of the potential of the first node N1, which will affect the anode potential of the light emitting element 20 and thus the stable light emission of the light emitting element 20. Similarly, when the first transistor 10 is the RESET transistor M3, the source of the RESET transistor M3 is electrically connected to the substrate end thereof, and the drain D of the driving transistor M1 is coupled to the first node N1, so that the shift of the threshold voltage of the first transistor 10 can be also suppressed, and the RESET control signal RESET provided by the RESET signal control end RESET can stably control the on or off of the RESET transistor M3, so as to RESET the potential of the first node N1, and ensure the stable and reliable light emission of the light emitting element 20.

It should be noted that the first transistor 10 may be a P-channel transistor or an N-channel transistor, which is not specifically limited in this embodiment of the present invention, and for convenience of description, the first transistor 10 is exemplified by a P-channel transistor in the embodiment of the present invention.

Optionally, fig. 2 is a schematic cross-sectional view of a part of a cross-sectional structure of a pixel circuit according to an embodiment of the present invention, as shown in fig. 1, a silicon-based substrate 100 is provided, and a source 101, a drain 102, and a substrate end 103 of a first transistor 10 are disposed in the silicon-based substrate 100; the doping type of the substrate terminal 103 of the first transistor 10 is the same as the type of the silicon-based substrate 100, and the doping type of the source 101 and the drain 102 of the first transistor 10 are opposite to the doping type of the substrate terminal 103 of the first transistor 10.

Specifically, the silicon-based substrate 100 may be a P-type or N-type substrate, and the doping type of the substrate end 103 of the first transistor 10 is the same as the channel type of the first transistor 10, that is, when the channel type of the first transistor 10 is N-type, the doping type of the substrate end 103 of the first transistor 10 is also N-type, and an N-type heavily doped region, that is, the substrate end 103, may be formed by heavily doping N-type impurity ions on the silicon-based substrate 100; the doping type of the source 101 and the drain 102 of the first transistor 10 are opposite to the channel type of the first transistor 10, that is, when the channel type of the first transistor 10 is N-type, two P-type heavily doped regions are formed by heavily doping P-type impurity ions at two opposite sides of the channel of the first transistor 10, and the two P-type heavily doped regions are respectively used as the source 101 and the drain 102 of the first transistor 10.

Alternatively, in other embodiments, when the channel type of the first transistor 10 is P-type, the doping type of the substrate end 103 of the first transistor 10 is also P-type, a P-type heavily doped region, i.e. the substrate end 103, can be formed by heavily doping P-type impurity ions on the silicon-based substrate 100, and at the same time, two N-type heavily doped regions are formed by heavily doping N-type impurity ions on two opposite sides of the first transistor 10, and the two N-type heavily doped regions are respectively used as the source 101 and the drain 102 of the first transistor 10.

It should be noted that the channel type of the first transistor 10 is not specifically limited in the embodiments of the present invention, and may be set according to actual requirements.

Optionally, referring to fig. 1 and 2 in combination, the first transistor 10 further includes a first connection electrode 111, a source connection structure 112, and a drain connection structure 113; the pixel circuit further comprises a first metal layer 110 on one side of the silicon-based substrate 100; the first metal layer 110 includes a first connection electrode 111, a source connection structure 112, and a drain connection structure 113; in the same first transistor 10, the first connection electrode 111 is electrically connected to the substrate terminal 103 through the via 131, the source connection structure 112 is electrically connected to the source 101, and the drain connection structure 113 is electrically connected to the drain 102. As such, the source 101 and the substrate terminal 103 of the first transistor 10 may be electrically connected to the drain of the driving transistor M1 through the source connection structure 112 and the first connection electrode 111, respectively, and the drain 102 of the first transistor 10 may be electrically connected to other devices or signal lines through the drain connection structure 113; meanwhile, the first connection electrode 111, the source connection structure 112 and the drain connection structure 113 are disposed on the same layer, which can simplify the structure of the pixel circuit and is beneficial to the light and thin of the silicon-based display panel including the pixel circuit.

In addition, a second metal layer 120 may be further disposed between the first metal layer 110 and the silicon-based substrate 100, the second metal layer 120 may include the gate electrode 104 of the first transistor 10, an insulating layer 130 may be included between the first metal layer 110 and the second metal layer 120, and a material of the insulating layer 130 may include an inorganic material and/or an organic material, which is not limited herein. At this time, the first metal layer 110 may further include a gate connection structure 114, and the gate connection structure 114 is electrically connected to the gate 104, so that the gate of the first transistor 10 may receive a corresponding control signal through the gate connection structure 114, thereby controlling on or off of the first transistor 10.

The material of the first metal layer 110 includes, but is not limited to, molybdenum aluminum molybdenum, titanium aluminum titanium, and the like, and the material of the second metal layer 120 includes, but is not limited to, molybdenum, titanium aluminum titanium, and the like.

Optionally, fig. 3 is a schematic cross-sectional view of a part of another pixel circuit according to an embodiment of the present invention, and as shown in fig. 3, when both the first light-emitting control transistor M2 and the reset transistor M3 are the first transistor 10, a substrate end of the first light-emitting control transistor M2 and a substrate end of the reset transistor M3 are the same substrate end 103.

Specifically, by disposing the substrate end 103 between the active region of the first light-emitting control transistor M2 and the active region of the reset transistor M3, the substrate end 103 can be used as both the substrate end of the first light-emitting control transistor M2 and the substrate end of the reset transistor M3, so that the number of substrate ends disposed in the pixel circuit can be reduced, and thus, there is no need to reserve a corresponding space for disposing more substrate ends, which is beneficial to simplifying the structure of the pixel circuit and reducing the occupied area of the pixel circuit.

In addition, fig. 4 is a schematic diagram of a partial top view structure of a pixel circuit according to an embodiment of the present invention, and referring to fig. 3 and fig. 4 in combination, since the source 101 of the first light-emitting control transistor M2 and the source 101 of the reset transistor M3 are both electrically connected to the substrate terminal 103, the source 101 of the first light-emitting control transistor M2 and the source 101 of the reset transistor M3 can be the same heavily doped region (for example, a P-type heavily doped region or an N-type heavily doped region) in the silicon-based substrate 100, and the substrate terminal 103 is disposed adjacent to the source 101, so as to reduce a pixel occupation area, and facilitate shortening an electrical connection path between the source 101 of the first light-emitting control transistor M2 and the source 101 of the reset transistor M3 and the substrate terminal 103, which facilitates circuit layout. The drain 102 of the first light emitting control transistor M2 and the drain 102 of the reset transistor M3 are two heavily doped regions independent of each other so as to receive different electrical signals, respectively. A region located between the source 101 and the drain 102 of the first light-emitting control transistor M2 and overlapping with a projection of the gate 104 of the first light-emitting control transistor M2 in a direction perpendicular to the substrate 100 is a channel region of the first light-emitting control transistor M2. Similarly, a region located between the source 101 and the drain 102 of the reset transistor M3 and overlapping a projection of the gate 104 of the reset transistor M3 in a direction perpendicular to the substrate 100 is a channel region of the reset transistor M3.

It should be noted that the source connection structure 112 and the drain connection structure 113 of the first light emitting control transistor M2 and the source connection structure 112 and the drain connection structure 113 of the reset transistor M3 may be disposed in the same layer or in different layers, which is not specifically limited in this embodiment of the present invention. Similarly, the gate connection structure 114 of the first light-emitting control transistor M2 and the gate connection structure 114 of the reset transistor M3 may be disposed in the same layer or in different layers, which is not specifically limited in this embodiment of the present invention. Fig. 3 is merely an exemplary illustration.

Alternatively, fig. 5 is a schematic cross-sectional view of a portion of another pixel circuit according to an embodiment of the present invention, and with reference to fig. 1 and 5, a substrate end of the driving transistor M1 is electrically connected to the first power terminal ELVDD; wherein the substrate end of the driving transistor M1 and the substrate end of the first transistor 10 are insulated from each other.

Specifically, since the substrate terminal of the driving transistor M1 is electrically connected to the first power supply terminal ELVDD, which is usually a fixed positive power supply signal, carriers in the substrate of the driving transistor M1 do not move forward under the influence of external factors, and thus the switching performance of the driving transistor M1 is not affected, and the noise is prevented. However, the substrate end of the first transistor 10 is electrically connected to the drain D of the driving transistor M1, and since the first light-emitting control transistor M2 is periodically turned on, the path formed between the first power source terminal ELVDD and the second power source terminal ELVSS is periodically turned on and off under the control of the first light-emitting control transistor M2, so that the driving current generated by the driving transistor M1 periodically charges and discharges the drain D of the driving transistor M1, the drain D of the driving transistor M1 is subject to potential fluctuation, and the potential received by the substrate end 103 of the first transistor 10 electrically connected to the drain D of the driving transistor M1 is also fluctuated. At this time, impurities of the opposite type to the substrate doping type of the driving transistor M1 and the first transistor 10 may be doped in the substrate base plate 100 between the driving transistor M1 and the first transistor 10 to form the isolation region 105, and the substrate end of the driving transistor M1 and the substrate end of the first transistor 10 may be isolated from each other to avoid the mutual influence between the substrate potential of the driving transistor M1 and the substrate potential of the first transistor 10.

It should be noted that the source connection structure 112 and the drain connection structure 113 of the first light-emitting control transistor M2 and the source connection structure and the drain connection structure of the driving transistor M1 may be disposed in the same layer or in different layers, which is not specifically limited in this embodiment of the present invention. Similarly, the gate connection structure 114 of the first light-emitting control transistor M2 and the gate connection structure of the driving transistor M1 may be disposed in the same layer, or may be disposed in different layers, which is not specifically limited in this embodiment of the present invention. Fig. 5 is an exemplary drawing only.

Optionally, fig. 6 is a schematic structural diagram of another pixel circuit provided in the embodiment of the present invention, and as shown in fig. 6, the pixel circuit further includes at least one second transistor 50; the drain of the second transistor 50 is electrically connected to the source S of the driving transistor M1 or the gate of the driving transistor M1; the second transistor 50 is an at least four-terminal device; a substrate end of the second transistor 50 is electrically connected to the first power source terminal ELVDD; wherein the substrate end of the second transistor 50 is insulated from the substrate end of the first transistor 10.

For example, fig. 6 exemplarily shows that the second transistor 50 may be the writing transistor M4 in the writing module 30, and may also be the second light-emitting control transistor M5 electrically connected between the first power terminal ELVDD and the source S of the driving transistor M1, which is not particularly limited in the embodiment of the present invention. Fig. 6 is an exemplary illustration only.

The second transistor 50 may be a P-channel transistor or an N-channel transistor, which is not specifically limited in this embodiment of the invention. When the channel type of the second transistor 50 is the same as that of the first transistor 10, the substrate end of the second transistor 50 is doped with the same type as that of the substrate end of the first transistor 10, and since the substrate end of the second transistor 50 is electrically connected to the first power supply terminal ELVDD, which is usually a fixed positive power supply signal, and the potential of the drain D of the driving transistor M1 electrically connected to the substrate end of the first transistor 10 fluctuates, fig. 7 is a partial cross-sectional structure diagram of still another pixel circuit provided by an embodiment of the present invention, and referring to fig. 7, the substrate end of the second transistor 50 and the substrate end of the first transistor 10 can be isolated from each other to avoid the substrate potential of the second transistor 50 and the substrate potential of the first transistor 10 from influencing each other and further influencing the stable operation of the second transistor 50 and the first transistor 10.

Alternatively, when the pixel circuit includes a plurality of second transistors 50, such as the writing transistor M4 and the second emission control transistor M5 in fig. 6, since the substrate terminals of the plurality of second transistors 50 are all electrically connected to the first power supply terminal ELVDD and the channel types of the plurality of second transistors 50 are the same (for example, all of the second transistors are P-channel transistors or all of the second transistors are N-channel transistors), the plurality of second transistors 50 may share the same substrate terminal, or the substrate terminals are respectively disposed for the second transistors 50, which is not specifically limited in the embodiment of the present invention.

Optionally, fig. 8 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention, as shown in fig. 8, when the pixel circuit includes a writing transistor M4, a storage capacitor C1 and a retention capacitor C2, a gate of the writing transistor M4 is electrically connected to the first control terminal SCAN1, a source of the writing transistor M4 is electrically connected to the input signal terminal DATA, and a drain of the writing transistor M4 and a gate of the driving transistor M1 are electrically connected to the second node N2; a first plate of the holding capacitor C2 is electrically connected to the first power source terminal ELVDD, and a second plate of the holding capacitor C2 and a first plate of the storage capacitor C1 are electrically connected to the third node N3; the second plate of the storage capacitor C1 is electrically connected to the second node N2.

It can be understood that the first capacitor C1 has a coupling effect, when signals are written or transmitted to the second node N2 and the third node N3 at two ends of the first capacitor C1, the first capacitor C1 can store signals according to potentials of the second node N2 and the third node N3, and the second capacitor C2 can maintain the signals stored in the first capacitor C1. When the second node N2 and the third node N3 are floating, the first capacitor C1 can make the potential of the floating node change along with the potential of the other node, and the two change amounts are the same; when the second node N2 and the third node N3 are both floated, the potential of the second node N2 and the potential of the third node N3 are both maintained under the second capacitor C2 and the first power source terminal ELVDD.

The writing transistor M4 may be a second transistor 50, a substrate end of the writing transistor M4 is electrically connected to the first power source terminal ELVDD, and a substrate end of the writing transistor M4 is insulated from a substrate end of the first transistor 10, so as to prevent a substrate end potential of the writing transistor M4 and a substrate end potential of the first transistor 10 from affecting each other, thereby affecting stable operations of the writing transistor M4 and the first transistor 10.

Optionally, with continued reference to fig. 6 or 8, when the pixel circuit further includes a second light-emitting control transistor M5, a gate of the second light-emitting control transistor M5 is electrically connected to the light-emitting control signal terminal EMIT, a source of the second light-emitting control transistor M5 is electrically connected to the first power terminal ELVDD, and a drain of the second light-emitting control transistor M5 and the source S of the driving transistor M1 are electrically connected to the fourth node N4; the fourth node N4 is coupled to the third node N3.

It can be understood that the light emitting control signal terminal electrically connected to the gate of the second light emitting control transistor M5 may be the same light emitting control signal terminal as the light emitting control signal terminal of the first light emitting control transistor M2, that is, have the same driving timing, or may be different light emitting control signal terminals, that is, have different driving timings, which is not limited in this embodiment of the present invention. Fig. 6 and 8 exemplarily show that the light emission control signal terminal electrically connected to the gate electrode of the second light emission control transistor M5 and the light emission control signal terminal of the first light emission control transistor M2 are the same light emission control signal terminal, which is the light emission control signal terminal EMIT, so as to facilitate simplification of the structure of the pixel circuit and reduce the number of signal lines for supplying signals to the pixel circuit.

Similarly, the second emission control transistor M5 may be the second transistor 50, a substrate end of the second emission control transistor M5 is electrically connected to the first power source terminal ELVDD, and the substrate end of the second emission control transistor M5 and the substrate end of the first transistor 10 are insulated from each other, so as to prevent the substrate end potential of the second emission control transistor M5 and the substrate end potential of the first transistor 10 from affecting each other and thus affecting the stable operation of the second emission control transistor M5 and the first transistor 10.

It should be noted that fig. 6 and fig. 8 only exemplarily illustrate the structure of each pixel circuit, and in the embodiment of the present invention, the structure of the pixel circuit is not limited to the above structure, and some devices may be added or reduced appropriately on the premise that the function of the pixel circuit can be realized and the core invention point of the embodiment of the present invention is met, which also belongs to the protection content of the embodiment of the present invention and is not repeated herein. The following takes fig. 8 as an example to illustrate the specific operation process of the pixel circuit according to the embodiment of the present invention.

Fig. 9 is a driving timing diagram of a pixel circuit according to an embodiment of the present invention, and with reference to fig. 8 and fig. 9, a P-channel transistor is taken as an example of each transistor in the pixel circuit.

In the initialization stage T1, the emission control signal EMIT of the emission control terminal EMIT is at an enable level (i.e., a low level), so that the emission control signal EMIT controls the second emission control transistor M5 to be in a conducting state, the first power signal ELVDD of the first power terminal ELVDD is transmitted to the fourth node N4 to initialize the fourth node N4, and the signal of the fourth node N4 is continuously transmitted to the third node N3, so that the potential of the second node N2 is the same as the potential of the third node N3, and is the first power signal ELVDD. A RESET control signal RESET of the RESET signal control terminal RESET is also changed from a high level to a low level, so that the RESET control signal RESET controls the RESET transistor M3 to be turned on, and a RESET signal VREF of the RESET signal terminal VREF is transmitted to the first node N1 through the turned-on RESET transistor M3, so as to RESET the first node N1. Meanwhile, the first control signal SCAN1 of the first control terminal SCAN1 is also changed from a high level to a low level, and the write transistor M4 is controlled to be turned on, so that the input signal terminal DATA is the initialization signal Vof, which is transmitted to the second node N2 through the turned-on write transistor M4, so as to initialize the second node N2. In addition, since the initializing signal Vof of the second node N2 is usually at a low level, and the first power signal Elvdd is usually at a high level, when the driving transistor M1 is a P-channel transistor, a difference between the initializing signal Vof at the gate of the driving transistor M1 and the first power signal Elvdd at the source S of the driving transistor M1 is smaller than the threshold voltage Vth of the driving transistor M1, so that the driving transistor M1 can be in a conducting state to prepare for the subsequent threshold compensation phase T2.

In the threshold compensation period T2, the emission control signal EMIT of the emission control terminal EMIT is changed from the enable level (i.e., low level) to the disable level (i.e., high level), so that the second emission control transistor M5 is turned off and the first power signal ELVDD of the first power terminal ELVDD is no longer transmitted to the fourth node N4. The RESET control signal RESET of the RESET signal control terminal RESET and the first control signal SCAN1 of the first control terminal SCAN1 still include a low level, the RESET transistor M3 and the write transistor M4 are both turned on, and the second node N2 is kept as the initialization signal Vof because the input signal terminal DATA is still the initialization signal Vof. Meanwhile, the driving transistor M1 is in a conducting state at the end of the previous stage, and since the voltage of the first power source terminal ELVDD is usually higher than the reset signal Vref, a path is formed from the third node N3 to the reset signal terminal Vref through the driving transistor M1 and the reset transistor M3, the potentials of the third node N3 and the fourth node N4 are continuously pulled down until a critical state (the difference between the gate-source voltage of the driving transistor M1 is equal to the threshold voltage Vth thereof) in which the driving transistor M1 is conducting is reached, i.e., the potential difference between the second node N2 and the fourth node N4 is equal to the threshold voltage Vth of the driving transistor M1, and the third node N3 and the fourth node N4 cannot be pulled down further. At this time, the potential of the fourth node N4 is Vof _ Vth, the potential of the third node N3 is the same as the potential of the fourth node N4 and is also Vof _ Vth, and the potential of the third node N3 may be stored in the storage capacitor C1. Since the potential of the third node N3 includes the threshold voltage of the driving transistor M1, the storage capacitor C1 can store the threshold voltage.

When the threshold compensation stage T2 is about to end, the input signal terminal DATA is changed from the initialization signal Vof to the DATA signal Vdata, and in order to prevent the signal of the input signal terminal DATA from being written into the second node N2 in the process of changing from the initialization signal Vof to the DATA signal Vdata, the potential of the second node N2 is affected, and the first control signal SCAN1 of the first control terminal SCAN1 may be changed from a low level to a high level in the process, so as to control the write transistor M4 to be in the off state.

After the threshold compensation stage T2 is finished, the DATA writing stage T3 is entered, at this time, the input signal terminal DATA has already become the DATA signal Vdata, the first control signal SCAN1 of the first control terminal SCAN1 changes from the high level to the low level again, the writing transistor M4 is turned on, and the DATA signal Vdata of the input signal terminal DATA can be written into the second node N2 through the turned-on writing transistor M4 and stored in the storage capacitor C1; if no signal is written into the third node N3, the potential of the third node N3 changes due to the coupling effect of the storage capacitor C1, that is, the voltage of the source S of the driving transistor M1 changes, and the driving transistor M1 is turned on again. During this period, the Reset control signal Reset of the Reset signal terminal VREF is still kept at the low level, so that the Reset transistor M3 is kept in the on state, and the Reset signal terminal VREF pulls down the potentials of the third node N3 and the fourth node N4 again until the driving transistor M1 is in the on critical state again, so that the potentials of the third node N3 and the fourth node N4 are kept at Vof-Vth. Thus, at the end of the data writing period T3, the potentials of the third node N3 and the fourth node N4 are maintained at Vof-Vth, and the potential of the second node N2 becomes Vdata.

In the light emitting period T4, the first control signal SCAN1 of the first control terminal SCAN1 changes to a high level, which controls the writing transistor M4 to be turned off, and no signal is written into the second node N2. The emission control signal EMIT of the emission control terminal EMIT changes from a non-enable level (i.e., a high level) to an enable level (i.e., a low level), the first-party control transistor M2 and the second emission control transistor M5 are both turned on, the first power signal ELVDD of the first power terminal ELVDD is written into the fourth node N4 again, the driving transistor M1 is turned on again under the control of the first power signal ELVDD and the potential of the second node N2, and at the same time, a current path is formed from the first power terminal ELVDD to the second power terminal ELVSS, the driving transistor M1 generates a driving current and starts to supply the driving current to the light emitting element 20. In addition, since the potentials of the third node N3 and the fourth node N4 are changed from Vof-Vth to Elvdd and the variation amount of the potentials is Vdd- (Vof-Vth), the potential of the second node N2 is changed with the potential variation of the third node N3 due to the coupling effect of the storage capacitor C1 and the variation amount of the potential of the second node N2 is also Vdd- (Vof-Vth), so that the potential of the second node N2 is changed from Vdata to Vdata + Vdd- (Vof-Vth), i.e., the potential of the second node N2 is Vdata + Vdd-Vof + Vth.

At this time, the driving current Id = k (Vdata + Vdd-Vof + Vth) -Vdd-Vth) ^2 generated by the driving transistor M1 according to the potentials of the gate and the source S, i.e. the generated driving current Id = k (Vdata-Vof) ^2, so that the driving current Id generated by the driving transistor M1 is independent of the threshold voltage Vth thereof, and therefore, the driving transistor M1 does not suffer from threshold drift due to aging of the driving transistor M1, process procedures and the like, and the magnitude of the driving current Id generated by the driving transistor M1 is not affected, so as to control the light emitting device 20 to emit light stably. Where k is a coefficient related to the material and size of the driving transistor M1.

Optionally, fig. 10 is a schematic structural diagram of another pixel circuit provided in an embodiment of the present invention, and as shown in fig. 10, the pixel circuit may further include: an isolation transistor M6; the gate of the isolation transistor M6 is electrically connected to the second control terminal SCAN2, and the source and the drain of the isolation transistor M6 are electrically connected to the third node N3 and the fourth node N4, respectively.

The isolation transistor M6 may be a P-channel transistor or an N-channel transistor, which is not specifically limited in this embodiment of the present invention, and fig. 10 exemplarily illustrates that the isolation transistor M6 is a P-channel transistor. The isolation transistor M6 can isolate the fourth node N4 (the node where the source S of the driving transistor M1 and the second emission control transistor M5 are electrically connected) from the gate of the driving transistor M1 in the emission phase, and can prevent the gate of the driving transistor M1 from changing with the fluctuation of the fourth node N4 in the emission phase, so as to improve the stability of the gate potential of the driving transistor M1, so that the driving transistor M1 can provide a stable driving current according to the stable potential of the gate thereof, and thus can stably emit light when the light emitting element 20 receives the stable current.

Alternatively, with continued reference to fig. 10, at least one of the write transistor M4, the second emission control transistor M5, and the isolation transistor M6 is a second transistor 50. In an alternative embodiment, the writing transistor M4, the second emission control transistor M5, and the isolation transistor M6 may all be the second transistor 50, i.e. the substrate terminals of the writing transistor M4, the second emission control transistor M5, and the isolation transistor M6 are all electrically connected to the first power terminal ELVDD and are all insulated from the substrate terminal of the first transistor 10, so as to prevent the driving transistor M4, the second emission control transistor M5, and the isolation transistor M6 from fluctuating the potential of the drain D of the driving transistor M1 (i.e. the potential of the first node N1) due to the drift of their threshold voltages and affecting the stable emission of the light emitting element 20. On the other hand, by mutually insulating the substrate ends of the writing transistor M4, the second light emission control transistor M5 and the isolation transistor M6 from the substrate end of the first transistor 10, it is also possible to avoid mutual influence of the substrate ends of the writing transistor M4, the second light emission control transistor M5, the isolation transistor M6 and the first transistor 10, and further influence on stable operation of the writing transistor M4, the second light emission control transistor M5, the isolation transistor M6 and the first transistor 10.

With continued reference to fig. 10, it can be understood that, in the light emitting phase, the light emitting control signal EMIT of the light emitting control terminal EMIT is switched between the enable level and the disable level with a set period, so that the potential of the fourth node N4 is in the oscillation change state, since the potentials of the fourth node N4 and the third node N3 are the same and change simultaneously, the potential of the third node N3 is in the oscillation change state, and then the potential of the second node N2 is affected by the coupling action of the storage capacitor C1, so that the potential of the second node N2 fluctuates, that is, the gate potential of the driving transistor M1 is in the fluctuation state, thereby affecting the stable light emission of the light emitting element 20.

Therefore, by providing the isolation transistor M6 between the third node N3 and the fourth node N4, and electrically connecting the source and the drain of the isolation transistor M6 to the third node N3 and the fourth node N4, respectively, the light emitting period T4 in fig. 9 can be divided into two periods, i.e., a first period T41 and a second period T42 (as shown in fig. 11). Fig. 11 and fig. 9 are the same as those in fig. 9, and reference may be made to the description of fig. 9, and no further description is given here, and only differences between fig. 11 and fig. 9 are exemplarily described here, and with reference to fig. 10 and fig. 11, it is to be noted that the second control terminal SCAN2 may multiplex the reset signal terminal VREF to simplify the circuit layout of the pixel circuit.

In the first phase T41 of the light emitting phase T4, the second control terminal SCAN2 controls the isolation transistor M6 to be turned on, so that the signal of the fourth node N4 can be transmitted to the third node N3, and in the threshold compensation phase T2, the isolation transistor M5 can also compensate the threshold voltage Vth of the driving transistor M1 into the storage capacitor C1. In the second stage T42 of the light-emitting stage T4, the second control signal Scan2 of the second control terminal is a high-level signal, the isolation transistor M5 is turned off, the path between the third node N3 and the fourth node N4 is disconnected, and the signal of the fourth node N4 is not transmitted to the third node N3, so that the influence on the potential of the third node N3 and thus the potential of the second node N2 due to the fluctuation of the potential of the source S of the driving transistor M1 (i.e., the potential of the fourth node N4) can be prevented. In this way, it can be ensured that the potential of the second node N2 is kept stable, so that the driving transistor M1 can generate a stable driving current to drive the light emitting element 20 to stably emit light in the second phase T42 of the light emitting phase T4.

It is understood that the first phase T41 of the light-emitting phase T4 can be a shorter time period than the second phase T42 of the light-emitting phase T4, and the time length of the first phase T41 of the light-emitting phase T4 is not particularly limited in the embodiments of the present invention on the premise that the first power signal Vdd is ensured to be written into the second node N2, so that the coupling amount with the threshold voltage Vth of the driving transistor M1 is coupled to the first node N1.

Based on the same inventive concept, an embodiment of the present invention further provides a silicon-based display panel, and fig. 12 is a schematic structural diagram of the silicon-based display panel provided in the embodiment of the present invention, as shown in fig. 12, the silicon-based display panel 2 includes a plurality of pixel circuits 1 in any of the above embodiments arranged in an array. The technical features and advantages corresponding to the pixel circuit are provided, and details not described in detail in the embodiment of the silicon-based display panel 2 may refer to the description of the pixel circuit above, and are not described herein again.

Based on the same inventive concept, an embodiment of the present invention further provides a display device, fig. 13 is a schematic structural diagram of the display device according to the embodiment of the present invention, and referring to fig. 13, the display device 3 includes the silicon-based display panel 2 according to any embodiment of the present invention. The display device 3 provided in the embodiment of the present invention may be a mobile phone as shown in fig. 13, and may also be any electronic product with a display function, including but not limited to the following categories: the touch screen system comprises a digital camera, an intelligent bracelet, intelligent glasses, a vehicle-mounted display, medical equipment, industrial control equipment, a touch interaction terminal and the like, and the embodiment of the invention is not particularly limited to this.

The above-described embodiments should not be construed as limiting the scope of the invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions may be made in accordance with design requirements and other factors. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A pixel circuit, comprising: the light-emitting device comprises a driving transistor and a light-emitting element, wherein the source electrode of the driving transistor is coupled to a first power supply end, the drain electrode of the driving transistor is electrically connected with the anode of the light-emitting element, and the cathode of the light-emitting element is electrically connected with a second power supply end;

2. The pixel circuit according to claim 1, further comprising:

the silicon-based substrate is provided with a source electrode, a drain electrode and a substrate end of the first transistor; the doping type of the substrate end of the first transistor is the same as that of the silicon-based substrate, and the doping types of the source electrode of the first transistor and the drain electrode of the first transistor are opposite to that of the substrate end of the first transistor.

3. The pixel circuit according to claim 2, wherein the first transistor further comprises a first connection electrode, a source connection structure, and a drain connection structure;

the pixel circuit further comprises a first metal layer positioned on one side of the silicon-based substrate; the first metal layer includes the first connection electrode, the source connection structure, and the drain connection structure;

in the same first transistor, the first connecting electrode is electrically connected with the substrate end through a via hole, the source electrode connecting structure is electrically connected with the source electrode, and the drain electrode connecting structure is electrically connected with the drain electrode.

4. The pixel circuit according to claim 1, further comprising: the reset transistor and the first light-emitting control transistor are both the first transistor;

the grid electrode of the reset transistor is electrically connected with the reset signal control end, and the drain electrode of the reset transistor is electrically connected with the reset signal end; the grid electrode of the first light-emitting control transistor is electrically connected with a light-emitting control signal end, and the drain electrode of the first light-emitting control transistor is electrically connected with the anode of the light-emitting element;

the source of the reset transistor, the substrate end of the reset transistor, the source of the first light emission control transistor, the substrate end of the first light emission control transistor, and the drain of the drive transistor are electrically connected to a first node.

5. The pixel circuit according to claim 4, wherein a substrate end of the first light emission control transistor and a substrate end of the reset transistor are the same substrate end.

6. The pixel circuit according to claim 1, wherein the substrate end of the driving transistor is electrically connected to the first power supply terminal;

wherein the substrate end of the driving transistor and the substrate end of the first transistor are insulated from each other.

7. The pixel circuit according to claim 1, further comprising: at least one second transistor; the drain electrode of the second transistor is electrically connected with the source electrode of the driving transistor or the grid electrode of the driving transistor; the second transistor is an at least four-terminal device; the substrate end of the second transistor is electrically connected with the first power supply end;

wherein the substrate end of the second transistor is insulated from the substrate end of the first transistor.

8. The pixel circuit of claim 7, further comprising: a write transistor, a storage capacitor, and a holding capacitor;

the grid electrode of the writing transistor is electrically connected with the first control end, the source electrode of the writing transistor is electrically connected with the input signal end, and the drain electrode of the writing transistor and the grid electrode of the driving transistor are electrically connected with the second node;

the first plate of the holding capacitor is electrically connected with the first power supply end, and the second plate of the holding capacitor is electrically connected with the first plate of the storage capacitor at a third node; the second plate of the storage capacitor is electrically connected to the second node.

9. The pixel circuit according to claim 8, further comprising: a second light emission control transistor;

a gate of the second light-emitting control transistor is electrically connected with a light-emitting control signal end, a source of the second light-emitting control transistor is electrically connected with the first power supply end, and a drain of the second light-emitting control transistor and a source of the driving transistor are electrically connected with a fourth node; the fourth node is coupled to the third node.

10. The pixel circuit according to claim 9, further comprising: an isolation transistor;

and the grid electrode of the isolation transistor is electrically connected with the second control end, and the source electrode and the drain electrode of the isolation transistor are respectively and electrically connected with the third node and the fourth node.

11. The pixel circuit according to claim 10, wherein at least one of the writing transistor, the second emission control transistor, and the isolation transistor is the second transistor.

12. A silicon-based display panel, comprising: a plurality of pixel circuits according to any one of claims 1-11 arranged in an array.

13. A display device, comprising: the silicon-based display panel of claim 12.