CN115329719B - InP-based terahertz HEMT transistor small-signal model - Google Patents
InP-based terahertz HEMT transistor small-signal model Download PDFInfo
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Abstract
The invention belongs to the field of semiconductor devices, and particularly provides an InP-based terahertz HEMT transistor small-signal model which is used for solving the problems that a parasitic parameter element in a traditional small-signal model lacks physical significance and does not consider skin effect. According to the invention, through the creative design of parasitic elements in the model, each parasitic element has a definite physical significance, and the skin effect impedance is introduced into the grounding hole; meanwhile, combining the transistor geometric figures into 4 groups according to a progressive relation, corresponding to 4 parasitic element submodels, performing step-by-step modeling simulation on the 4 groups of geometric figures through three-dimensional electromagnetic field simulation software, and sequentially extracting parameter values corresponding to all parasitic elements based on a simulation result; based on the method, the modeling time can be effectively saved, and the simulation precision of the small-signal model is remarkably improved; in addition, compared with the traditional small-signal model, the number of parasitic elements is increased, and the simulation precision of the small-signal model can be effectively improved.
Description
Technical Field
The invention belongs to the field of semiconductor devices, relates to a microelectronic device technology, further relates to a small-signal equivalent circuit model of an HEMT (high Electron mobility transistor), and particularly provides an InP-based terahertz HEMT small-signal model.
Background
The InP material has the characteristics of high electron mobility, high saturation drift velocity and the like, compared with the GaN-based HEMT transistor, the InP material device has a better noise coefficient, and compared with the GaAs-based HEMT transistor, the InP material has higher electron mobility and can be applied to a higher frequency band; therefore, the InP-based HEMT transistor is suitable for designing a low-noise amplifier with terahertz frequency, and has great significance in the aspects of electronic warfare, phased array radar, satellite communication, radio astronomy and the like of terahertz frequency.
The small signal equivalent circuit model (short for small signal model) is a link between circuit design and device characteristics, and after modeling is carried out on a device, the model can be embedded into EDA software to carry out circuit simulation and design. For the HEMT transistor device, a conventional small-signal model is shown in fig. 22, and a corresponding conventional parasitic parameter extraction method is to perform parameter fitting by using a cold tube state with gate voltage pinch-off and leakage voltage of 0V, and has the following limitations: 1. only the equivalent element is adopted to fit the test data, the physical significance is to be further improved, and the parasitic effects of different parts of the geometric figure cannot be clearly distinguished; 2. the simulation precision is poor due to the fact that the number of equivalent elements is small; 3. some special physical effects, such as skin effect, are ignored; the above limitation is particularly significant in the terahertz frequency band.
Disclosure of Invention
The invention aims to provide an InP-based terahertz HMET transistor small-signal model aiming at the problems that a parasitic element in the traditional small-signal model lacks physical significance and does not consider skin effect; the core creation of the invention lies in the creative design of parasitic elements in the model, wherein each parasitic element has definite physical significance, and the grounding hole introduces skin effect impedance; meanwhile, combining the transistor geometric figures into 4 groups according to the progressive relation from part to the whole, respectively corresponding to 4 parasitic element submodels, performing step-by-step modeling simulation on the 4 groups of geometric figures through three-dimensional electromagnetic field simulation software, and sequentially extracting the parameter values of corresponding parasitic elements based on the simulation result; based on the method, the modeling time can be effectively saved, and the simulation precision of the small-signal model is remarkably improved.
In order to achieve the purpose, the invention adopts the technical scheme that:
an InP-based terahertz HEMT transistor small-signal model, comprising: a parasitic element and an intrinsic element, wherein the parasitic element comprises: parasitic resistance outside gridR g1 And a parasitic resistance in the middle of the gridR g2 Internal parasitic resistance of gridR g_finger External parasitic capacitance of gridC g And a parasitic capacitance in the middle of the gridC gs_in Internal parasitic capacitance of gridC gs_finger Parasitic inductance of grid electrodeL g_finger External parasitic resistance of drain electrodeR d1 Middle parasitic resistance of drainR d2 Internal parasitic resistance of drainR d_finger External parasitic capacitance of drainC d Middle part parasitic capacitance of drain electrodeC ds_in Internal parasitic capacitance of drainC ds_finger Parasitic inductance of drain electrodeL d_finger Gate-drain parasitic capacitanceC gd_finger Parasitic inductance of source electrodeL s Source skin effect impedanceZ rf ；
Wherein the gate external parasitic resistanceR g1 Connected between an external gate node G and a middle gate node G1, the gate middle parasitic resistanceR g2 And gate external parasitic capacitanceC g Connected in series between the middle gate node G1 and the external source node S, and the internal parasitic resistance of the gateR g_finger Parasitic inductance with drainL d_finger Connected in series between a middle gate node G1 and an intrinsic gate node G2, the gate middle parasitic capacitanceC gs_in Connected between the middle gate node G1 and the intrinsic source node S1, the internal parasitic capacitance of the gateC gs_finger Connected between the intrinsic gate node G2 and the intrinsic source node S1, and the external parasitic drain resistorR d1 Connected between an external drain node D and a middle drain node D1, a parasitic resistance in the middle of the drainR d2 And the external parasitic capacitance of the drainC d Connected between the middle drain electrode node D1 and the external source electrode node S after being connected in series, and the internal parasitic resistance of the drain electrodeR d_finger Parasitic inductance with drainL d_finger Connected in series between the middle drain node D1 and the intrinsic drain node D2, and the parasitic capacitance in the middle of the drainC ds_in Connected between the middle drain node D1 and the intrinsic source node S1, the internal parasitic capacitance of the drainC ds_finger Connected between an intrinsic drain node D2 and an intrinsic source node S1, the gate-drain parasitic capacitanceC gd_finger Connected between an intrinsic gate node G2 and an intrinsic drain node D2, the source parasitic inductanceL s And source skin effect impedanceZ rf Connected in series between the external source node S and the intrinsic source node S1.
Further, the intrinsic element includes: gate-source intrinsic capacitanceC gs Gate source intrinsic resistanceR i Gate-drain intrinsic capacitanceC gd Gate drain intrinsic resistanceR gd Drain-source intrinsic capacitanceC ds Drain source intrinsic resistanceR ds And a voltage controlled current sourceVCCSWherein the gate-source intrinsic capacitanceC gs And gate source intrinsic resistanceR i Connected in series between an intrinsic gate node G2 and an intrinsic source node S1, the gate-drain intrinsic capacitanceC gd And gate drain intrinsic resistanceR gd Connected in series between an intrinsic gate node G2 and an intrinsic drain node D2, the drain-source intrinsic capacitanceC ds Drain source intrinsic resistanceR ds And a voltage controlled current sourceVCCSConnected in parallel between the intrinsic drain node D2 and the intrinsic source node S1.
Further, the parasitic parameter extraction process in the parasitic element is as follows:
Step 3, modeling the partial structure of the transistor in three-dimensional electromagnetic simulation software, wherein the modeling comprises the following steps: the substrate part, the back gold part positioned on the lower surface of the substrate, the dielectric layer part positioned on the upper surface of the substrate, the grid electrode transmission line part positioned on the upper surface of the dielectric layer, the drain electrode transmission line part, the two source electrode parts and the source electrode grounding hole; then, two-port three-dimensional electromagnetic simulation is carried out on the transistor in the full frequency band, Y parameters are calculated, and then parasitic capacitance in the middle of the grid electrode is calculated according to the Y parametersC gs_in Middle part parasitic capacitance of drain electrodeC ds_in ；
And 4, modeling the complete structure of the transistor in three-dimensional electromagnetic simulation software, wherein the modeling comprises the following steps: the substrate part, the back gold part positioned on the lower surface of the substrate, the dielectric layer part positioned on the upper surface of the substrate, the grid transmission line part, the grid finger part, the drain transmission line part, the drain metal strip part, the two source electrode parts and the source electrode grounding hole which are positioned on the upper surface of the dielectric layer; then, two-port three-dimensional electromagnetic simulation is carried out on the transistor in the full frequency band, Y parameters are calculated, and then the grid-drain parasitic capacitance is calculated according to the Y parametersC gd_finger Internal parasitic capacitance of drainC ds_finger Internal parasitic capacitance of gridC gs_finger ；
Step 5, setting:R g1 =λR Tg 、R g2 =(1-λ)R Tg ，R d1 =φR Td 、R d2 =(1-φ)R Td ，λandφall are distribution ratios with the value range of 0 to 1,λandφis set to 0.5; at the same time, the parasitic resistance in the grid is setR g_finger Parasitic inductance of grid electrodeL g_finger Internal parasitic resistance of drainR d_finger Parasitic inductance of drain electrodeL d_finger Is 0; and optimizing all parasitic parameters according to the parasitic cost function to obtain final parasitic parameters.
Further, in step 1, the parasitic resistance outside the gateR g1 And the parasitic resistance in the middle of the gridR g2 Total resistance ofR Tg External parasitic capacitance of gridC g External parasitic resistance of drainR d1 And the parasitic resistance in the middle of the drainR d2 Total resistance ofR Td External parasitic capacitance of drain electrodeC d The following equation is satisfied:
wherein,Z 11 、Z 22 in turn, represent the corresponding terms in the Z parameter,fthe frequency is represented by a frequency-dependent signal,f max representing the highest frequency.
Further, in step 2, the parasitic inductance of the source electrodeL s Source side of the transistorSkin effect impedanceZ rf The following equation is satisfied:
wherein,Z 11 represents the corresponding item in the Z parameter,fthe frequency is represented by a frequency-dependent signal,f max representing the highest frequency.
Furthermore, in step 3, the parasitic capacitance in the middle of the gateC gs_in Middle part parasitic capacitance of drain electrodeC ds_in The following equation is satisfied:
wherein,Y 11 、Y 22 in turn, represent the corresponding terms in the Y parameter,fthe frequency is represented by a frequency-dependent signal,f min representing the lowest frequency.
Furthermore, in step 4, the parasitic capacitance of the gate and the drainC gd_finger Internal parasitic capacitance of drainC ds_finger Internal parasitic capacitance of gridC gs_finger The following equation is satisfied:
wherein,Y 11 、Y 22 、Y 12 in turn, represent the corresponding terms in the Y parameter,fthe frequency is represented by a frequency-dependent variable,f min representing the lowest frequency.
Further, in step 5, the parasitic cost function is:
wherein,J i,j andK i,j are all preset weight values, and are all preset weight values,S a (i,j) A circuit simulation result representing the parasitic element,S b (i,j) And representing a three-dimensional electromagnetic simulation result.
Further, the extraction process of the intrinsic parameters of the intrinsic elements is as follows:
measuring S parameters of the transistor under all bias conditions in a full frequency band, and calculating to obtain corresponding Y parameters according to the S parameters; based on known parasitic parameters, the full-band test Y parameters of the transistor are de-embedded to obtain intrinsic Y parameters Y int (ii) a Gate-source intrinsic capacitanceC gs Gate source intrinsic resistanceR i Gate-drain intrinsic capacitanceC gd Gate drain intrinsic resistanceR gd Drain-source intrinsic capacitanceC ds Drain source intrinsic resistanceR ds Voltage controlled current sourceVCCSThe following equation is satisfied:
wherein,g m representative voltage controlled current sourceVCCSThe transconductance of (a) is,ωrepresenting angular frequency, tau representing voltage-controlled current sourceVCCSDelay of (2);
and optimizing all intrinsic parameters according to the intrinsic cost function to obtain the final intrinsic parameters.
Further, the intrinsic cost function is:
wherein,J i,j andK i,j and is also a preset weight, and the weight,S c (i,j) A circuit simulation result representing a small-signal model,S d (i,j) The test results are shown.
Compared with the prior art, the invention has the beneficial results that:
the invention provides an InP-based terahertz HEMT transistor small-signal model, which is characterized in that each parasitic element has definite physical significance by creative design of a parasitic element part in the small-signal model, and skin effect impedance is introduced; specifically, the method comprises the following steps: using parasitic resistances outside the gateR g1 Middle parasitic resistance of gridR g2 And gate external parasitic capacitanceC g Common simulation of gate transmission line parasitic effect by using external parasitic resistance of drainR d1 Middle parasitic resistance of drainR d2 And the external parasitic capacitance of the drainC d Common simulation of drain transmission line parasitic effect, and source parasitic inductanceL s And source skin effect impedanceZ rf Simulating parasitic effect of source electrode grounding hole by using parasitic capacitance in the middle of grid electrodeC gs_in Simulating the coupling effect of the gate transmission line and the source grounding hole by using the parasitic capacitance in the middle of the drainC ds_in Analog drain transmission line and sourceCoupling effect of grounding hole by using parasitic resistance in gridR g_finger Parasitic inductance of grid electrodeL g_finger Simulating parasitic effect of grid bar by using parasitic resistance in drainR d_finger Drain parasitic inductanceL d_finger Simulating parasitic effect of drain electrode in active region by using parasitic capacitance in grid electrodeC gs_finger Simulating the coupling between grid and source by using the parasitic capacitance in drainC ds_finger Simulating the coupling between the drain and the source of the active region by using the parasitic capacitance of the gate and the drainC gd_finger Simulating coupling between the grid and the drain; furthermore, according to the progressive relationship from part to the whole, the transistor geometric figures are combined into 4 groups and respectively correspond to 4 parasitic element submodels, the 4 groups of geometric figures are subjected to step-by-step modeling simulation through three-dimensional electromagnetic field simulation software, and parameter values corresponding to all parasitic elements are sequentially extracted based on the simulation result, so that the modeling time is effectively saved, and the simulation precision of the small-signal model is remarkably improved; in addition, compared with the traditional small-signal model, the small-signal model has the advantages that the number of parasitic parameter elements is increased, and the simulation precision of the small-signal model can be effectively improved.
Drawings
Fig. 1 is a schematic view of a topological structure of an InP-based terahertz HEMT transistor small-signal model in the present invention.
Fig. 2 is a schematic structural diagram of a first parasitic element submodel in the small-signal model shown in fig. 1.
Fig. 3 is a schematic structural diagram of a second parasitic element sub-model in the small-signal model shown in fig. 1.
Fig. 4 is a schematic structural diagram of a third parasitic element submodel in the small-signal model shown in fig. 1.
Fig. 5 is a schematic structural diagram of a fourth parasitic element submodel in the small-signal model shown in fig. 1.
FIG. 6 is a three-dimensional electromagnetic simulation model corresponding to the first parasitic element sub-model shown in FIG. 2.
FIG. 7 is a three-dimensional electromagnetic simulation model corresponding to the second parasitic element submodel shown in FIG. 3.
FIG. 8 is a three-dimensional electromagnetic simulation model corresponding to the third parasitic element sub-model shown in FIG. 4.
FIG. 9 is a three-dimensional electromagnetic simulation model corresponding to the fourth parasitic element submodel shown in FIG. 5.
FIG. 10 shows the circuit simulation result and the three-dimensional electromagnetic simulation result S of the parasitic element in the embodiment of the present invention 11 Parameter comparison graph.
FIG. 11 shows the circuit simulation result and the S of the three-dimensional electromagnetic simulation result of the parasitic element in the embodiment of the present invention 12 Parameter comparison graph.
FIG. 12 shows the circuit simulation result and the three-dimensional electromagnetic simulation result S of the parasitic element in the embodiment of the present invention 21 Parameter comparison graph.
FIG. 13 shows the circuit simulation result and the S of the three-dimensional electromagnetic simulation result of the parasitic element in the embodiment of the present invention 22 Parameter comparison graph.
FIG. 14 is a diagram illustrating the S of the circuit simulation result and the test result of the small-signal model under the cold tube condition in the embodiment of the present invention 11 Parameter comparison graph.
FIG. 15 is a S of a circuit simulation result and a test result of a small-signal model in a cold tube state according to an embodiment of the present invention 12 Parameter comparison graph.
FIG. 16 is a S of a circuit simulation result and a test result of the small-signal model under the cold tube state in the embodiment of the present invention 21 Parameter comparison graph.
FIG. 17 is a S of a circuit simulation result and a test result of the small-signal model under the cold tube state in the embodiment of the present invention 22 And comparing the parameters with the graph.
FIG. 18 is a diagram illustrating the S of the circuit simulation result and the test result of the small signal model under the common amplification state in the embodiment of the present invention 11 And comparing the parameters with the graph.
FIG. 19 is a diagram showing S of a circuit simulation result and a test result of a small signal model under a common amplification state according to an embodiment of the present invention 12 Parameter comparison graph.
FIG. 20 is a S of the circuit simulation result and the test result of the small signal model under the normal amplification state in the embodiment of the present invention 21 And comparing the parameters with the graph.
FIG. 21 is a S of the circuit simulation result and the test result of the small signal model under the normal amplification state in the embodiment of the present invention 22 And comparing the parameters with the graph.
Fig. 22 is a schematic view of a topology of a small-signal model of a conventional HEMT transistor.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the present invention will be further described in detail with reference to the accompanying drawings and embodiments.
The present embodiment provides an InP-based terahertz HEMT transistor small-signal model, which has a structure as shown in fig. 1, and includes: a parasitic element and an intrinsic element having the following nodes: an external gate node G, a middle gate node G1, an intrinsic gate node G2, an external drain node D, a middle drain node D1, an intrinsic drain node D2, an external source node S, an intrinsic source node S1; more specifically:
the intrinsic element includes: gate-source intrinsic capacitanceC gs Gate source intrinsic resistanceR i Gate-drain intrinsic capacitanceC gd Gate drain intrinsic resistanceR gd Drain-source intrinsic capacitanceC ds Drain source intrinsic resistanceR ds And a voltage controlled current sourceVCCSWherein the gate-source intrinsic capacitanceC gs And gate source intrinsic resistanceR i Connected in series between an intrinsic gate node G2 and an intrinsic source node S1, the gate-drain intrinsic capacitanceC gd And gate drain intrinsic resistanceR gd Connected in series between an intrinsic gate node G2 and an intrinsic drain node D2, the drain-source intrinsic capacitanceC ds Drain source intrinsic resistanceR ds And a voltage controlled current sourceVCCSConnected between the intrinsic drain node D2 and the intrinsic source node S1 after being connected in parallel;
the parasitic element includes: parasitic resistance outside gridR g1 Middle parasitic resistance of gridR g2 Parasitic current inside the gridResistance deviceR g_finger External parasitic capacitance of gridC g Middle parasitic capacitance of gridC gs_in Internal parasitic capacitance of gridC gs_finger Parasitic inductance of grid electrodeL g_finger External parasitic resistance of drainR d1 Middle parasitic resistance of drainR d2 Internal parasitic resistance of drain electrodeR d_finger External parasitic capacitance of drainC d Middle part parasitic capacitance of drain electrodeC ds_in Internal parasitic capacitance of drainC ds_finger Parasitic inductance of drain electrodeL d_finger Gate-drain parasitic capacitanceC gd_finger Parasitic inductance of source electrodeL s Source skin effect impedanceZ rf ；
Parasitic resistance outside the grid in the parasitic elementR g1 Connected between an external gate node G and a middle gate node G1, the gate middle parasitic resistanceR g2 And gate external parasitic capacitanceC g Connected in series between the middle gate node G1 and the external source node S, and the internal parasitic resistance of the gateR g_finger And parasitic inductance of drain electrodeL d_finger Connected in series between a middle gate node G1 and an intrinsic gate node G2, the gate middle parasitic capacitanceC gs_in Connected between the middle gate node G1 and the intrinsic source node S1, the internal parasitic capacitance of the gateC gs_finger Connected between the intrinsic gate node G2 and the intrinsic source node S1, and the external parasitic drain resistorR d1 Connected between an external drain node D and a middle drain node D1, a parasitic resistance in the middle of the drainR d2 And drain external parasitic capacitanceC d Connected between the middle drain electrode node D1 and the external source electrode node S after being connected in series, and the internal parasitic resistance of the drain electrodeR d_finger And parasitic inductance of drain electrodeL d_finger Connected in series and then connectedConnected between the middle drain node D1 and the intrinsic drain node D2, the drain middle parasitic capacitanceC ds_in Connected between the middle drain node D1 and the intrinsic source node S1, the internal parasitic capacitance of the drainC ds_finger Connected between an intrinsic drain node D2 and an intrinsic source node S1, the gate-drain parasitic capacitanceC gd_finger Connected between an intrinsic gate node G2 and an intrinsic drain node D2, the source parasitic inductanceL s And source skin effect impedanceZ rf Connected in series between the external source node S and the intrinsic source node S1.
The core creation of this embodiment lies in: the inventive design of the parasitic element part in the small signal model is characterized in that each parasitic element has definite physical significance and introduces skin effect impedance; meanwhile, combining the transistor geometric figures into 4 groups according to the progressive relation from part to the whole, respectively corresponding to 4 parasitic element submodels, performing step-by-step modeling simulation on the 4 groups of geometric figures through three-dimensional electromagnetic field simulation software, and sequentially extracting parameter values corresponding to each parasitic element based on the simulation result; more specifically:
first parasitic element submodel: the gate and drain external parasitic parameters, the structure of which is shown in FIG. 2, include the gate external parasitic resistanceR g1 Middle parasitic resistance of gridR g2 External parasitic capacitance of gridC g External parasitic resistance of drain electrodeR d1 Middle parasitic resistance of drainR d2 External parasitic capacitance of drain electrodeC d The node comprises an external grid node G, an external drain node D and an external source node S; parasitic resistance outside gridR g1 Middle parasitic resistance of gridR g2 And gate external parasitic capacitanceC g Simulating the parasitic effect of the grid transmission line together; parasitic resistance outside drainR d1 Middle parasitic resistance of drainR d2 And the external parasitic capacitance of the drainC d Common analog drainTransmission line parasitics;
second parasitic element submodel: the parasitic source external parameters, the structure of which is shown in FIG. 3, include parasitic source inductanceL s Source skin effect impedanceZ rf The included nodes include an external source node S and an intrinsic source node S1; it should be noted that there are two sources in the overall transistor structure, and in this model, only a single source structure is represented, so the parasitic source inductance is 2L s A source skin effect impedance of 2Z rf Parasitic inductance of source 2L s And source skin effect impedance 2Z rf Simulating parasitic effect of one source electrode grounding hole, wherein the parasitic effect of two source electrode grounding holes is in parallel connection in a small signal model, namely combining and equivalent to a source electrode parasitic inductanceL s And source skin effect impedanceZ rf ；
Third parasitic element submodel: the structure of the external parasitic parameters of the gate, the drain and the source is shown in fig. 4, and comprises a first parasitic element submodel: parasitic resistance outside gridR g1 Middle parasitic resistance of gridR g2 External parasitic capacitance of gridC g External parasitic resistance of drainR d1 Middle parasitic resistance of drainR d2 External parasitic capacitance of drainC d Second parasitic element submodel: parasitic inductance of source electrodeL s Source skin effect impedanceZ rf And parasitic capacitance in the middle of the gateC gs_in And the parasitic capacitance in the middle of the drainC ds_in (ii) a The included nodes include an external gate node G, a middle gate node G1, an external drain node D, a middle drain node D1, an external source node S and an intrinsic source node S1; parasitic capacitance in the middle of gridC gs_in Simulating the coupling effect between the gate transmission line and the source grounding hole, and the parasitic capacitance in the middle of the drainC ds_in Simulating the coupling effect of a drain electrode transmission line and a source electrode grounding hole;
fourth parasitic element submodel: the overall parasitic parameters, the structure of which is shown in fig. 5, include a third parasitic element submodel: parasitic resistance outside gridR g1 Middle parasitic resistance of gridR g2 External parasitic capacitance of gridC g External parasitic resistance of drainR d1 Middle parasitic resistance of drainR d2 External parasitic capacitance of drainC d Parasitic inductance of source electrodeL s Source skin effect impedanceZ rf Middle parasitic capacitance of gridC gs_in And the parasitic capacitance in the middle of the drainC ds_in And gate internal parasitic capacitanceC gs_finger Internal parasitic resistance of gridR g_finger Parasitic inductance of grid electrodeL g_finger Internal parasitic capacitance of drainC ds_finger Internal parasitic resistance of drainR d_finger Drain parasitic inductanceL d_finger And gate-drain parasitic capacitanceC gd_finger (ii) a Including all nodes, in which the parasitic resistance inside the gateR g_finger Parasitic inductance of grid electrodeL g_finger Simulating parasitic effect of the grid; parasitic resistance in drainR d_finger Parasitic inductance of drain electrodeL d_finger Simulating the parasitic effect of the drain electrode of the active region; parasitic capacitance inside gridC gs_finger Coupling the analog grid and the source; internal parasitic capacitance of drainC ds_finger Simulating the coupling between the drain electrode and the source electrode of the active region; parasitic capacitance of gate and drainC gd_finger Simulating the coupling between the grid and the drain;
meanwhile, the 4 parasitic element submodels include all connecting lines between corresponding elements in the small-signal model, and all connecting lines between elements and nodes.
Further, the embodiment also provides a parameter extraction process of the small signal model, and specifically takes a 35nm inp hemt transistor as an example for explanation, the test frequency band is 10 to 110ghz, and the test is specifically implemented by segmenting the existing 10 to 66ghz test system and 75 to 110ghz test system; the method specifically comprises the following steps:
the model corresponds to a first parasitic element submodel, and circuit analysis is carried out on the first parasitic element submodel to obtain the external parasitic resistance of the gridR g1 And the parasitic resistance in the middle of the gridR g2 Total resistance ofR Tg External parasitic capacitance of gridC g External parasitic resistance of drain electrodeR d1 And the parasitic resistance in the middle of the drainR d2 Total resistance ofR Td External parasitic capacitance of drain electrodeC d Calculated from the following equation:
wherein,Z 11 、Z 22 in turn representing the corresponding terms in the Z parameter,fthe frequency is represented by a frequency-dependent variable,f max representing the highest frequency (110 GHz), the Im () function represents taking the real part of the result, and the Re () function represents taking the imaginary part of the result;
the model is corresponding to a second parasitic element submodel, and circuit analysis is carried out on the second parasitic element submodel to obtain the source parasitic inductanceL s Source skin effect impedanceZ rf Calculated from the following equation:
wherein,Z 11 represents the corresponding item in the Z parameter,fthe frequency is represented by a frequency-dependent variable,f max represents the highest frequency;
step 3, modeling the partial structure of the transistor in three-dimensional electromagnetic simulation software, wherein the modeling comprises the following steps: a substrate portion, a back gold portion located on the lower surface of the substrate, a dielectric layer portion located on the upper surface of the substrate, a gate transmission line portion, a drain transmission line portion, two source portions and a source ground hole located on the upper surface of the dielectric layer, as shown in fig. 8; then carrying out two-port three-dimensional electromagnetic simulation on the transistor in the full frequency band, and calculating S parameters, Y parameters and Z parameters of the transistor, wherein the first port is set as a grid transmission line edge and a back metal edge, and the second port is set as a drain transmission line edge and a back metal edge;
the model corresponds to a third parasitic element submodel, and circuit analysis is carried out on the third parasitic element submodel to obtain the parasitic capacitance in the middle of the gridC gs_in Middle part parasitic capacitance of drain electrodeC ds_in Calculated from the following equation:
wherein,Y 11 、Y 22 in turn representing the corresponding items in the Y parameter,fthe frequency is represented by a frequency-dependent signal,f min represents the lowest frequency; specifically, the capacitance value is calculated at a frequency of 10GHz in the present embodiment for the following two reasons: 1. under extremely low frequency (close to direct current), a certain error exists in the simulation of the three-dimensional simulation software on the inductance, and 2, under very high frequency, the parasitic inductance of the source electrodeL s The influence of (2) is large; therefore, the capacitance value is generally extracted at the low-end frequency (10 GHz) with smaller simulation error of the three-dimensional electromagnetic field;
and 4, modeling the complete structure of the transistor in three-dimensional electromagnetic simulation software, wherein the modeling comprises the following steps: a substrate portion, a back metal portion located on the lower surface of the substrate, a dielectric layer portion located on the upper surface of the substrate, a gate transmission line portion, a gate finger portion, a drain transmission line portion, a drain metal strip portion, two source portions and a source grounding hole located on the upper surface of the dielectric layer, as shown in fig. 9; then carrying out two-port three-dimensional electromagnetic simulation on the transistor in the full frequency band, and calculating S parameters, Y parameters and Z parameters of the transistor, wherein the first port is set as a gate finger edge and a back metal edge, and the second port is set as a drain electrode transmission line edge and a back metal edge;
the model corresponds to a fourth parasitic element submodel, and circuit analysis is carried out on the fourth parasitic element submodel to obtain the gate-drain parasitic capacitanceC gd_finger Internal parasitic capacitance of drainC ds_finger Internal parasitic capacitance of gridC gs_finger Calculated from the following equation:
wherein,Y 11 、Y 22 、Y 12 in turn, represent the corresponding terms in the Y parameter,fthe frequency is represented by a frequency-dependent signal,f min represents the lowest frequency; specifically, the capacitance value is calculated at a frequency of 10GHz in this embodiment;
step 5, solving all equations from step 1 to step 4 to obtain the external parasitic capacitance of the gridC g Middle parasitic capacitance of gridC gs_in Internal parasitic capacitance of gridC gs_finger External parasitic capacitance of drainC d Middle part parasitic capacitance of drain electrodeC ds_in Internal parasitic capacitance of drainC ds_finger Gate-drain parasitic capacitanceC gd_finger Parasitic inductance of source electrodeL s Source skin effect impedanceZ rf And a parasitic resistance outside the gateR g1 And the parasitic resistance in the middle of the gridR g2 Total resistance ofR Tg External parasitic resistance of drainR d1 And the parasitic resistance in the middle of the drainR d2 Total resistance ofR Td (ii) a Therefore, the invention provides:R g1 =λR Tg 、R g2 =(1-λ)R Tg ，R d1 =φR Td 、R d2 =(1-φ)R Td ，λand withφThe distribution ratio of the average value range of 0 to 1,λandφthe initial value of (3) is 0.5; at the same time, the parasitic resistance in the grid electrodeR g_finger Parasitic inductance of grid electrodeL g_finger Internal parasitic resistance of drainR d_finger Parasitic inductance of drain electrodeL d_finger Setting the initial value to be 0; optimizing all parasitic parameters according to a parasitic cost function to obtain final parasitic parameter values;
the parasitic cost function is:
wherein,J i,j andK i,j are all preset weight values, and are all preset weight values,J i,j =0.125、K i,j =0.125；S a (i,j) A circuit simulation result (S parameter) representing a parasitic element,S b (i,j) The three-dimensional electromagnetic simulation result (cold tube state: biased at V gs =-0.3V、V ds = 0V); in the cost function, the former term represents an amplitude error, the latter term represents a phase error, and the parameter optimization process based on the cost function is common knowledge in the art and is not described herein again;
typical values of the parasitic parameters finally extracted for the 35nm InP HEMT transistor in this embodiment are shown in table 1:
TABLE 1
Based on the parasitic parameters, the comparison between the circuit simulation result of the parasitic element and the three-dimensional electromagnetic simulation result is shown in fig. 10-13, which are S in sequence 11 、S 12 、S 21 、S 22 A parameter; as can be seen from the figure, the parasitic element in the embodiment can better simulate the geometric three-dimensional electromagnetic simulation S parameter of the transistor;
step 6, measuring S parameters of the transistor under full bias in a full frequency band, and calculating to obtain corresponding Y parameters and Z parameters according to the S parameters; it should be noted that: the input, output and ground reference surfaces are respectively G, D and S points, and the Y parameter and the Z parameter respectively comprise parameters due to the inclusion of 2 test portsY 11 、Y 12 、Y 21 、Y 22 And parametersZ 11 、Z 12 、Z 21 、Z 22 The specific meaning of each parameter is common knowledge in the art, and is not described herein again, nor is the process of calculating the S parameter, the Y parameter, and the Z parameter described herein;
step 7, based on the parasitic parameters of the parasitic elements extracted in the steps 1 to 5, the transistor full-band test Y parameters are subjected to de-embedding to obtain intrinsic Y parameters Y int (ii) a After de-embedding, the input, output, and ground reference planes become G2, D2, and S1, respectively, and contain only intrinsic elements: gate-source intrinsic capacitanceC gs Gate source intrinsic resistanceR i Gate-drain intrinsic capacitanceC gd Gate drain intrinsic resistanceR gd Drain-source intrinsic capacitanceC ds Drain source intrinsic resistanceR ds Voltage controlled current sourceVCCSThe intrinsic parameters satisfy the following equations:
wherein,g m representing a voltage controlled current sourceVCCSThe transconductance of (a) is,ωrepresenting angular frequency, tau representing voltage-controlled current sourceVCCSDelay of (2);
wherein,J i,j andK i,j and is also a preset weight, and the weight,J i,j =0.125、K i,j =0.125；S c (i,j) Circuit simulation results (S-parameters) representing a small-signal model,S d (i,j) The test results (S-parameters) are indicated.
The transistor usually has two states of cold tube and amplification, and the typical cold tube (V) is selected below gs =-0.3V、V ds = 0V), normal amplification state (V) gs =0.1V、V ds = 0.4V) bias point for validation;
(1) Cold pipe (V) gs =-0.3V、V ds = 0V) bias point verification;
for the 35nm InP HEMT transistor in this example, the measured frequency ranges are 10 to 66GHz and 75 to 110GHz, in a cold tube (V) gs =-0.3V、V ds = 0V), typical values of the intrinsic parameters obtained by the final extraction are shown in table 2:
TABLE 2
Circuit simulation results and test results of small signal model based on parasitic parameters in table 1 and intrinsic parameters in table 2For example, as shown in FIGS. 14 to 17, S is provided in sequence 11 、S 12 、S 21 、S 22 A parameter; as can be seen from the figure, the small signal model of the invention obtains higher precision below 66GHz, and even if the error is increased to a certain extent above 75GHz, the trend is still consistent; it should be noted that, because the existing test system cannot directly cover 10 to 110GHz, two sets of systems of 10 to 66GHz and 75 to 110GHz are adopted for testing, and compared with the system of 10 to 66GHz, the test error of the system of 75 to 110GHz is relatively large and is introduced by the system itself; therefore, the small-signal model obtains higher precision and can better simulate the performance of a device in a cold tube state;
(2) Amplified state (V) gs =0.1V、V ds = 0.4V) bias point validation;
for the InP HEMT transistor with the wavelength of 35nm in the embodiment, the measured frequency ranges are 10 to 66GHz and 75 to 110GHz, and the InP HEMT transistor is in a common amplifier state (V) gs =0.1V、V ds = 0.4V), typical values of the intrinsic parameters obtained by the final extraction are shown in table 3:
TABLE 3
Based on the parasitic parameters in Table 1 and the intrinsic parameters in Table 3, the comparison between the circuit simulation result and the test result of the small signal model is shown in FIGS. 18-21, which are S in sequence 11 、S 12 、S 21 、S 22 A parameter; as can be seen from the figure, the small-signal model of the invention also obtains higher precision, and can better simulate the performance of the device under the state of an amplifier;
in conclusion, the small-signal model of the InP-based terahertz HMET transistor is provided, the modeling time is effectively saved, and the simulation accuracy of the small-signal model is remarkably improved.
While the invention has been described with reference to specific embodiments, any feature disclosed in this specification may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise; all of the disclosed features, or all of the method or process steps, may be combined in any combination, except mutually exclusive features and/or steps.
Claims (10)
1. An InP-based terahertz HEMT transistor small-signal model comprising: a parasitic element and an intrinsic element, wherein the parasitic element comprises: parasitic resistance outside gridR g1 Middle parasitic resistance of gridR g2 Internal parasitic resistance of gridR g_finger External parasitic capacitance of gridC g Middle parasitic capacitance of gridC gs_in Internal parasitic capacitance of gridC gs_finger Parasitic inductance of grid electrodeL g_finger External parasitic resistance of drainR d1 Middle parasitic resistance of drainR d2 Internal parasitic resistance of drainR d_finger External parasitic capacitance of drainC d Middle part parasitic capacitance of drain electrodeC ds_in Internal parasitic capacitance of drainC ds_finger Parasitic inductance of drain electrodeL d_finger Gate-drain parasitic capacitanceC gd_finger Parasitic inductance of source electrodeL s Source skin effect impedanceZ rf ；
Wherein the gate external parasitic resistanceR g1 Connected between an external gate node G and a middle gate node G1, the gate middle parasitic resistanceR g2 And gate external parasitic capacitanceC g Connected in series between the middle gate node G1 and the external source node S, and the internal parasitic resistance of the gateR g_finger Parasitic inductance with drainL d_finger Connected in series between a middle gate node G1 and an intrinsic gate node G2, the gate middle parasitic capacitanceC gs_in Connected between the middle gate node G1 and the intrinsic source node S1, the internal parasitic capacitance of the gateC gs_finger Is connected to the bookA parasitic resistance between the sign gate node G2 and the intrinsic source node S1R d1 Connected between an external drain node D and a middle drain node D1, the drain middle parasitic resistanceR d2 And the external parasitic capacitance of the drainC d Connected between the middle drain electrode node D1 and the external source electrode node S after being connected in series, and the internal parasitic resistance of the drain electrodeR d_finger Parasitic inductance with drainL d_finger Connected in series between a middle drain node D1 and an intrinsic drain node D2, the drain middle parasitic capacitanceC ds_in Connected between the middle drain node D1 and the intrinsic source node S1, the internal parasitic capacitance of the drainC ds_finger Connected between an intrinsic drain node D2 and an intrinsic source node S1, the gate-drain parasitic capacitanceC gd_finger Connected between an intrinsic gate node G2 and an intrinsic drain node D2, the source parasitic inductanceL s And source skin effect impedanceZ rf Connected in series between the external source node S and the intrinsic source node S1.
2. The InP-based terahertz HEMT transistor small-signal model according to claim 1, wherein said intrinsic element comprises: gate-source intrinsic capacitanceC gs Gate source intrinsic resistanceR i Gate-drain intrinsic capacitanceC gd Gate drain intrinsic resistanceR gd Drain-source intrinsic capacitanceC ds Drain source intrinsic resistanceR ds And a voltage controlled current sourceVCCSWherein the gate-source intrinsic capacitanceC gs And gate source intrinsic resistanceR i Connected in series between an intrinsic gate node G2 and an intrinsic source node S1, the gate-drain intrinsic capacitanceC gd And gate drain intrinsic resistanceR gd Connected in series between an intrinsic gate node G2 and an intrinsic drain node D2, the drain-source intrinsic capacitanceC ds Drain source intrinsic resistanceR ds And a voltage controlled current sourceVCCSConnected in parallel between the intrinsic drain node D2 and the intrinsic source node S1.
3. The InP-based terahertz HEMT transistor small-signal model of claim 1, wherein the step-by-step extraction process of parasitic parameters in said parasitic element is:
step 1, modeling a partial structure of a transistor in three-dimensional electromagnetic simulation software, wherein the modeling comprises the following steps: the substrate part, the back gold part positioned on the lower surface of the substrate, the dielectric layer part positioned on the upper surface of the substrate, the grid electrode transmission line part positioned on the upper surface of the dielectric layer and the drain electrode transmission line part positioned on the upper surface of the dielectric layer; then carrying out two-port three-dimensional electromagnetic simulation on the transistor in the full frequency band, calculating a Z parameter, and further calculating according to the Z parameter to obtain a grid external parasitic resistanceR g1 And the parasitic resistance in the middle of the gridR g2 Total resistance ofR Tg External parasitic capacitance of gridC g External parasitic resistance of drain electrodeR d1 And the parasitic resistance in the middle of the drainR d2 Total resistance ofR Td External parasitic capacitance of drain electrodeC d ；
Step 2, modeling the partial structure of the transistor in three-dimensional electromagnetic simulation software, wherein the modeling comprises the following steps: the substrate part, the back gold part positioned on the lower surface of the substrate, the dielectric layer part positioned on the upper surface of the substrate, the single source electrode part positioned on the upper surface of the dielectric layer and the source electrode grounding hole; then, single-port three-dimensional electromagnetic simulation is carried out on the transistor in the full frequency band, the Z parameter is calculated, and then the parasitic inductance of the source electrode is obtained through calculation according to the Z parameterL s Source skin effect impedanceZ rf ；
Step 3, modeling the partial structure of the transistor in three-dimensional electromagnetic simulation software, wherein the modeling comprises the following steps: the substrate part, the back gold part positioned on the lower surface of the substrate, the dielectric layer part positioned on the upper surface of the substrate, the grid electrode transmission line part positioned on the upper surface of the dielectric layer, the drain electrode transmission line part, the two source electrode parts and the source electrode grounding hole; then the crystal is paired in the full frequency bandPerforming two-port three-dimensional electromagnetic simulation on the tube, calculating Y parameters, and calculating to obtain the middle parasitic capacitance of the grid according to the Y parametersC gs_in Middle part parasitic capacitance of drain electrodeC ds_in ；
And 4, modeling the complete structure of the transistor in three-dimensional electromagnetic simulation software, wherein the modeling comprises the following steps: the substrate part is positioned on the back gold part of the lower surface of the substrate, the dielectric layer part positioned on the upper surface of the substrate, the grid transmission line part, the grid finger part, the drain transmission line part, the drain metal strip part, the two source electrode parts and the source electrode grounding hole which are positioned on the upper surface of the dielectric layer; then, two-port three-dimensional electromagnetic simulation is carried out on the transistor in the full frequency band, Y parameters are calculated, and then the grid-drain parasitic capacitance is calculated according to the Y parametersC gd_finger Internal parasitic capacitance of drainC ds_finger Internal parasitic capacitance of gridC gs_finger ；
Step 5, setting:R g1 =λR Tg 、R g2 =(1-λ)R Tg ，R d1 =φR Td 、R d2 =(1-φ)R Td ，λandφall the distribution proportions are within the value range of 0 to 1,λandφis set to 0.5; meanwhile, a parasitic resistor in the grid electrode is arrangedR g_finger Parasitic inductance of grid electrodeL g_finger Internal parasitic resistance of drainR d_finger Drain parasitic inductanceL d_finger Is 0; and optimizing all parasitic parameters according to the parasitic cost function to obtain final parasitic parameters.
4. The InP-based terahertz HEMT small-signal model as claimed in claim 3, wherein in step 1, the parasitic resistance outside the gateR g1 And the parasitic resistance in the middle of the gridR g2 Total resistance ofR Tg External parasitic capacitance of gridC g External parasitic resistance of drainR d1 And the parasitic resistance in the middle of the drainR d2 Total resistance ofR Td External parasitic capacitance of drainC d The following equation is satisfied:
wherein,Z 11 、Z 22 in turn, represent the corresponding terms in the Z parameter,fthe frequency is represented by a frequency-dependent signal,f max representing the highest frequency.
5. The InP-based terahertz HEMT small-signal model as defined in claim 3, wherein in step 2, the parasitic inductance of the source electrodeL s Source skin effect impedanceZ rf The following equation is satisfied:
wherein,Z 11 represents the corresponding item in the Z parameter,fthe frequency is represented by a frequency-dependent variable,f max representing the highest frequency.
6. The InP-based terahertz HEMT small-signal model as defined in claim 3, wherein in step 3, the parasitic capacitance in the middle of the gateC gs_in Middle part parasitic capacitance of drain electrodeC ds_in The following equation is satisfied:
wherein,Y 11 、Y 22 in turn, represent the corresponding terms in the Y parameter,fthe frequency is represented by a frequency-dependent variable,f min representing the lowest frequency.
7. The InP-based terahertz HEMT small-signal model as defined in claim 3, wherein in step 4, the gate-drain parasitic capacitanceC gd_finger Internal parasitic capacitance of drainC ds_finger Internal parasitic capacitance of gridC gs_finger The following equation is satisfied:
wherein,Y 11 、Y 22 、Y 12 in turn, represent the corresponding terms in the Y parameter,fthe frequency is represented by a frequency-dependent signal,f min representing the lowest frequency.
8. The InP-based terahertz HEMT transistor small-signal model as claimed in claim 3, wherein in step 5, the parasitic cost function is:
wherein,J i,j and withK i,j Are all preset weight values, and are all preset weight values,S a (i,j) A circuit simulation result representing the parasitic element,S b (i,j) And representing a three-dimensional electromagnetic simulation result.
9. The InP-based terahertz HEMT transistor small-signal model according to claim 2, wherein the extraction process of intrinsic parameters of said intrinsic element is:
measuring S parameters of the transistor under all bias conditions in a full frequency band, and calculating to obtain corresponding Y parameters according to the S parameters; based on known parasitic parameters, the full-band test Y parameters of the transistor are de-embedded to obtain intrinsic Y parameters Y int (ii) a Gate-source intrinsic capacitanceC gs Gate source intrinsic resistanceR i Gate-drain intrinsic capacitanceC gd Gate drain intrinsic resistanceR gd Drain-source intrinsic capacitanceC ds Drain source intrinsic resistanceR ds Voltage controlled current sourceVCCSThe following equation is satisfied:
wherein,g m representative voltage controlled current sourceVCCSThe transconductance of (a) is,ωrepresenting angular frequency, tau representing voltage-controlled current sourceVCCSTime delay of (2);
and optimizing all intrinsic parameters according to the intrinsic cost function to obtain the final intrinsic parameters.
10. The InP-based terahertz HEMT transistor small-signal model of claim 9, wherein said intrinsic cost function is:
wherein,J i,j andK i,j is a pre-set weight of the weight,S c (i,j) Represents the circuit simulation results of the small-signal model,S d (i,j) The test results are shown.
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