CN116258104A - Reconfigurable model of InP terahertz transistor and parameter extraction method thereof - Google Patents
Reconfigurable model of InP terahertz transistor and parameter extraction method thereof Download PDFInfo
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Abstract
The invention belongs to the field of semiconductor devices, and particularly provides a reconfigurable model of an InP terahertz transistor and a parameter extraction method thereof, which are used for solving the problems that the application range of the existing model is small and transistors with different structures cannot be modeled. According to the invention, the variable element is introduced on the basis of the existing model, and the transistors of various types are induced under the unified model through the variable element, so that the physical meaning among the transistors of various types is more definite; meanwhile, in the parameter extraction process, 6 parasitic element sub-models are equivalent to the transistor, step modeling simulation is carried out through three-dimensional electromagnetic field simulation software, and then parameter extraction is completed for various transistors under a unified model and equation expression thereof based on a new parameter extraction algorithm; based on the method, the method and the device can accurately model the double-hole bridged transistor, the single-hole bridged transistor and the double-hole non-bridged transistor, greatly improve the application range of the model, and have the advantages of saving the modeling time and improving the simulation precision.
Description
Technical Field
The invention belongs to the field of semiconductor devices, relates to the technology of microelectronic devices, further relates to a small signal equivalent circuit model of an HEMT transistor, and particularly provides a reconfigurable model of an InP terahertz transistor and a parameter extraction method thereof.
Background
The InP material has the characteristics of high electron mobility, high saturation drift speed and the like, has better noise coefficient compared with a GaN-based HEMT transistor, has higher electron mobility compared with a GaAs-based HEMT transistor, and can be applied to higher frequency bands; therefore, the InP-based HEMT transistor is suitable for the design of a low-noise amplifier with terahertz frequency, and has great significance in the aspects of electronic warfare, phased array radar, satellite communication, radio astronomy and the like with terahertz frequency.
The small-signal equivalent circuit model (small-signal model for short) is a tie between circuit design and device characteristics, and after modeling is carried out on a device, the model can be embedded into EDA software to carry out circuit simulation and design. For HEMT transistor devices, parasitic parameters of the traditional small signal model have no physical significance, the simulation precision is not high, and modeling of different transistor structures cannot be performed; in order to solve the problem, the inventor of the invention discloses a small signal model of an InP-based terahertz HEMT transistor in a patent document with a publication number of CN114970419A, and the parasitic parameter extraction process of the model has definite physical meaning and greatly improves the precision; however, in the chip design process, the passive structure of the transistor is often changed, such as three types of common dual-hole bridged transistors (dual-hole structure transistors including air bridges), single-hole bridged transistors (single-hole structure transistors including air bridges), dual-hole bridgeless transistors (dual-hole structure transistors not including air bridges), and in this patent document, 3 sets of models need to be built to describe the 3 types of transistors respectively.
Disclosure of Invention
The invention aims to provide an InP-based terahertz HEMT transistor small signal model which can be reconstructed and is oriented to different passive structures and a parameter extraction method thereof, aiming at the problems that the small signal model has a small application range and can not model transistors with different structures. According to the invention, the variable element is introduced on the basis of the existing model, and the transistors of various types with the changed passive structures are induced under the unified model through the variable element, so that the physical meaning among the transistors with different structures is more definite; meanwhile, in the parameter extraction process, the geometric figures of the transistors are divided into 6 groups, 6 parasitic element sub-models are respectively equivalent, the 6 groups of geometric figures are subjected to step-by-step modeling simulation through three-dimensional electromagnetic field simulation software, and then the transistors with different structures are subjected to parameter extraction (including parasitic parameters and intrinsic parameters) under a unified model and equation expression thereof based on a new parameter extraction algorithm; based on the method, the device and the system for modeling the double-hole bridge transistor can accurately model the double-hole bridge transistor (the double-hole structure transistor containing the air bridge), the single-hole bridge transistor (the single-hole structure transistor containing the air bridge) and the double-hole bridge-free transistor (the double-hole structure transistor not containing the air bridge), greatly improve the application range of the model, and have the advantages of saving modeling time and improving the simulation precision of the small-signal model.
In order to achieve the above purpose, the invention adopts the following technical scheme:
a reconfigurable model of an InP terahertz transistor, comprising: parasitic and intrinsic elements; it is characterized in that the method comprises the steps of,
the parasitic element includes: grid external parasitic impedance Z g Parasitic capacitance C outside grid g Parasitic capacitance C in the middle of grid gs_in Parasitic capacitance C in gate gs_finger Parasitic impedance Z inside grid grf Parasitic inductance L inside grid g_finger Parasitic capacitance C of gate and drain gd_finger Parasitic impedance Z inside drain drf Parasitic inductance L inside drain d_finger Leakage and leakParasitic capacitance C in the pole ds_finger Parasitic capacitance C in the middle of drain ds_in Drain external parasitic impedance Z d Drain external parasitic capacitance C d Source impedance Z srf Parasitic inductance L of source electrode s Parasitic capacitance delta C in the middle of variable grid gs_in Variable drain middle parasitic capacitance ΔC ds_in Variable gate internal parasitic capacitance ΔC gs_finger Variable drain internal parasitic capacitance ΔC ds_finger Variable source parasitic inductance Δl s Variable source impedance ΔZ srf The method comprises the steps of carrying out a first treatment on the surface of the Wherein,,
the gate external parasitic impedance Z g Parasitic capacitance C outside the gate g Connected in series between an external gate node G and an external source node S, the drain external parasitic impedance Z d Parasitic capacitance C outside the drain d Connected in series between an external drain node D and an external source node S, the source parasitic inductance L s Impedance Z with source electrode srf Connected in series between the external source node S and the intrinsic source node S1, the parasitic capacitance C in the middle of the grid electrode gs_in And variable gate middle parasitic capacitance delta C gs_in Connected in parallel between the external gate node G and the intrinsic source node S1, the drain middle parasitic capacitance C ds_in And variable drain middle parasitic capacitance delta C ds_in Connected in parallel between the external drain node D and the intrinsic source node S1, the internal parasitic impedance Z of the grid electrode grf Parasitic inductance L inside the gate g_finger Connected in series between the external gate node G and the intrinsic gate node G1, the drain internal parasitic impedance Z drf Parasitic inductance L inside the drain d_finger Connected in series between the external drain node D and the intrinsic drain node D1, the parasitic capacitance C inside the gate gs_finger And variable gate internal parasitic capacitance ΔC gs_finger Connected in parallel between the intrinsic gate node G1 and the intrinsic source node S1, the drain internal parasitic capacitance C ds_finger And variable drain internal parasitic capacitance ΔC ds_finger Connected in parallel between the intrinsic drain node D1 and the intrinsic source node S1, the gate-drain parasitic capacitanceC gd_finger Connected between the intrinsic gate node G1 and the intrinsic drain node D1, the variable source parasitic inductance DeltaL s And variable source impedance deltaz srf Connected in series between the external source node S and the intrinsic source node S1.
Further, the eigenelements include: grid source intrinsic capacitance C gs Intrinsic resistance R of gate source i Grid leakage intrinsic capacitance C gd Grid leakage intrinsic resistance R gd Intrinsic capacitance C of drain source ds Intrinsic resistance R of drain source ds And a voltage-controlled current source VCCS, wherein the gate-source intrinsic capacitance C gs Intrinsic resistance R of gate source i Connected in series between the intrinsic gate node G1 and the intrinsic source node S1, the gate-drain intrinsic capacitance C gd And gate-drain intrinsic resistance R gd Connected in series between the intrinsic gate node G1 and the intrinsic drain node D1, the drain-source intrinsic capacitance C ds Intrinsic resistance R of drain source ds Is connected in parallel with the voltage-controlled current source VCCS between the intrinsic drain node D1 and the intrinsic source node S1.
The parameter extraction method of the reconfigurable model of the InP terahertz transistor comprises the following steps: parasitic parameter extraction and intrinsic parameter extraction; the parasitic parameter extraction method is characterized by comprising the following steps of:
step 1, modeling a part of a structure of a transistor in three-dimensional electromagnetic simulation software, wherein the step comprises the following steps: the substrate part is positioned at the back gold part of the lower surface of the substrate, the dielectric layer part is positioned at the upper surface of the substrate, and the gate transmission line part and the drain transmission line part are positioned at the upper surface of the dielectric layer; then carrying out two-port three-dimensional electromagnetic simulation on the transistor in the full frequency band, calculating Y parameter and Z parameter, and further obtaining external parasitic impedance Z of the grid electrode according to the calculation of the Z parameter g Parasitic capacitance C outside grid g Drain external parasitic impedance Z d Drain external parasitic capacitance C d ；
Further, in step 1, the gate external parasitic impedance Z g Parasitic capacitance C outside grid g Drain external parasitic impedance Z d Drain external parasitic capacitance C d The following equation is satisfied:
wherein Z is 1 (1, 1) and Z 1 (2, 2) represents the corresponding term of the Z parameter in step 1, f represents the frequency, f l And f h Representing a lower frequency limit and an upper frequency limit, respectively.
Further, in step 2, the source impedance Z srf Parasitic inductance L of source electrode s The following equation is satisfied:
for a dual-hole bridged transistor, a variable source parasitic electricalSense ΔL s Variable source impedance ΔZ srf The following equation is satisfied:
for a dual-hole bridgeless transistor, the source parasitic inductance Δl is variable s Variable source impedance ΔZ srf The following equation is satisfied:
for a single-hole bridged transistor, the variable source parasitic inductance ΔL s Variable source impedance ΔZ srf The method meets the following conditions: ΔL s ＝+∞，ΔZ srf ＝+∞；
Wherein Z is 2 (1, 1) represents the corresponding term of the Z parameter in step 2, f represents the frequency, f l And f h Representing a lower frequency limit and an upper frequency limit, respectively.
Further, in step 3, the parasitic inductance L inside the gate g_finger Parasitic impedance Z inside grid grf The following equation is satisfied:
wherein Y is 3 (2, 1) represents the corresponding item of the Y parameter in step 3,f represents frequency, f l And f h Representing a lower frequency limit and an upper frequency limit, respectively.
Further, in step 4, the parasitic inductance L inside the drain d_finger Parasitic impedance Z inside drain drf The following equation is satisfied:
wherein Y is 4 (2, 1) represents the corresponding term in the Y parameter in step 4, f represents the frequency, f l And f h Representing a lower frequency limit and an upper frequency limit, respectively.
Further, in step 5, the parasitic capacitance C in the middle of the gate gs_in Parasitic capacitance C in the middle of drain ds_in The following equation is satisfied:
wherein Y is 5a (1,1)、Y 5a (1,2)、Y 5a (2,1)、Y 5a (2, 2) the correspondence of Y parameter for the double-hole bridged transistor in step 5, Y 1 (1,1)、Y 1 (2, 2) represent the corresponding terms of the Y parameter in step 1, Z 2 (1, 1) represents the corresponding term of the Z parameter in step 2, f represents the frequency, f l And f h Respectively representing a lower frequency limit and an upper frequency limit;
for a dual-hole bridged transistor, the parasitic capacitance ΔC in the middle of the gate is variable gs_in Variable drain middle parasitic capacitance ΔC ds_in The method meets the following conditions: ΔC gs_in ＝0，ΔC ds_in ＝0；
For a dual-hole bridgeless transistor, the parasitic capacitance ΔC in the middle of the gate is variable gs_in Variable drain middle parasitic capacitance ΔC ds_in The following equation is satisfied:
wherein Y is 5b (1,1)、Y 5b (1,2)、Y 5b (2,1)、Y 5b (2, 2) sequentially representing the corresponding terms of the Y parameter for the dual-hole bridgeless transistor in step 5;
for a single-hole bridged transistor, the parasitic capacitance ΔC in the middle of the gate is variable gs_in Variable drain middle parasitic capacitance ΔC ds_in The following equation is satisfied:
wherein Y is 5c (1,1)、Y 5c (1,2)、Y 5c (2,1)、Y 5c (2, 2) represents the correspondence of the Y parameter for the single-hole bridged transistor in step 5.
Further, in step 6, the gate-drain parasitic capacitance C gd_finger Parasitic capacitance C inside drain ds_finger Parasitic capacitance C in gate gs_finger The following equation is satisfied:
wherein Y is 6a (1,1)、Y 6a (1,2)、Y 6a (2,1)、Y 6a (2, 2) the correspondence of Y parameter for the double-hole bridged transistor in step 6, Y 1 (1,1)、Y 1 (2, 2) represent the corresponding terms of the Y parameter in step 1, Z 2 (1, 1) represents the corresponding term of the Z parameter in step 2, Y 52a (1,1)、Y 52a (2, 2) representing the corresponding terms of the Y parameter in step 5, Y 3 (2, 1) represents the corresponding term of the Y parameter in step 3, Y 4 (2, 1) represents the corresponding term of the Y parameter in step 4, f represents the frequency, f l And f h Respectively representing a lower frequency limit and an upper frequency limit;
for a dual-hole bridged transistor, the parasitic capacitance ΔC inside the gate is variable gs_finger Variable drain internal parasitic capacitance ΔC ds_finger The method meets the following conditions: ΔC gs_finger ＝0，ΔC ds_finger ＝0；
For a dual-hole bridgeless transistor, the parasitic capacitance ΔC inside the gate is variable gs_finger Variable drain internal parasitic capacitance ΔC ds_finger The following equation is satisfied:
wherein Y is 6b (1,1)、Y 6b (1,2)、Y 6b (2,1)、Y 6b (2, 2) sequentially representing the corresponding terms of the Y parameter for the dual-hole bridgeless transistor in step 6; y is Y 52b (1,1)、Y 52b (2, 2) representing the corresponding terms of the Y parameter in step 5, respectively;
for a single-hole bridged transistor, the parasitic capacitance ΔC inside the gate is variable gs_finger Variable drain internal parasitic capacitance ΔC ds_finger The following equation is satisfied:
wherein Y is 6c (1,1)、Y 6c (1,2)、Y 6c (2,1)、Y 6c (2, 2) the correspondence of Y parameter for the single-hole bridged transistor in step 6, Y 52c (1,1)、Y 52c (2, 2) represent the corresponding terms of the Y parameter in step 5, respectively.
Further, the intrinsic parameter extraction includes the steps of:
respectively optimizing intrinsic parameters of the double-hole bridge transistor, the double-hole bridge-free transistor and the single-hole bridge transistor according to the intrinsic cost function;
and carrying out judgment fusion on the intrinsic parameters of the double-hole bridged transistor, the double-hole non-bridged transistor and the single-hole bridged transistor according to the optimized intrinsic parameters:
respectively averaging each intrinsic parameter, and calculating and respectively calculating error functions:
wherein M is a 、M b 、M c Intrinsic parameter values of a double-hole bridged transistor, a double-hole non-bridged transistor and a single-hole bridged transistor respectively, 
The average value corresponding to the intrinsic parameters;
if the error is more than or equal to 10%, the intrinsic parameter is kept unchanged, and if the error is less than 10%, the intrinsic parameter is updated to a corresponding average value.
Compared with the prior art, the invention has the beneficial effects that:
the invention provides a reconfigurable InP-based terahertz HEMT transistor small signal model facing different structures and a parameter extraction method thereof, in particular to a method for extracting parameters of the InP-based terahertz HEMT transistor small signal model: the invention improves the existing small signal model, solves the problem that different transistor structures cannot be modeled aiming at the existing small signal model, can accurately model three types of double-hole bridged transistors (double-hole structure transistors containing air bridges), single-hole bridged transistors (single-hole structure transistors containing air bridges) and double-hole non-bridged transistors (double-hole structure transistors not containing air bridges) under a unified model, and can determine the initial value of each parasitic parameter in the model. Compared with the existing small signal model, the invention greatly improves the application range of the model, saves modeling time and improves the simulation precision of the small signal model.
Drawings
Fig. 1 is a schematic diagram of a topology structure of an InP-based terahertz HEMT transistor small signal model in the present invention.
Fig. 2 is a schematic diagram of the first parasitic element sub-model in the small signal model shown in fig. 1.
Fig. 3 is a schematic diagram of the structure of a second parasitic element sub-model in the small signal model shown in fig. 1.
Fig. 4 is a schematic structural diagram of a third parasitic element sub-model in the small signal model shown in fig. 1.
Fig. 5 is a schematic structural diagram of a fourth parasitic element sub-model in the small signal model shown in fig. 1.
Fig. 6 is a schematic structural diagram of a fifth parasitic element sub-model in the small signal model shown in fig. 1.
Fig. 7 is a schematic structural diagram of a sixth parasitic element sub-model in the small signal model shown in fig. 1.
Fig. 8 is a three-dimensional electromagnetic simulation model corresponding to the first parasitic element sub-model shown in fig. 2.
Fig. 9 is a three-dimensional electromagnetic simulation model corresponding to the second parasitic element sub-model shown in fig. 3.
Fig. 10 is a three-dimensional electromagnetic simulation model corresponding to the third parasitic element sub-model shown in fig. 4.
Fig. 11 is a three-dimensional electromagnetic simulation model corresponding to the fourth parasitic element sub-model shown in fig. 5.
Fig. 12 is a three-dimensional electromagnetic simulation model of a double-hole bridged transistor corresponding to the fifth parasitic element sub-model shown in fig. 6.
Fig. 13 is a three-dimensional electromagnetic simulation model of a double-hole bridgeless transistor corresponding to the fifth parasitic element sub-model shown in fig. 6.
Fig. 14 is a three-dimensional electromagnetic simulation model of the fifth parasitic element sub-model of fig. 6 corresponding to a single-hole bridged transistor.
Fig. 15 is a three-dimensional electromagnetic simulation model of a double-hole bridged transistor corresponding to the sixth parasitic element sub-model shown in fig. 7.
Fig. 16 is a three-dimensional electromagnetic simulation model of a double-hole bridgeless transistor corresponding to the sixth parasitic element sub-model shown in fig. 7.
Fig. 17 is a three-dimensional electromagnetic simulation model of a single-hole bridged transistor corresponding to the sixth parasitic element sub-model shown in fig. 7.
FIG. 18 shows a double-hole bridged-crystal in an embodiment of the present inventionThe body tube is in a common enlarged state (V gs ＝0.2V、V ds Circuit simulation results of small signal model =0.6v) versus S11 parameter of test results.
FIG. 19 shows a dual-hole bridge transistor in a normal amplifying state (V gs ＝0.2V、V ds =0.6v) the S12 parameter comparison graph of the circuit simulation result and the test result of the small signal model.
FIG. 20 shows a dual-hole bridge transistor in a normal amplifying state (V gs ＝0.2V、V ds =0.6v) the S21 parameter comparison graph of the circuit simulation result and the test result of the small signal model.
FIG. 21 shows a dual-hole bridge transistor in a normal amplifying state (V gs ＝0.2V、V ds =0.6v) the S22 parameter comparison graph of the circuit simulation result and the test result of the small signal model.
FIG. 22 shows a dual-hole bridgeless transistor in a normal amplifying state (V gs ＝0.2V、V ds Circuit simulation results of small signal model =0.6v) versus S11 parameter of test results.
Fig. 23 shows a conventional amplification state (V) of a dual-hole bridgeless transistor according to an embodiment of the present invention gs ＝0.2V、V ds =0.6v) the S12 parameter comparison graph of the circuit simulation result and the test result of the small signal model.
FIG. 24 shows a dual-hole bridgeless transistor in a normal amplifying state (V) gs ＝0.2V、V ds =0.6v) the S21 parameter comparison graph of the circuit simulation result and the test result of the small signal model.
FIG. 25 shows a dual-hole bridgeless transistor in a normal amplifying state (V) gs ＝0.2V、V ds =0.6v) the S22 parameter comparison graph of the circuit simulation result and the test result of the small signal model.
FIG. 26 shows a single-hole bridge transistor in a normal amplifying state (V gs ＝0.2V、V ds Circuit simulation results of small signal model =0.6v) versus S11 parameter of test results.
FIG. 27 is a common amplifying state (V) of the single-hole bridge transistor in the embodiment of the invention gs ＝0.2V、V ds =0.6v) the S12 parameter comparison graph of the circuit simulation result and the test result of the small signal model.
FIG. 28 shows a single-hole bridge transistor in a normal amplifying state (V gs ＝0.2V、V ds =0.6v) the S21 parameter comparison graph of the circuit simulation result and the test result of the small signal model.
FIG. 29 shows a single-hole bridge transistor in a normal amplifying state (V gs ＝0.2V、V ds =0.6v) the S22 parameter comparison graph of the circuit simulation result and the test result of the small signal model.
Fig. 30 is a graph showing the comparison between the circuit simulation results of the small signal model and the S21 parameter of the test results of the three types of transistors in the normal amplifying state according to the embodiment of the present invention.
Fig. 31 is a graph showing the comparison between the circuit simulation results of the small signal model and the S11 parameter of the test results of the three types of transistors in the normal amplifying state according to the embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the present invention will be further described in detail with reference to the accompanying drawings and embodiments.
The embodiment provides a reconfigurable InP-based terahertz HEMT transistor small-signal model with different structures and a parameter extraction method thereof, wherein the topological structure of the small-signal model is shown in fig. 1, and the method comprises the following steps: parasitic and intrinsic elements having the following nodes: an external gate node G, an intrinsic gate node G1, an external drain node D, an intrinsic drain node D1, an external source node S, an intrinsic source node S1.
More specifically:
the eigenelement includes: grid source intrinsic capacitance C gs Intrinsic resistance R of gate source i Grid leakage intrinsic capacitance C gd Grid leakage intrinsic resistance R gd Intrinsic capacitance C of drain source ds Intrinsic resistance R of drain source ds And a voltage controlled current source VCCS, whichIn the gate-source intrinsic capacitance C gs Intrinsic resistance R of gate source i Connected in series between the intrinsic gate node G1 and the intrinsic source node S1, the gate-drain intrinsic capacitance C gd And gate-drain intrinsic resistance R gd Connected in series between the intrinsic gate node G1 and the intrinsic drain node D1, the drain-source intrinsic capacitance C ds Intrinsic resistance R of drain source ds Is connected in parallel with the voltage-controlled current source VCCS between the intrinsic drain node D1 and the intrinsic source node S1.
The parasitic element includes: grid external parasitic impedance Z g Parasitic capacitance C outside grid g Parasitic capacitance C in the middle of grid gs_in Parasitic capacitance C in gate gs_finger Parasitic impedance Z inside grid grf Parasitic inductance L inside grid g_finger Parasitic capacitance C of gate and drain gd_finger Parasitic impedance Z inside drain drf Parasitic inductance L inside drain d_finger Parasitic capacitance C inside drain ds_finger Parasitic capacitance C in the middle of drain ds_in Drain external parasitic impedance Z d Drain external parasitic capacitance C d Source impedance Z srf Parasitic inductance L of source electrode s Parasitic capacitance delta C in the middle of variable grid gs_in Variable drain middle parasitic capacitance ΔC ds_in Variable gate internal parasitic capacitance ΔC gs_finger Variable drain internal parasitic capacitance ΔC ds_finger Variable source parasitic inductance Δl s Variable source impedance ΔZ srf The method comprises the steps of carrying out a first treatment on the surface of the Wherein, the parasitic capacitance delta C in the middle of the variable grid gs_in Variable drain middle parasitic capacitance ΔC ds_in Variable gate internal parasitic capacitance ΔC gs_finger Variable drain internal parasitic capacitance ΔC ds_finger Variable source parasitic inductance Δl s Variable source impedance ΔZ srf The value of the variable element is changed according to different transistor structures, and the change of transistor parameters under different structures is reflected;
in the parasitic element, the gate external parasitic impedance Z g Parasitic capacitance C outside the gate g Connected in series to an external grid node GBetween the external source node S and the drain external parasitic impedance Z d Parasitic capacitance C outside the drain d Connected in series between an external drain node D and an external source node S, the source parasitic inductance L s Impedance Z with source electrode srf Connected in series between the external source node S and the intrinsic source node S1, the parasitic capacitance C in the middle of the grid electrode gs_in And variable gate middle parasitic capacitance delta C gs_in Connected in parallel between the external gate node G and the intrinsic source node S1, the drain middle parasitic capacitance C ds_in And variable drain middle parasitic capacitance delta C ds_in Connected in parallel between the external drain node D and the intrinsic source node S1, the internal parasitic impedance Z of the grid electrode grf Parasitic inductance L inside the gate g_finger Connected in series between the external gate node G and the intrinsic gate node G1, the drain internal parasitic impedance Z drf Parasitic inductance L inside the drain d_finger Connected in series between the external drain node D and the intrinsic drain node D1, the parasitic capacitance C inside the gate gs_finger And variable gate internal parasitic capacitance ΔC gs_finger Connected in parallel between the intrinsic gate node G1 and the intrinsic source node S1, the drain internal parasitic capacitance C ds_finger And variable drain internal parasitic capacitance ΔC ds_finger Connected in parallel between the intrinsic drain node D1 and the intrinsic source node S1, the gate-drain parasitic capacitance C gd_finger Connected between the intrinsic gate node G1 and the intrinsic drain node D1, the variable source parasitic inductance DeltaL s And variable source impedance deltaz srf Connected in series between the external source node S and the intrinsic source node S1.
The core creation of the invention is that: the invention introduces variable elements into the model to simulate transistors with different structures and corresponding parameter extraction methods, and further inducts various transistors with changed passive structures under the unified model and parameter extraction methods, so that the physical meaning among the transistors with different structures is more definite.
On the basis, the embodiment also provides a parameter extraction method of the small signal model; in the parameter extraction process, the transistor geometric figures are divided into 6 groups, 6 parasitic element sub-models are respectively equivalent, the 6 groups of geometric figures are subjected to step-by-step modeling simulation through three-dimensional electromagnetic field simulation software, and then the parameter extraction is realized by adopting a new method based on simulation results; the invention can accurately model the double-hole bridge transistor (the double-hole structure transistor containing the air bridge), the single-hole bridge transistor (the single-hole structure transistor containing the air bridge) and the double-hole bridge-free transistor (the double-hole structure transistor not containing the air bridge), greatly improves the application range of the model, and has the advantages of saving the modeling time and improving the simulation precision of the small signal model.
More specifically:
a first parasitic element submodel: the external parasitic parameters of the grid and the drain electrode have the structure shown in fig. 2, and the external parasitic parameters comprise: grid external parasitic impedance Z g Parasitic capacitance C outside grid g Drain external parasitic impedance Z d Drain external parasitic capacitance C d The included nodes comprise an external grid node G, an external drain node D and an external source node S; grid external parasitic impedance Z g Drain external parasitic impedance Z d Jointly simulating parasitic effects of the grid transmission lines; drain external parasitic impedance Z d Drain external parasitic capacitance C d Jointly simulating parasitic effects of drain transmission lines;
a second parasitic element submodel: source external parasitic parameters, the structure of which is shown in fig. 3, comprising: source impedance Z srf Parasitic inductance L of source electrode s And a variable source impedance ΔZ srf And variable source parasitic inductance DeltaL s The included nodes are an external source node S and an intrinsic source node S1, a source impedance Z srf Parasitic inductance L of source electrode s Variable source parasitic inductance Δl s Variable source impedance ΔZ srf Simulating the inductance of the through hole and the impedance introduced by the skin effect;
third parasitic element submodel: the gate finger introduces parasitic parameters, the structure of which is shown in fig. 4, comprising: first parasitic element submodel, parasitic inductance L inside grid electrode g_finger Parasitic impedance Z inside grid grf The method comprises the steps of carrying out a first treatment on the surface of the The included nodes comprise an external source node S, an external grid node G and an external drain node D; parasitic inductance L inside grid g_finger Parasitic impedance Z inside grid grf Respectively simulating inductance of the gate finger and impedance introduced by skin effect;
fourth parasitic element submodel: the parasitic parameters introduced by the drain metal strip have the structure shown in fig. 5, and include: first parasitic element submodel, drain internal parasitic inductance L d_finger Parasitic impedance Z inside drain drf The method comprises the steps of carrying out a first treatment on the surface of the The included nodes comprise an external source node S, an external grid node G and an external drain node D; parasitic inductance L inside drain d_finger Parasitic impedance Z inside grid drf Respectively simulating inductance of a drain electrode metal strip and impedance introduced by skin effect;
fifth parasitic element submodel: the external parasitic parameters of the gate, the drain and the source are shown in fig. 6, and the structure comprises: first parasitic element sub-model, second parasitic element sub-model, and gate middle parasitic capacitance C gs_in Parasitic capacitance C in the middle of drain ds_in And variable drain middle parasitic capacitance ΔC ds_in And variable gate middle parasitic capacitance delta C gs_in The method comprises the steps of carrying out a first treatment on the surface of the The included nodes comprise an external source node S, an intrinsic source node S1, an external gate node G and an external drain node D; parasitic capacitance C in the middle of the grid gs_in And variable gate middle parasitic capacitance ΔC gs_in Simulating the coupling effect of the grid transmission line and the source electrode, and the parasitic capacitance C in the middle of the drain electrode ds_in And a variable drain middle parasitic capacitance ΔC ds_in Simulating the coupling effect of the drain transmission line and the source;
sixth parasitic element submodel: the overall parasitic parameters, the structure of which is shown in fig. 7, include all parasitic elements and nodes;
meanwhile, the 6 parasitic element submodels comprise all connecting wires between corresponding elements and all connecting wires between elements and nodes in the small signal model.
Further, in this embodiment, an InP-based HEMT transistor of 35nm is taken as an example, and the test frequency band is 10-110 GHz, and the existing 10-66 GHz test system and 75-110 GHz test system are adopted to realize the test in sections; the method specifically comprises the following steps:
step 1, modeling a part of a structure of a transistor in three-dimensional electromagnetic simulation software, wherein the step comprises the following steps: the substrate part, the back gold part on the lower surface of the substrate, the dielectric layer part on the upper surface of the substrate, the gate transmission line part and the drain transmission line part on the upper surface of the dielectric layer, as shown in fig. 8; then carrying out two-port three-dimensional electromagnetic simulation on the transistor in the full frequency band (10-110 GHz), and calculating Y parameters and Z parameters of the transistor, wherein a first port is set to be a gate transmission line edge and a back gold edge, and a second port is set to be a drain transmission line edge and a back gold edge;
the model corresponds to the first parasitic element sub-model, and the first parasitic element sub-model is subjected to circuit analysis to obtain the external parasitic impedance Z of the grid electrode g Parasitic capacitance C outside grid g Drain external parasitic impedance Z d Drain external parasitic capacitance C d Calculated from the following equation:
wherein Z is 1 (1, 1) and Z 1 (2, 2) representing the corresponding term in the Z parameter calculated in step 1, im () and re () functions representing the imaginary and real parts, respectively, f representing the frequency, f l And f h Respectively representing a lower frequency limit and an upper frequency limit adopted in the parameter extraction process; according to the present inventionTest conditions of the examples, choose f l And f h 30GHz and 60GHz respectively;
the model corresponds to a second parasitic element sub-model, and the second parasitic element sub-model is subjected to circuit analysis to obtain source impedance Z srf Parasitic inductance L of source electrode s The following equation is satisfied:
1) For a dual-hole bridged transistor, the variable source parasitic inductance ΔL s Variable source impedance ΔZ srf The following equation is satisfied:
wherein Z is 2 (1, 1) represents the corresponding term in the Z parameter calculated in step 2, im () and re () functions represent the imaginary and real parts, respectively, f represents frequency, f l And f h Respectively representing a lower frequency limit and an upper frequency limit adopted in the parameter extraction process; according to the test conditions of the present embodiment, f is selected l And f h 30GHz and 60GHz respectively;
2) For a dual-hole bridgeless transistor, the source parasitic inductance Δl is variable s Variable source impedance ΔZ srf The following equation is satisfied:
3) For a single-hole bridged transistor, the variable source parasitic inductance ΔL s Variable source impedance ΔZ srf The method meets the following conditions: ΔL s ＝+∞，ΔZ srf ＝+∞；
the model corresponds to a third parasitic element sub-model, and the third parasitic element sub-model is subjected to circuit analysis to obtain the parasitic inductance L in the grid electrode g_finger Parasitic impedance Z inside grid grf The following equation is satisfied:
wherein Y is 3 (2, 1) representing the corresponding term in the Y parameter calculated in step 3, im () and re () functions represent the imaginary and real parts, respectively, f represents frequency, f l And f h Respectively representing a lower frequency limit and an upper frequency limit adopted in the parameter extraction process; according to the test conditions of the present embodiment, f is selected l And f h 30GHz and 60GHz respectively;
the model corresponds to a fourth parasitic element sub-model, and the circuit analysis is carried out on the fourth parasitic element sub-model to obtain the parasitic inductance L in the drain electrode d_finger Parasitic impedance Z inside drain drf The following equation is satisfied:
wherein Y is 4 (2, 1) showing the steps4 the corresponding terms in the Y parameter calculated, im () and re () functions represent the imaginary and real parts, f represents the frequency, f l And f h Respectively representing a lower frequency limit and an upper frequency limit adopted in the parameter extraction process; according to the test conditions of the present embodiment, f is selected l And f h 30GHz and 60GHz respectively;
step 5, modeling partial structures of the double-hole bridged transistor, the double-hole non-bridged transistor and the single-hole bridged transistor in three-dimensional electromagnetic simulation software; comprising the following steps: the substrate part, the back gold part positioned on the lower surface of the substrate, the dielectric layer part positioned on the upper surface of the substrate, the grid transmission line part, the drain transmission line part and the two source electrode parts positioned on the upper surface of the dielectric layer; in addition to the above, for a dual-hole bridged transistor, it also includes an air bridge connecting two sources and two ground holes, as shown in fig. 12; for a dual-hole bridgeless transistor, two ground holes are included, as shown in fig. 13; for a single-hole bridged transistor, it also includes an air bridge connecting two sources and a single ground hole, as shown in FIG. 14; then two-port three-dimensional electromagnetic simulation is carried out on the three transistors in the full frequency band, Y parameters are calculated, and then parasitic capacitance C in the middle of the grid electrode of the three transistors is obtained according to the Y parameters gs_in Parasitic capacitance C in the middle of drain ds_in Parasitic capacitance delta C in the middle of variable grid gs_in Variable drain middle parasitic capacitance ΔC ds_in The first port is arranged as a gate transmission line edge and a back gold edge, and the second port is arranged as a drain transmission line edge and a back gold edge;
wherein Y is 5a (1,1)、Y 5a (1,2)、Y 5a (2,1)、Y 5a (2, 2) representing in sequence the corresponding terms in the Y parameter calculated for the double-hole bridged transistor in step 5, im () and re () functions representing the imaginary and real parts, respectively, Y 1 (1,1)、Y 1 (2, 2) each represents a corresponding term, Z, in the Y parameter calculated in step 1 2 (1, 1) represents the corresponding term in the Z parameter calculated in the step 2, f represents the frequency, f l And f h Respectively representing a lower frequency limit and an upper frequency limit adopted in the parameter extraction process; according to the test conditions of the present embodiment, f is selected l And f h 30GHz and 60GHz respectively;
1) For a dual-hole bridged transistor, the parasitic capacitance ΔC in the middle of the gate is variable gs_in Variable drain middle parasitic capacitance ΔC ds_in The method meets the following conditions:
ΔC gs_in ＝0，ΔC ds_in ＝0；
2) For a dual-hole bridgeless transistor, the parasitic capacitance ΔC in the middle of the gate is variable gs_in Variable drain middle parasitic capacitance ΔC ds_in The following equation is satisfied:
wherein Y is 5b (1,1)、Y 5b (1,2)、Y 5b (2,1)、Y 5b (2, 2) the corresponding terms in the Y parameters calculated for the double-hole bridgeless transistor in step 5, Y 51b And Z 51b Y and Z parameters of the same set of characteristics, which can be mutually converted, Y 52b And Z 52b Y-parameters and Z-parameters, which are the same set of characteristics, can be mutually converted, and im () and re () functions represent the imaginary and real parts, respectively, Y 1 (1,1)、Y 1 (2, 2) each represents a corresponding term, Z, in the Y parameter calculated in step 1 2 (1, 1) represents the corresponding term in the Z parameter calculated in the step 2, f represents the frequency, f l And f h Respectively representing a lower frequency limit and an upper frequency limit adopted in the parameter extraction process;
3) For a single-hole bridged transistor, the parasitic capacitance ΔC in the middle of the gate is variable gs_in Variable drain middle parasitic capacitance ΔC ds_in The following equation is satisfied:
wherein Y is 5c (1,1)、Y 5c (1,2)、Y 5c (2,1)、Y 5c (2, 2) representing in sequence the corresponding terms in the Y parameter calculated in step 5 for the single-hole bridged transistor, Y 51c And Z 51c Y and Z parameters of the same set of characteristics, which can be mutually converted, Y 52c And Z 52c Y-parameters and Z-parameters, which are the same set of characteristics, can be mutually converted, and im () and re () functions represent the imaginary and real parts, respectively, Y 1 (1,1)、Y 1 (2, 2) each represents a corresponding term, Z, in the Y parameter calculated in step 1 2 (1, 1) represents the corresponding term in the Z parameter calculated in the step 2, f represents the frequency, f l And f h Respectively representing a lower frequency limit and an upper frequency limit adopted in the parameter extraction process;
step 6, modeling the complete structures of the double-hole bridged transistor, the double-hole bridgeless transistor and the single-hole bridged transistor in three-dimensional electromagnetic simulation software, wherein the modeling comprises the following steps: the substrate part, the back gold part on the lower surface of the substrate, the dielectric layer part on the upper surface of the substrate, the gate transmission line part, the gate finger part, the drain transmission line, the drain metal strip part and the two source electrode parts on the upper surface of the dielectric layer; in addition to the above, for a dual-hole bridged transistor, it also includes an air bridge connecting two sources and two ground holes, as shown in fig. 15; for a dual-hole bridgeless transistor, two ground holes are included, as shown in fig. 16; for a single-hole bridged transistor, it also includes an air bridge connecting two sources and a single ground hole, as shown in FIG. 17; then carrying out two-port three-dimensional electromagnetic simulation on the transistor in the full frequency band, calculating Y parameters, and further obtaining a gate-drain parasitic capacitance C according to the Y parameters gd_finger Parasitic capacitance C inside drain ds_finger Parasitic capacitance C in gate gs_finger Variable gate internal parasitic capacitance ΔC gs_finger Variable drain internal parasitic capacitance ΔC ds_finger The first port is arranged as a gate transmission line edge and a back gold edge, and the second port is arranged as a drain transmission line edge and a back gold edge;
wherein Y is 6a (1,1)、Y 6a (1,2)、Y 6a (2,1)、Y 6a (2, 2) represents in turn the corresponding term in the Y parameter for the double-hole bridged transistor calculated in step 6, Y 61a And Z 61a Y and Z parameters of the same set of characteristics, which can be mutually converted, Y 62a And Z 62a Y and Z parameters of the same set of characteristics, which can be mutually converted, Y 63a And Z 63a Y and Z parameters of the same set of characteristics, which can be mutually converted, Y 64a And Z 64a Y parameter and Z parameter which are the same group of characteristics and can be mutually converted; im () and re () functions represent taking the virtual representation, respectivelyPart and take part, Y 1 (1,1)、Y 1 (2, 2) each represents a corresponding term, Z, in the Y parameter calculated in step 1 2 (1, 1) represents the corresponding term in the Z parameter calculated in the step 2, f represents the frequency, f l And f h Respectively represent a lower frequency limit and an upper frequency limit adopted in the parameter extraction process, Y ca Represent C gs_in And C ds_in The resulting effect, the value of which can be calculated from the two-hole bridged transistor in step 5, is shown as follows:
wherein Y is 52a (1, 1) and Y 52a (2, 2) as calculated in step 5, j representing an imaginary unit;
Z rl representing parasitic inductance L inside the gate g_finger Parasitic impedance Z inside grid grf Parasitic inductance L inside drain d_finger And drain internal parasitic impedance Z drf The resulting effect is shown by the following formula:
wherein Y is 3 (2, 1) represents the corresponding item in the Y parameter calculated in step 3, Y 4 (2, 1) represents the corresponding item in the Y parameter calculated in the step 4;
1) For a dual-hole bridged transistor, the parasitic capacitance ΔC inside the gate is variable gs_finger Variable drain internal parasitic capacitance ΔC ds_finger The method meets the following conditions:
ΔC gs_finger ＝0，ΔC ds_finger ＝0；
2) For a dual-hole bridgeless transistor, the parasitic capacitance ΔC inside the gate is variable gs_finger Variable drain internal parasitic capacitance ΔC ds_finger The following equation is satisfied:
wherein Y is 6b (1,1)、Y 6b (1,2)、Y 6b (2,1)、Y 6b (2, 2) represents in turn the corresponding terms in the Y parameter for the double-hole bridgeless transistor calculated in step 6, Y 61b And Z 61b Y and Z parameters of the same set of characteristics, which can be mutually converted, Y 62b And Z 62b Y and Z parameters of the same set of characteristics, which can be mutually converted, Y 63b And Z 63b Y and Z parameters of the same set of characteristics, which can be mutually converted, Y 64b And Z 64b Y parameter and Z parameter which are the same group of characteristics and can be mutually converted; im () and re () functions represent the imaginary and real parts, Y, respectively 1 (1,1)、Y 1 (2, 2) each represents a corresponding term, Z, in the Y parameter calculated in step 1 2 (1, 1) represents the corresponding term in the Z parameter calculated in the step 2, f represents the frequency, f l And f h Respectively represent a lower frequency limit and an upper frequency limit adopted in the parameter extraction process, Y cb Represent C gs_in And C ds_in The resulting effect can be calculated from the two-hole bridgeless transistor in step 5The following formula is shown:
wherein Y is 52b (1, 1) and Y 52b (2, 2) from step 5;
3) For a single-hole bridged transistor, the parasitic capacitance ΔC inside the gate is variable gs_finger Variable drain internal parasitic capacitance ΔC ds_finger The following equation is satisfied:
wherein Y is 6c (1,1)、Y 6c (1,2)、Y 6c (2,1)、Y 6c (2, 2) represents in turn the corresponding terms in the Y parameter for the single-hole bridged transistor calculated in step 6, Y 61c And Z 61c Y and Z parameters of the same set of characteristics, which can be mutually converted, Y 62c And Z 62c Is the Y parameter and Z parameter of the same set of characteristics,can be mutually converted, Y 63c And Z 63c Y and Z parameters of the same set of characteristics, which can be mutually converted, Y 64c And Z 64c Y parameter and Z parameter which are the same group of characteristics and can be mutually converted; im () and re () functions represent the imaginary and real parts, Y, respectively 1 (1,1)、Y 1 (2, 2) each represents a corresponding term, Z, in the Y parameter calculated in step 1 2 (1, 1) represents the corresponding term in the Z parameter calculated in the step 2, f represents the frequency, f l And f h Respectively represent a lower frequency limit and an upper frequency limit adopted in the parameter extraction process, Y cc Represent C gs_in And C ds_in The resulting effect, the value of which can be calculated for a single-hole bridged transistor in step 5, is shown as follows:
wherein Y is 52c (1, 1) and Y 52c (2, 2) from step 5;
Therefore, the initial values of the parasitic parameters are set as the parasitic parameters extracted in the steps 1-6, and all the parasitic parameters are optimized according to the parasitic cost function to obtain final parasitic parameters;
The parasitic cost function is:
wherein J is i,j And K is equal to i,j Are all preset weights, J i,j ＝0.125、K i,j ＝0.125；S a (i, j) represents the result of circuit simulation of parasitic element (S parameter), S b (i, j) represents a three-dimensional electromagnetic simulation result; in the cost function, the front term represents the amplitude error, and the rear term represents the phase error; the cost function is disclosed in reference 1, and will not be described here.
Based on the above steps, typical values of parasitic parameters extracted from the bridged bipolar transistor in this embodiment are shown in table 1:
TABLE 1
Typical values of parasitic parameters extracted from the bridgeless bipolar transistor are shown in table 2:
TABLE 2
Typical values of parasitic parameters extracted for a bridged single-hole transistor are shown in table 3:
TABLE 3 Table 3
After the parasitic parameter extraction process, the intrinsic parameters are extracted as follows:
After de-embedding, the input, output and grounding reference surfaces are changed into G1, D1 and S1 respectively, and only comprise intrinsic elements; grid source intrinsic capacitance C gs Intrinsic resistance R of gate source i Grid leakage intrinsic capacitance C gd Grid leakage intrinsic resistance R gd Intrinsic capacitance C of drain source ds Intrinsic resistance R of drain source ds The intrinsic parameters of the voltage controlled current source VCCS satisfy the following equation:
wherein g m Representing the transconductance of the voltage-controlled current source VCCS, ω representing the angular frequency, τ representing the delay of the voltage-controlled current source VCCS;
double-hole bridge transistor and double-hole bridge-free crystal according to intrinsic cost functionThe body tube and the single-hole bridge transistor respectively perform intrinsic parameter optimization, and all the intrinsic parameters are optimized: grid source intrinsic capacitance C gs Intrinsic resistance R of gate source i Grid leakage intrinsic capacitance C gd Grid leakage intrinsic resistance R gd Intrinsic capacitance C of drain source ds Intrinsic resistance R of drain source ds And a voltage controlled current source VCCS, obtaining an intrinsic parameter value;
the eigencost function is:
Wherein J is i,j And K is equal to i,j Also is a preset weight, S c (i, j) represents the result of circuit simulation of the small signal model, S d (i, j) represents a test result;
intrinsic parameters of three types of transistors are fused:
respectively averaging the intrinsic parameters of the three types of transistors after optimization, and evaluating the degree of deviation of the intrinsic parameters of the double-hole bridge transistor, the double-hole bridge-free transistor and the single-hole bridge transistor from the average value by using the following error function; if the error is more than or equal to 10%, the intrinsic parameters are kept unchanged (original values after optimization are kept), and if the error is less than 10%, the intrinsic parameters are updated to corresponding average values;
the error functions for the double-hole bridged transistor, the double-hole non-bridged transistor and the single-hole bridged transistor are as follows in sequence:
wherein M is a 、M b 、M c Intrinsic parameter values of a double-hole bridged transistor, a double-hole non-bridged transistor and a single-hole bridged transistor respectively,
is the average value corresponding to the intrinsic parameters.
Double-hole bridge transistorThe final extracted intrinsic parameters are shown in table 4, the final extracted intrinsic parameters of the double-hole bridgeless transistor are shown in table 5, and typical values of the final extracted intrinsic parameters of the single-hole bridgeless transistor are shown in table 6; as can be seen from comparison of tables 4, 5 and 6, C gd 、C gs 、C ds 、R gd 、g m The element τ remains unchanged, R i 、R ds There is a certain variation due to the passive structure having a certain influence on the active layer; thus, in the model C gd 、C gs 、C ds 、R gd 、g m The tau element being shared by three transistors, R i 、R ds The elements are assigned values respectively.
TABLE 4 Table 4
| C gd (fF) | C gs (fF) | C ds (fF) | R gd (Ω) |
| 5 | 25 | 2 | 50 |
| R i (Ω) | R ds (Ω) | g m (mS) | τ(ps) |
| 2 | 170 | 69 | 0 |
TABLE 5
| C gd (fF) | C gs (fF) | C ds (fF) | R gd (Ω) |
| 5 | 25 | 2 | 50 |
| R i (Ω) | R ds (Ω) | g m (mS) | τ(ps) |
| 2 | 140 | 69 | 0 |
TABLE 6
| C gd (fF) | C gs (fF) | C ds (fF) | R gd (Ω) |
| 5 | 25 | 2 | 50 |
| R i (Ω) | R ds (Ω) | g m (mS) | τ(ps) |
| 22 | 160 | 69 | 0 |
Further, in the present embodiment, for an InP HEMT transistor of 35nm, in a usual amplified state (bias point: V gs ＝0.2V、V ds The comparison of the circuit simulation results and the test results of the double-hole bridged transistor model based on the parasitic parameters of table 1 and the intrinsic parameters of table 4 are shown in fig. 18 to 21; based on the parasitic parameters of table 2 and the intrinsic parameters of table 5, the comparison between the circuit simulation result and the test result of the double-hole bridgeless transistor model is shown in fig. 22 to 25; comparison of circuit simulation results and test results for single-hole bridged transistor models based on the parasitic parameters of Table 3 and the intrinsic parameters of Table 6As shown in fig. 26 to 29; as can be seen from the graph, for the double-hole bridgeless transistor, the small signal model also obtains higher precision, and can better simulate the performance of the device in an amplified state; the amplitude pairs of the S21 and S11 parameters of the circuit simulation results and the test results of the transistors with the three structures are shown in fig. 30 and 31, and the graphs show that the single-hole bridged transistor is reduced compared with the rest transistors in the aspects of the S21 gain and the S11 input port reflection coefficient, and the reconfigurable model provided by the invention can accurately simulate the three models respectively.
In summary, the invention provides the InP-based terahertz HMET transistor small-signal model and the parameter extraction method thereof, which can expand the modeling range to the common types of double-hole bridged transistors, single-hole bridged transistors and double-hole non-bridged transistors, effectively save modeling time and remarkably improve the simulation precision of the small-signal model.
While the invention has been described in terms of specific embodiments, any feature disclosed in this specification may be replaced by alternative features serving the equivalent or similar purpose, unless expressly stated otherwise; all of the features disclosed, or all of the steps in a method or process, except for mutually exclusive features and/or steps, may be combined in any manner.
Claims (10)
1. A reconfigurable model of an InP terahertz transistor, comprising: parasitic and intrinsic elements; it is characterized in that the method comprises the steps of,
the parasitic element includes: grid external parasitic impedance Z g Parasitic capacitance C outside grid g Parasitic capacitance C in the middle of grid gs_in Parasitic capacitance C in gate gs_finger Parasitic impedance Z inside grid grf Parasitic inductance L inside grid g_finger Parasitic capacitance C of gate and drain gd_finger Parasitic impedance Z inside drain drf Parasitic inductance L inside drain d_finger Parasitic capacitance C inside drain ds_finger Parasitic capacitance C in the middle of drain ds_in Drain external parasitic impedance Z d Drain external parasitic capacitance C d Source impedance Z srf Parasitic inductance L of source electrode s Parasitic capacitance delta C in the middle of variable grid gs_in Variable drain middle parasitic capacitance ΔC ds_in Variable gate internal parasitic capacitance ΔC gs_finger Variable drain internal parasitic capacitance ΔC ds_finger Variable source parasitic inductance Δl s Variable source impedance ΔZ srf The method comprises the steps of carrying out a first treatment on the surface of the Wherein,,
the gate external parasitic impedance Z g Parasitic capacitance C outside the gate g Connected in series between an external gate node G and an external source node S, the drain external parasitic impedance Z d Parasitic capacitance C outside the drain d Connected in series between an external drain node D and an external source node S, the source parasitic inductance L s Impedance Z with source electrode srf Connected in series between the external source node S and the intrinsic source node S1, the parasitic capacitance C in the middle of the grid electrode gs_in And variable gate middle parasitic capacitance delta C gs_in Connected in parallel between the external gate node G and the intrinsic source node S1, the drain middle parasitic capacitance C ds_in And variable drain middle parasitic capacitance delta C ds_in Connected in parallel between the external drain node D and the intrinsic source node S1, the internal parasitic impedance Z of the grid electrode grf Parasitic inductance L inside the gate g_finger Connected in series between the external gate node G and the intrinsic gate node G1, the drain internal parasitic impedance Z drf Parasitic inductance L inside the drain d_finger Connected in series between the external drain node D and the intrinsic drain node D1, the parasitic capacitance C inside the gate gs_finger And variable gate internal parasitic capacitance ΔC gs_finger Connected in parallel between the intrinsic gate node G1 and the intrinsic source node S1, the drain internal parasitic capacitance C ds_finger And variable drain internal parasitic capacitance ΔC ds_finger Connected in parallel between the intrinsic drain node D1 and the intrinsic source node S1, the gate-drain parasitic capacitance C gd_finger Connected between the intrinsic gate node G1 and the intrinsic drain node D1, the variable source parasitic inductance DeltaL s And variable source impedance deltaz srf Series connection ofAnd then between the external source node S and the intrinsic source node S1.
2. A reconfigurable model of an InP terahertz transistor according to claim 1, wherein said eigenelements comprise: grid source intrinsic capacitance C gs Intrinsic resistance R of gate source i Grid leakage intrinsic capacitance C gd Grid leakage intrinsic resistance R gd Intrinsic capacitance C of drain source ds Intrinsic resistance R of drain source ds And a voltage-controlled current source VCCS, wherein the gate-source intrinsic capacitance C gs Intrinsic resistance R of gate source i Connected in series between the intrinsic gate node G1 and the intrinsic source node S1, the gate-drain intrinsic capacitance C gd And gate-drain intrinsic resistance R gd Connected in series between the intrinsic gate node G1 and the intrinsic drain node D1, the drain-source intrinsic capacitance C ds Intrinsic resistance R of drain source ds Is connected in parallel with the voltage-controlled current source VCCS between the intrinsic drain node D1 and the intrinsic source node S1.
3. The method for extracting parameters of a reconfigurable model of an InP terahertz transistor according to claim 1, comprising: parasitic parameter extraction and intrinsic parameter extraction; the parasitic parameter extraction method is characterized by comprising the following steps of:
step 1, modeling a part of a structure of a transistor in three-dimensional electromagnetic simulation software, wherein the step comprises the following steps: the substrate part is positioned at the back gold part of the lower surface of the substrate, the dielectric layer part is positioned at the upper surface of the substrate, and the gate transmission line part and the drain transmission line part are positioned at the upper surface of the dielectric layer; then carrying out two-port three-dimensional electromagnetic simulation on the transistor in the full frequency band, calculating Y parameter and Z parameter, and further obtaining external parasitic impedance Z of the grid electrode according to the calculation of the Z parameter g Parasitic capacitance C outside grid g Drain external parasitic impedance Z d Drain external parasitic capacitance C d ；
Step 2, modeling a transistor part structure in three-dimensional electromagnetic simulation software, including: a substrate part, a back gold part positioned on the lower surface of the substrate, and a dielectric layer positioned on the upper surface of the substrateThe part is positioned on the single source electrode part on the upper surface of the dielectric layer and is provided with a source electrode grounding hole; then, single-port three-dimensional electromagnetic simulation is carried out on the transistor in the full frequency band, Z parameters are calculated, and then source electrode impedance Z is obtained according to the Z parameters srf Parasitic inductance L of source electrode s Variable source parasitic inductance Δl s Variable source impedance ΔZ srf ；
Step 3, modeling a part of the structure of the transistor in three-dimensional electromagnetic simulation software, including: the substrate part, the back gold part positioned on the lower surface of the substrate, the dielectric layer part positioned on the upper surface of the substrate, the gate transmission line part, the gate finger part and the extension part thereof positioned on the upper surface of the dielectric layer; then carrying out two-port three-dimensional electromagnetic simulation on the transistor in the full frequency band, calculating Y parameters, and further obtaining parasitic inductance L in the grid electrode according to the Y parameters g_finger Parasitic impedance Z inside grid grf ；
Step 4, modeling a part of the structure of the transistor in three-dimensional electromagnetic simulation software, wherein the step comprises the following steps: the substrate part, the back gold part positioned on the lower surface of the substrate, the dielectric layer part positioned on the upper surface of the substrate, the drain electrode transmission line part, the drain electrode metal strip part and the extension part thereof positioned on the upper surface of the dielectric layer; then carrying out two-port three-dimensional electromagnetic simulation on the transistor in the full frequency band, calculating Y parameters, and further obtaining the parasitic inductance L in the drain electrode according to the Y parameters d_finger Parasitic impedance Z inside drain drf ；
Step 5, modeling a part of the structure of the transistor in three-dimensional electromagnetic simulation software, including: the substrate part, the back gold part positioned on the lower surface of the substrate, the dielectric layer part positioned on the upper surface of the substrate, the grid transmission line part, the drain transmission line part and the two source electrode parts positioned on the upper surface of the dielectric layer; for the double-hole bridged transistor, the double-hole bridged transistor also comprises an air bridge connected with two source electrodes and two grounding holes; for a dual-hole bridgeless transistor, two ground holes are also included; for a single-hole bridged transistor, the single-hole bridged transistor also comprises an air bridge for connecting two sources and a single grounding hole; then respectively carrying out two-port three-dimensional electromagnetic simulation on the three types of transistors in the full frequency band, calculating Y parameters, and further calculating according to the Y parametersObtaining the parasitic capacitance C in the middle of the grid electrode of the three types of transistors gs_in Parasitic capacitance C in the middle of drain ds_in Parasitic capacitance delta C in the middle of variable grid gs_in Variable drain middle parasitic capacitance ΔC ds_in ；
Step 6, modeling the complete structure of the transistor in three-dimensional electromagnetic simulation software, wherein the step comprises the following steps: the substrate part, the back gold part on the lower surface of the substrate, the dielectric layer part on the upper surface of the substrate, the gate transmission line part, the gate finger part, the drain transmission line, the drain metal strip part and the two source electrode parts on the upper surface of the dielectric layer; for the double-hole bridged transistor, the double-hole bridged transistor also comprises an air bridge connected with two source electrodes and two grounding holes; for a dual-hole bridgeless transistor, two ground holes are also included; for a single-hole bridged transistor, the single-hole bridged transistor also comprises an air bridge for connecting two sources and a single grounding hole; then carrying out two-port three-dimensional electromagnetic simulation on the transistor in the full frequency band, calculating Y parameters, and further obtaining a gate-drain parasitic capacitance C according to the Y parameters gd_finger Parasitic capacitance C inside drain ds_finger Parasitic capacitance C in gate gs_finger Variable gate internal parasitic capacitance ΔC gs_finger Variable drain internal parasitic capacitance ΔC ds_finger ；
Step 7, the parasitic impedance Z outside the grid electrode g Parasitic capacitance C outside grid g Parasitic capacitance C in the middle of grid gs_in Parasitic capacitance C in gate gs_finger Parasitic impedance Z inside grid grf Parasitic inductance L inside grid g_finger Parasitic capacitance C of gate and drain gd_finger Parasitic impedance Z inside drain drf Parasitic inductance L inside drain d_finger Parasitic capacitance C inside drain ds_finger Parasitic capacitance C in the middle of drain ds_in Drain external parasitic impedance Z d Drain external parasitic capacitance C d Source impedance Z srf Parasitic inductance L of source electrode s Parasitic capacitance delta C in the middle of variable grid gs_in Variable drain middle parasitic capacitance ΔC ds_in Variable gate internal parasitic capacitance ΔC gs_finger Variable drain internal parasitic capacitance ΔC ds_finger Variable source parasitic inductance Δl s Variable source impedance ΔZ srf Setting the parasitic parameters extracted in the steps 1-6, and optimizing all the parasitic parameters according to the parasitic cost function to obtain final parasitic parameters.
4. The method for extracting parameters of a reconfigurable model of an InP terahertz transistor as claimed in claim 3, wherein in step 1, the gate external parasitic impedance Z g Parasitic capacitance C outside grid g Drain external parasitic impedance Z d Drain external parasitic capacitance C d The following equation is satisfied:
wherein Z is 1 (1, 1) and Z 1 (2, 2) represents the corresponding term of the Z parameter in step 1, f represents the frequency, f l And f h Representing a lower frequency limit and an upper frequency limit, respectively.
5. The method for extracting parameters of a reconfigurable model of an InP terahertz transistor as claimed in claim 3, wherein in step 2, the source impedance Z srf Parasitic inductance L of source electrode s The following equation is satisfied:
for a dual-hole bridged transistor, the variable source parasitic inductance ΔL s Variable source impedance ΔZ srf The following equation is satisfied:
for a dual-hole bridgeless transistor, the source parasitic inductance Δl is variable s Variable source impedance ΔZ srf The following equation is satisfied:
for a single-hole bridged transistor, the variable source parasitic inductance ΔL s Variable source impedance ΔZ srf The method meets the following conditions: ΔL s ＝+∞，ΔZ srf ＝+∞；
Wherein Z is 2 (1, 1) represents the corresponding term of the Z parameter in step 2, f represents the frequency, f l And f h Representing a lower frequency limit and an upper frequency limit, respectively.
6. The method for extracting parameters of a reconfigurable model of an InP terahertz transistor as set forth in claim 3, wherein in step 3, the gate electrodeInternal parasitic inductance L g_finger Parasitic impedance Z inside grid grf The following equation is satisfied:
Wherein Y is 3 (2, 1) represents the corresponding term of the Y parameter in step 3, f represents the frequency, f l And f h Representing a lower frequency limit and an upper frequency limit, respectively.
7. The method for extracting parameters of a reconfigurable model of an InP terahertz transistor as set forth in claim 3, wherein in step 4, the drain internal parasitic inductance L d_finger Parasitic impedance Z inside drain drf The following equation is satisfied:
wherein Y is 4 (2, 1) represents the corresponding term in the Y parameter in step 4, f represents the frequency, f l And f h Representing a lower frequency limit and an upper frequency limit, respectively.
8. The method for extracting parameters of a reconfigurable model of an InP terahertz transistor as set forth in claim 3, wherein in step 5, the parasitic capacitance C in the middle of the gate gs_in Parasitic capacitance C in the middle of drain ds_in The following equation is satisfied:
wherein Y is 5a (1,1)、Y 5a (1,2)、Y 5a (2,1)、Y 5a (2, 2) the correspondence of Y parameter for the double-hole bridged transistor in step 5, Y 1 (1,1)、Y 1 (2, 2) represent the corresponding terms of the Y parameter in step 1, Z 2 (1, 1) represents the corresponding term of the Z parameter in step 2, f represents the frequency, f l And f h Respectively representing a lower frequency limit and an upper frequency limit;
for a dual-hole bridged transistor, the parasitic capacitance ΔC in the middle of the gate is variable gs_in Variable drain middle parasitic capacitance ΔC ds_in The method meets the following conditions: ΔC gs_in ＝0，ΔC ds_in ＝0；
For a dual-hole bridgeless transistor, the parasitic capacitance ΔC in the middle of the gate is variable gs_in Variable drain middle parasitic capacitance ΔC ds_in The following equation is satisfied:
wherein Y is 5b (1,1)、Y 5b (1,2)、Y 5b (2,1)、Y 5b (2, 2) sequentially representing the corresponding terms of the Y parameter for the dual-hole bridgeless transistor in step 5;
for a single-hole bridged transistor, the parasitic capacitance ΔC in the middle of the gate is variable gs_in Variable drain middle parasitic capacitance ΔC ds_in The following equation is satisfied:
wherein Y is 5c (1,1)、Y 5c (1,2)、Y 5c (2,1)、Y 5c (2, 2) represents the correspondence of the Y parameter for the single-hole bridged transistor in step 5.
9. The method for extracting parameters of a reconfigurable model of an InP terahertz transistor as claimed in claim 3, wherein in step 6, the gate-drain parasitic capacitance C gd_finger Parasitic capacitance C inside drain ds_finger Internal register of grid electrodeGenerating capacitor C gs_finger The following equation is satisfied:
wherein Y is 6a (1,1)、Y 6a (1,2)、Y 6a (2,1)、Y 6a (2,2) The corresponding terms of the Y parameter for the double-hole bridge transistor in step 6 are sequentially shown, Y 1 (1,1)、Y 1 (2, 2) represent the corresponding terms of the Y parameter in step 1, Z 2 (1, 1) represents the corresponding term of the Z parameter in step 2, Y 52a (1,1)、Y 52a (2, 2) representing the corresponding terms of the Y parameter in step 5, Y 3 (2, 1) represents the corresponding term of the Y parameter in step 3, Y 4 (2, 1) represents the corresponding term of the Y parameter in step 4, f represents the frequency, f l And f h Respectively representing a lower frequency limit and an upper frequency limit;
for a dual-hole bridged transistor, the parasitic capacitance ΔC inside the gate is variable gs_finger Variable drain internal parasitic capacitance ΔC ds_finger The method meets the following conditions: ΔC gs_finger ＝0，ΔC ds_finger ＝0；
For a dual-hole bridgeless transistor, the parasitic capacitance ΔC inside the gate is variable gs_finger Variable drain internal parasitic capacitance ΔC ds_finger The following equation is satisfied:
wherein Y is 6b (1,1)、Y 6b (1,2)、Y 6b (2,1)、Y 6b (2, 2) sequentially representing the corresponding terms of the Y parameter for the dual-hole bridgeless transistor in step 6; y is Y 52b (1,1)、Y 52b (2, 2) representing the corresponding terms of the Y parameter in step 5, respectively;
for a single-hole bridged transistor, the parasitic capacitance ΔC inside the gate is variable gs_finger Variable drain internal parasitic capacitance ΔC ds_finger The following equation is satisfied:
wherein Y is 6c (1,1)、Y 6c (1,2)、Y 6c (2,1)、Y 6c (2, 2) the correspondence of Y parameter for the single-hole bridged transistor in step 6, Y 52c (1,1)、Y 52c (2, 2) represent the corresponding terms of the Y parameter in step 5, respectively.
10. A method for extracting parameters of a reconfigurable model of an InP terahertz transistor according to claim 3, wherein said intrinsic parameter extraction comprises the steps of:
step 8, measuring the S parameter of the transistor under the full bias in the full frequency band, and calculating the corresponding Y parameter and Z parameter by the S parameter;
step 9, de-embedding the transistor full-band test Y parameter based on the parasitic parameter obtained in the step 7 to obtain an intrinsic Y parameter Y int The method comprises the steps of carrying out a first treatment on the surface of the And then according to the intrinsic Y parameter Y int And (3) calculating to obtain intrinsic parameters: grid source intrinsic capacitance C gs Intrinsic resistance R of gate source i Grid leakage intrinsic capacitance C gd Grid leakage intrinsic resistance R gd Intrinsic capacitance C of drain source ds Intrinsic resistance R of drain source ds A voltage controlled current source VCCS;
step 10, optimizing intrinsic parameters of a double-hole bridged transistor, a double-hole non-bridged transistor and a single-hole bridged transistor;
respectively optimizing intrinsic parameters of the double-hole bridge transistor, the double-hole bridge-free transistor and the single-hole bridge transistor according to the intrinsic cost function;
and then according to the optimized intrinsic parameters, judging and fusing the intrinsic parameters of the double-hole bridged transistor, the double-hole non-bridged transistor and the single-hole bridged transistor:
respectively averaging each intrinsic parameter, and calculating and respectively calculating error functions:
wherein M is a 、M b 、M c Intrinsic parameter values of a double-hole bridged transistor, a double-hole non-bridged transistor and a single-hole bridged transistor respectively,
the average value corresponding to the intrinsic parameters;
if the error is more than or equal to 10%, the intrinsic parameter is kept unchanged, and if the error is less than 10%, the intrinsic parameter is updated to a corresponding average value.
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