CN116415531A - InP HEMT small-signal equivalent circuit model, parameter extraction method, equipment and medium - Google Patents

InP HEMT small-signal equivalent circuit model, parameter extraction method, equipment and medium Download PDF

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CN116415531A
CN116415531A CN202111681602.4A CN202111681602A CN116415531A CN 116415531 A CN116415531 A CN 116415531A CN 202111681602 A CN202111681602 A CN 202111681602A CN 116415531 A CN116415531 A CN 116415531A
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parasitic
drain
gate
capacitance
source
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吕红亮
戚军军
安维
段兰燕
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ZTE Corp
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ZTE Corp
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    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/331—Design verification, e.g. functional simulation or model checking using simulation with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
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    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
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Abstract

The invention relates to the technical field of microelectronic devices and discloses an InP HEMT small-signal equivalent circuit model, a parameter extraction method, equipment and a medium. Wherein the equivalent circuit model includes: the device comprises a grid electrode, a drain electrode, a source electrode, an intrinsic module, a grid electrode parasitic module, a source electrode parasitic module, a drain electrode parasitic module and a grid electrode drain parasitic module; the grid electrode, the drain electrode and the source electrode are respectively connected to the grid electrode, the drain electrode and the source electrode internal node of the intrinsic module through the parasitic modules of the grid electrode, the drain electrode and the source electrode; two ends of the gate-drain parasitic module are respectively connected with the gate and the drain parasitic module; the model also comprises a grid electrode, a drain electrode and a grid-drain distributed capacitance; the first end of the grid and drain distributed capacitor is grounded, and the second end of the grid and drain distributed capacitor is connected to the joints of the two ends of the grid and drain parasitic module and the grid and drain parasitic module respectively; two ends of the grid-drain distribution capacitor are respectively connected to the connection parts of the first end and the second end of the grid-drain parasitic module and the grid parasitic module. Can reflect the distribution effect in the actual device.

Description

InP HEMT small-signal equivalent circuit model, parameter extraction method, equipment and medium
Technical Field
The embodiment of the invention relates to the technical field of microelectronic devices, in particular to an InP HEMT small-signal equivalent circuit model, a parameter extraction method, equipment and a medium.
Background
The device model is a bridge for connecting the device process and the circuit design, and the accurate and compact device model can play a role in guiding and accelerating the design process of the circuit. For the indium phosphide high electron mobility transistor (InP HEMT) widely applied to the scenes of monolithic integrated circuits (Monolithic Microwave Integrated Circuit, abbreviated as MMIC) and the like due to the remarkable advantages of high cut-off frequency, low noise coefficient and the like, the establishment of an accurate large-signal equivalent circuit model and a noise equivalent circuit model has very important significance along with the widening of the application range and the improvement of the application frequency.
The basis of the establishment of the noise model and the large signal model is just a small signal equivalent circuit model, and the establishment of the noise model and the large signal model is gradually becoming the focus and hot spot of research in the technical field of microelectronics nowadays. The small-signal equivalent circuit model is determined by the topological structure of the InP HEMT, and the electrical characteristics of the device are represented. Each parameter in the topological structure of the model has a specific physical meaning, and the topological structures of different device structures are different, so that the accuracy of the topological structure and model parameters of the small-signal equivalent circuit model determines the modeling accuracy of the small-signal model.
InP HEMT devices are widely used in the rf microwave field due to their excellent frequency characteristics. However, with the increase of the application frequency, the traditional small-signal circuit model is difficult to embody the distribution effect in the device, the modeling precision is insufficient, and the high-frequency characteristic of the device cannot be accurately represented.
Disclosure of Invention
The invention mainly aims at providing an InP HEMT small-signal equivalent circuit model, a parameter extraction method, equipment and a medium, which are used for enabling the small-signal equivalent circuit model to embody the distribution effect of devices.
To achieve the above object, an embodiment of the present invention provides an InP HEMT small-signal equivalent circuit model, the model including: the device comprises a grid electrode, a drain electrode, a source electrode, an intrinsic module, a grid electrode parasitic module, a source electrode parasitic module, a drain electrode parasitic module and a grid electrode drain parasitic module; the grid is connected to a grid internal node of the intrinsic module through the grid parasitic module, the drain is connected to a drain internal node of the intrinsic module through the drain parasitic module, and the source is connected to a source internal node of the intrinsic module through the source parasitic module; the first end of the gate-drain parasitic module is connected with the gate parasitic module, and the second end of the gate-drain parasitic module is connected with the drain parasitic module; the model also comprises a grid distributed capacitance, a drain distributed capacitance and a grid-drain distributed capacitance; the first end of the grid distributed capacitor is grounded, and the second end of the grid distributed capacitor is connected to the joint of the first end of the grid drain parasitic module and the grid parasitic module; the first end of the drain distributed capacitor is grounded, and the second end of the drain distributed capacitor is connected to the connection part of the second end of the gate-drain parasitic module and the drain parasitic module; the first end of the gate-drain distribution capacitor is connected to the junction of the first end of the gate-drain parasitic module and the gate parasitic module, and the second end of the gate-drain distribution capacitor is connected to the junction of the second end of the gate-drain parasitic module and the drain parasitic module.
In order to achieve the above object, an embodiment of the present invention provides a method for extracting parameters of an InP HEMT small-signal equivalent circuit model, which is the above model, including: acquiring a first equivalent circuit model, and determining the value of parasitic inductance of the model according to the impedance parameter of the first equivalent circuit model; the first equivalent circuit model is an equivalent circuit model obtained by performing de-embedding treatment on the resistor in the model; the parasitic inductance comprises a grid parasitic inductance, a source parasitic inductance and a drain parasitic inductance; the resistor comprises a grid parasitic resistor, a source parasitic resistor, a drain parasitic resistor, a grid source intrinsic resistor and a drain source intrinsic resistor; acquiring a second equivalent circuit model, and determining the values of parasitic capacitance and distributed capacitance of the model according to admittance parameters of the second equivalent circuit model; the second equivalent circuit model is an equivalent circuit model obtained by performing de-embedding treatment on the resistor and the parasitic inductor in the model; the parasitic capacitance comprises a grid parasitic capacitance, a source parasitic capacitance, a drain parasitic capacitance and a grid drain parasitic capacitance; the distributed capacitance comprises a grid distributed capacitance, a drain distributed capacitance and a grid-drain distributed capacitance; acquiring a third equivalent circuit model, and determining the value of the parasitic resistance of the model according to the impedance parameter of the third equivalent circuit model; the third equivalent circuit model is an equivalent circuit model obtained by performing de-embedding treatment on the capacitance and the parasitic inductance in the model; the capacitance includes the parasitic capacitance, the distributed capacitance, and an intrinsic capacitance; the parasitic resistances include the gate parasitic resistance, the source parasitic resistance, and the drain parasitic resistance; acquiring a fourth equivalent circuit model, and determining the numerical value of an intrinsic unit of the model according to the admittance parameter of the fourth equivalent circuit model; the fourth equivalent circuit model is an equivalent circuit model of an intrinsic module of the model; the intrinsic unit comprises a gate-drain intrinsic capacitance, a gate-source intrinsic resistance, a drain-source intrinsic resistance and a drain-source intrinsic capacitance.
To achieve the above object, an embodiment of the present invention provides an electronic device including: at least one processor; and a memory communicatively coupled to the at least one processor; the memory stores instructions executable by the at least one processor, so that the at least one processor can execute the parameter extraction method of the InP HEMT small-signal equivalent circuit model.
To achieve the above object, an embodiment of the present invention provides a computer-readable storage medium storing a computer program which, when executed by a processor, implements the above-mentioned method for extracting parameters of an InP HEMT small-signal equivalent circuit model.
In an embodiment of the invention, the InP HEMT small-signal equivalent circuit model comprises a gate distribution capacitance, a drain distribution capacitance and a gate-drain distribution capacitance for characterizing a distribution effect between the gate fingers of the InP HEMT device. Compared with the traditional InP HEMT small-signal equivalent circuit model, the equivalent circuit model provided by the invention can reflect the distribution effect in an actual device, more accurately reflect the property of the actual device, and has important significance for the design of the device based on the InP HEMT.
Drawings
One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which the figures do not depict a proportional limitation unless expressly stated otherwise.
Fig. 1 is a schematic structural diagram of an InP HEMT small-signal equivalent circuit model according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of another InP HEMT small-signal equivalent circuit model according to an embodiment of the present invention;
fig. 3 is a schematic flow chart of a method for extracting InP HEMT small-signal equivalent circuit model parameters according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a first equivalent circuit model according to an embodiment of the present invention;
FIG. 5 shows the product of ω and the impedance parameter and ω according to an embodiment of the present invention 2 Is a functional relationship diagram of (2);
FIG. 6 is a schematic diagram of a second equivalent circuit model according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of a third equivalent circuit model according to an embodiment of the present invention;
FIG. 8 is a schematic diagram of Re (Z) 22 ) And Re (Z) 12 ) Respectively follow 1/(V) gs -V th ) A graph of changing functional relationships;
FIG. 9 is a schematic diagram of Re (Z) 11 ) And 1/I g Is a functional relationship diagram of (2);
FIG. 10 is a schematic diagram of a fourth equivalent circuit model according to an embodiment of the present invention;
FIG. 11 is a diagram showing comparison between simulation results and test data of an equivalent circuit model according to an embodiment of the present invention;
fig. 12 is a schematic structural diagram of an electronic device according to an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, those of ordinary skill in the art will understand that in various embodiments of the present invention, numerous technical details have been set forth in order to provide a better understanding of the present invention. However, the claimed invention may be practiced without these specific details and with various changes and modifications based on the following embodiments. The following divisions of the embodiments are for convenience of description, and should not be construed as limiting the specific embodiments of the present invention, and the embodiments may be mutually combined and referred to without contradiction.
The term "comprising" as used herein refers to the presence of a feature, step or element, but does not exclude the presence or addition of one or more other features, steps or elements. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
In addition, in the description of the embodiments of the present application, the terms "first," "second," "third," etc. are used merely for descriptive purposes and distinguishing between similar objects, and not necessarily for describing a sequential or chronological order, nor should it be construed as indicating or implying relative importance.
An embodiment of the invention relates to an InP HEMT small-signal equivalent circuit model, and a circuit structure diagram is shown in fig. 1.
In this embodiment, the InP HEMT small-signal equivalent circuit model includes: the device comprises a grid electrode, a drain electrode, a source electrode, an intrinsic module, a grid electrode parasitic module, a source electrode parasitic module, a drain electrode parasitic module and a grid electrode drain parasitic module; the grid is connected to a grid internal node of the intrinsic module through the grid parasitic module, the drain is connected to a drain internal node of the intrinsic module through the drain parasitic module, and the source is connected to a source internal node of the intrinsic module through the source parasitic module; the first end of the gate-drain parasitic module is connected with the gate parasitic module, and the second end of the gate-drain parasitic module is connected with the drain parasitic module; the model also comprises a grid distributed capacitance, a drain distributed capacitance and a grid-drain distributed capacitance; the first end of the grid distributed capacitor is grounded, and the second end of the grid distributed capacitor is connected to the joint of the first end of the grid drain parasitic module and the grid parasitic module; the first end of the drain distributed capacitor is grounded, and the second end of the drain distributed capacitor is connected to the connection part of the second end of the gate-drain parasitic module and the drain parasitic module; the first end of the gate-drain distribution capacitor is connected to the junction of the first end of the gate-drain parasitic module and the gate parasitic module, and the second end of the gate-drain distribution capacitor is connected to the junction of the second end of the gate-drain parasitic module and the drain parasitic module.
The implementation details of the InP HEMT small-signal equivalent circuit model in the present embodiment are specifically described below, and the following is only for facilitating understanding of the implementation details of the present embodiment, and is not necessary for implementing the present embodiment. The specific structure is shown in figure 1.
The InP HEMT small-signal equivalent circuit model comprises: gate 101, drain 102, source 103, intrinsic module 108, gate parasitic module 104, source parasitic module 105, drain parasitic module 106, and gate drain parasitic module 107; the gate 101 is connected to the intra-gate node of the intrinsic module 108 through the gate parasitic module 104, the drain 102 is connected to the intra-drain node of the intrinsic module 108 through the drain parasitic module 106, and the source 103 is connected to the intra-source node of the intrinsic module 108 through the source parasitic module 105; a first end of the gate-drain parasitic module 106 is connected with the gate parasitic module 104, and a second end of the gate-drain parasitic module 107 is connected with the drain parasitic module 106; the model also includes a gate distributed capacitance 109, a drain distributed capacitance 1010, and a gate drain distributed capacitance 1011; the first end of the grid distributed capacitor 109 is grounded, and the second end is connected to the connection part of the first end of the grid leakage parasitic module 107 and the grid parasitic module 104; the first end of the drain distributed capacitor 1010 is grounded, and the second end is connected to the connection of the second end of the gate-drain parasitic module 107 and the drain parasitic module 106; a first end of the gate-drain distributed capacitor 1011 is connected to a junction of the first end of the gate-drain parasitic module 106 and the gate parasitic module 104, and a second end of the gate-drain distributed capacitor 1011 is connected to a junction of the second end of the gate-drain parasitic module 107 and the drain parasitic module 106.
In one example, the gate parasitic module includes a gate parasitic resistance, a gate parasitic inductance, and a gate parasitic capacitance; the drain parasitic module comprises a drain parasitic resistor, a drain parasitic inductance and a drain parasitic capacitance; the source parasitic module comprises a source parasitic resistor and a source parasitic inductor; the gate-drain parasitic module comprises a gate-drain parasitic capacitor; the first end of the gate parasitic inductance and the first end of the gate parasitic capacitance are connected to the first end of the gate parasitic resistance, the second end of the gate parasitic inductance is connected to the gate of the model, the second end of the gate parasitic capacitance is connected to the source parasitic module, and the second end of the gate parasitic resistance is connected to the gate internal node; the first end of the drain parasitic inductance and the first end of the drain parasitic capacitance are connected to the first end of the drain parasitic resistance, the second end of the drain parasitic inductance is connected to the drain of the model, the second end of the drain parasitic capacitance is connected to the junction of the source parasitic module and the second end of the gate parasitic capacitance, and the second end of the drain parasitic resistance is connected to the drain internal node; the first end of the source parasitic resistor is connected with the first end of the source parasitic capacitor, the second end of the source parasitic resistor is connected with the source internal node, and the second end of the source parasitic inductor is connected with the source of the model; the second end of the gate parasitic capacitor is connected to the source parasitic module, specifically, the second end of the gate parasitic capacitor is connected to a connection position of the source parasitic resistor and the source parasitic inductor in the source parasitic module.
In this example, the first end of the gate-drain parasitic module is connected to the gate parasitic module, specifically, the first end of the gate-drain parasitic capacitor is connected to the first end of the gate parasitic resistor in the gate parasitic module; the second end of the gate-drain parasitic module is connected with the drain parasitic module, and particularly, the second end of the gate-drain parasitic capacitor is connected with the first end of the drain parasitic resistor in the drain parasitic module.
In the InP HEMT small-signal equivalent circuit model according to the present embodiment, the intrinsic module may further include: the gate-source intrinsic capacitance between the gate internal node and the drain internal node, the gate-source intrinsic capacitance between the gate internal node and the source internal node, and the gate-source intrinsic resistance connected in series with the gate-source intrinsic capacitance, the drain-source intrinsic resistance between the drain internal node and the source internal node, and the drain-source intrinsic capacitance connected in parallel with the drain-source intrinsic resistance. The circuit configuration diagram of the InP HEMT small-signal equivalent circuit model in this example is shown in fig. 2.
In the InP HEMT small-signal equivalent circuit model shown in fig. 2, C pg Is parasitic capacitance of grid electrode C pd Is parasitic capacitance of drain electrode, C pgd Parasitic capacitance is used as the gate drain; l (L) g 、L d 、L s The parasitic inductance of the grid, the parasitic inductance of the drain and the parasitic inductance of the source are respectively introduced by the grid, the drain and the source bonding pads; r is R g For the gate pad and the gate parasitic resistance introduced by the schottky contact of the gate port, R s And R is d Source and drain parasitic resistances introduced for the source and drain pads, respectively. The intrinsic capacitance includes: grid source intrinsic capacitance C gs Grid leakage intrinsic capacitance C gd Drain-source intrinsic capacitance C ds The method comprises the steps of carrying out a first treatment on the surface of the The intrinsic resistance includes: grid source intrinsic resistance R is (also called as gate-source channel resistance) and drain-source intrinsic resistance R ds 。
It is worth mentioning that the intrinsic transconductance g shown in FIG. 2 m To output current I ds Relative to input voltage V gs Which reflects the variation of the output current with the output voltage. The transconductance delay factor τ is g corresponding to the change in gate voltage m Varying delay times.
The inventor of the invention discovers that for a multi-finger HEMT device, as the frequency increases, the distribution effect among the gate fingers of the multi-finger device becomes more and more remarkable, but the traditional small signal model has the problem that the electrical characteristics of the device cannot be accurately represented. In an embodiment of the invention, the InP HEMT small-signal equivalent circuit model comprises a gate distribution capacitance, a drain distribution capacitance and a gate-drain distribution capacitance for characterizing a distribution effect between the gate fingers of the InP HEMT device. Compared with the traditional InP HEMT small-signal equivalent circuit model, the equivalent circuit model provided by the invention can reflect the distribution effect in an actual device, more accurately reflect the property of the actual device, and has important significance for the design of the device based on the InP HEMT.
An embodiment of the present invention relates to a method for extracting parameters of an InP HEMT small-signal equivalent circuit model, wherein the InP HEMT small-signal equivalent circuit model is as described in the above embodiment.
In this embodiment, a first equivalent circuit model is obtained, and a value of parasitic inductance of the model is determined according to an impedance parameter of the first equivalent circuit model; the first equivalent circuit model is an equivalent circuit model obtained by performing de-embedding treatment on the resistor in the model; the parasitic inductance comprises a grid parasitic inductance, a source parasitic inductance and a drain parasitic inductance; the resistor comprises a grid parasitic resistor, a source parasitic resistor, a drain parasitic resistor, a grid source intrinsic resistor and a drain source intrinsic resistor; acquiring a second equivalent circuit model, and determining the values of parasitic capacitance and distributed capacitance of the model according to admittance parameters of the second equivalent circuit model; the second equivalent circuit model is an equivalent circuit model obtained by performing de-embedding treatment on the resistor and the parasitic inductor in the model; the parasitic capacitance comprises a grid parasitic capacitance, a source parasitic capacitance, a drain parasitic capacitance and a grid drain parasitic capacitance; the distributed capacitance comprises a grid distributed capacitance, a drain distributed capacitance and a grid-drain distributed capacitance; acquiring a third equivalent circuit model, and determining the value of the parasitic resistance of the model according to the impedance parameter of the third equivalent circuit model; the third equivalent circuit model is an equivalent circuit model obtained by performing de-embedding treatment on the capacitance and the parasitic inductance in the model; the capacitance includes the parasitic capacitance, the distributed capacitance, and an intrinsic capacitance; the parasitic resistances include the gate parasitic resistance, the source parasitic resistance, and the drain parasitic resistance; acquiring a fourth equivalent circuit model, and determining the numerical value of an intrinsic unit of the model according to the admittance parameter of the fourth equivalent circuit model; the fourth equivalent circuit model is an equivalent circuit model of an intrinsic module of the model; the intrinsic unit comprises a gate-drain intrinsic capacitance, a gate-source intrinsic resistance, a drain-source intrinsic resistance and a drain-source intrinsic capacitance.
The implementation details of the method for extracting parameters of the InP HEMT small-signal equivalent circuit model in the present embodiment are specifically described below, and the following is only for facilitating understanding the implementation details of the present embodiment, and is not necessary for implementing the present embodiment. The specific flow is shown in fig. 3, and may include the following steps:
step 301, a first equivalent circuit model is obtained, and the value of the parasitic inductance of the model is determined according to the impedance parameter of the first equivalent circuit model.
In one example, this step may include obtaining an expression of the product of ω and the impedance parameter of the first equivalent circuit model, with respect to ω according to the imaginary part of the expression 2 And the slope of (a) determines the value of the parasitic inductance.
The method for determining the value of the parasitic inductance of the model according to this example may be specifically implemented by the following technical means. An equivalent circuit for calculating the parasitic inductance value is first determined. Because under the condition of cold pinch-off, the conductance g of the source-drain current source m And output conductance G ds The depletion region of the device can be ignored and thus characterized by three capacitances. In addition, since the parasitic resistance and inductance are sensitive to the S parameter in the low frequency band, in order to extract the parasitic capacitance more accurately and conveniently, it is necessary to extract the parasitic inductance in the high frequency band (i.e., the band greater than 25 GHz). Further, since the parasitic resistance does not affect the imaginary part of the Y parameter, the parasitic resistance may not be considered in extracting the parasitic inductance, i.e., it is not necessary to display it in the equivalent circuit. In combination with the above considerations, a method for determining parasitic capacitance can be obtainedAn equivalent circuit diagram of the values of (2) is shown in figure 4. In the equivalent circuit shown in fig. 4, the three intrinsic capacitances used to characterize the device depletion region parameters are respectively C shown in fig. 2 ig ，C id And C igd . The impedance parameter (Z parameter) can be expressed as
Figure BDA0003444331000000051
Figure BDA0003444331000000052
Figure BDA0003444331000000061
Wherein, the liquid crystal display device comprises a liquid crystal display device,
C xg ＝C pg +C dg (4)
C xd ＝C pd +C dd (5)
C xpg ＝C pgd +C dgd (6)
M＝(C xg +C ig +C xgd +C igd )(C xd +C id +C xgd +C igd )-(C xgd +C igd ) 2 (7)
multiplying Z parameter by omega, taking imaginary part to obtain:
Figure BDA0003444331000000062
Figure BDA0003444331000000063
Figure BDA0003444331000000064
based on the expressions (8) - (10), it is possible to obtainI m (ωZ ij ) With omega 2 The graph of the variation is shown in FIG. 5, and the abscissa in FIG. 5 is ω 2 The ordinate is I m (ωZ ij ). Can be represented by I in FIG. 5 m (ωZ ij ) And omega 2 The approximate slope of each functional relation curve is used for obtaining parasitic inductance L g 、L d And L s Is a numerical value of (2).
Step 302, a second equivalent circuit model is obtained, and the values of the parasitic capacitance and the distributed capacitance of the model are determined according to the admittance parameters of the second equivalent circuit model.
In one example, the step may include determining a value of a total capacitance between the gate and the drain, a value of a total capacitance between the gate and the source, and a value of a total capacitance between the source and the drain based on the admittance parameter and the value of the intrinsic capacitance of the second equivalent circuit model; determining the values of the parasitic capacitance and the distributed capacitance of the model according to the value of the total capacitance between the gate and the drain, the value of the total capacitance between the gate and the source, and the value of the total capacitance between the source and the drain; wherein the gate parasitic capacitance is equal to the source parasitic capacitance, and the gate distributed capacitance is equal to the drain distributed capacitance; the intrinsic capacitance comprises a gate-drain intrinsic capacitance, a gate-source intrinsic capacitance and a drain-source intrinsic capacitance.
The method for determining the values of the parasitic capacitance and the distributed capacitance of the model according to the present embodiment may be specifically implemented by the following technical means. In determining the equivalent circuit for calculating the parasitic capacitance value, the parasitic inductance L is compared with the structure of the equivalent circuit shown in fig. 4 g 、L d And L s The de-embedding is performed and a second equivalent circuit is determined as shown in fig. 6. And device gate width scaling is used to determine extrinsic parasitic and distributed capacitances.
In the first equivalent circuit as shown in fig. 6, the Y parameter can be expressed as:
Im(Y C11 )/ω＝C xg +C ig +C igd +C xgd (11)
Im(Y C22 )/ω＝C xd +C id +C igd +C xgd (12)
-Im(Y C12 )/ω＝C igd +C xgd (13)
intrinsic capacitance C when the device is turned off ig ，C id And C igd The linear relation with the gate width of the device can be expressed by the following expression:
C ig (W)＝C ig0 W (14)
C id (W)＝C id0 W (15)
C igd (W)＝C igd0 W (16)
wherein C is ig0 ，C id0 And C igd0 The capacitance scaling factors are respectively, and W is the gate width.
Substituting the expressions (14) to (16) into the expressions (11) to (13) to deduce the gate leakage capacitance C xg Grid source capacitance C xd Drain-source capacitance C xgd The expression of (2) is as follows:
Figure BDA0003444331000000071
Figure BDA0003444331000000072
Figure BDA0003444331000000073
substituting Y parameters of InP HEMT devices with four different sizes of 4×25μm, 4×50μm, 4×75μm and 4×150μm into formulas (17) - (19) for solving to obtain intrinsic capacitance C xg ，C xd And C xgd Is a numerical value of (2).
Further, a capacitance C that minimizes the difference between the measured value and the simulation value is determined among the calculated plurality of capacitance values xg ，C xd And C xgd The value of (2) is the optimal value of the capacitor.In practical implementation, C can be used in the process of determining the optimal value of the capacitor dg The value of (2) varies from 0 to C xg 、C dd From 0 to C xd 、C dgd From 0 to C xgd . In addition, in order to reduce the difficulty of the optimum value determination process, it can be assumed that:
C pg ≈C pd ,C dg ≈C dd (20)
when the error between the measured data and the simulation data reaches a minimum, the values of parasitic capacitance and distributed capacitance can be determined.
Step 303, obtaining a third equivalent circuit model, and determining the value of the parasitic resistance of the model according to the impedance parameter of the third equivalent circuit model.
In one example, the step may include determining values of the source parasitic resistance, the drain parasitic resistance, and the gate parasitic resistance based on a real part of an impedance parameter of the third equivalent circuit model.
The method for determining the value of the parasitic resistance of the model according to this example may be specifically implemented by the following means.
When an equivalent circuit for calculating the value of the parasitic resistance is determined, the parasitic capacitance can be de-embedded, so that the device works in a cold bias state. A third equivalent circuit that can be determined for calculating the parasitic capacitance value is shown in fig. 7.
In the equivalent circuit as shown in fig. 7, the Z parameter can be expressed by the following expression:
Z R11 ＝R s +R g +R j +jω(L s +L g ) (21)
Z R12 ＝Z 21 ＝R s +1/2R j +jωL s (22)
Z R22 ＝R s +R d +R c +jω(L s +L d ) (23)
wherein R is j ＝nKT/qI g ，I g And the leakage current of the device gate is given, and n is a gate Schottky diode management ideal factor.
As can be seen from formulas (21) - (23), the parasitic resistance R can be obtained by solving the real part of the Z parameter s And R is R d Is a numerical value of (2). Due to resistance R c Satisfy R c ∝1/(V gs -V th ) Therefore, equation (23) can be rewritten as AND (V) gs -V th ) The related function may yield the following expression:
Figure BDA0003444331000000074
Figure BDA0003444331000000075
and then at V ds ＝0、V gs The Z parameters were tested at different biases at-0.25V, 0V, 0.25V and 0.5V, respectively. Re (Z) 22 ) And Re (Z) 12 ) Respectively follow 1/(V) gs -V th ) The graph of the function of the variation is shown in fig. 8. Extrinsic resistance R can be obtained s And R is R d Is a value of (2).
In determining parasitic resistance R g When, firstly according to R j ∝nKT/qI g ∝1/I g Solving the resistance R j . Re (Z) 11 ) And 1/I g The functional relationship of (2) is shown in FIG. 9. The following expression can be obtained in combination with expression (21):
Re(Z R11 )| 1/Ig＝0 ＝R s +R g (26)
the parasitic resistance R can be determined according to the expression g Is a numerical value of (2).
And step 304, acquiring a fourth equivalent circuit model, and determining the numerical value of the intrinsic unit of the model according to the admittance parameter of the fourth equivalent circuit model.
After the extrinsic parameters of the small signal circuit model are determined through the above steps, the intrinsic parameters of the built InPHEMT small signal model may be determined for the intrinsic portion thereof. After all parasitic parameters are de-embedded in the equivalent circuit shown in fig. 1, a fourth equivalent circuit for determining the intrinsic parameters of the small signal circuit model can be obtained as shown in fig. 10.
In the equivalent circuit for determining the intrinsic parameters of the small signal circuit model as shown in fig. 10, the Y parameter expression can be obtained as follows:
Figure BDA0003444331000000081
Y 12 ＝-jωC gd (28)
Figure BDA0003444331000000082
Figure BDA0003444331000000083
by the expression of the above Y parameter, the expression of the intrinsic parameter can be obtained as follows:
R is ＝Re[1/(Y 11 +Y 12 )] (31)
Figure BDA0003444331000000084
Figure BDA0003444331000000085
Figure BDA0003444331000000086
Figure BDA0003444331000000087
R ds ＝Re[1/(Y 22 +Y 12 )] (36)
Figure BDA0003444331000000088
through the steps, the values of all parameters in the InP HEMT small-signal equivalent circuit model can be obtained, and the values are shown in the following table:
Figure BDA0003444331000000091
fig. 11 is a diagram comparing simulation results and test data of an InP HEMT small-signal equivalent circuit model after an extrinsic parasitic capacitance capable of reflecting device distribution effects is introduced. As shown in fig. 11, the InP HEMT model according to the present embodiment improves the fitting accuracy of the small signal model S parameters at high frequencies compared to the conventional InP HEMT model.
In summary, after the extrinsic distributed capacitance is added, the simulation result of the small signal model is well fitted with test data in the frequency range of 2-50 GHz, so that the small signal characteristic of the InP HEMT can be more accurately represented by the equivalent circuit model provided by the invention under high frequency compared with the traditional InP HEMT small signal equivalent circuit model.
The inventor of the invention considers the influence of the high-frequency distribution effect of the device, adds a distribution capacitor for representing the distribution effect of the device into an extrinsic parameter part of an InP HEMT small-signal equivalent circuit model, and adopts a parameter extraction method for extracting parasitic inductance first and then parasitic capacitance in order to eliminate errors introduced by the parasitic inductance in the process of determining the distribution capacitor parameter. And the parasitic inductance is de-embedded in the process of determining the value of the parasitic inductance, so that errors caused by the existence of the parasitic inductance when the parasitic capacitance is extracted are eliminated, the problem of inaccurate high-frequency fitting precision in the prior art is solved, and the fitting precision of an InP HEMT small-signal equivalent circuit model is improved.
Embodiments of the present invention also provide an electronic device, as shown in fig. 12, comprising at least one processor 1201; and a memory 1202 communicatively coupled to the at least one processor 1201; the memory 1202 stores instructions executable by the at least one processor 1201, and the instructions are executed by the at least one processor 1201, so that the at least one processor 1201 can execute the parameter extraction method of the InP HEMT small-signal equivalent circuit model.
Where the memory 1202 and the processor 1201 are connected by a bus, the bus may comprise any number of interconnected buses and bridges, the buses connecting the various circuits of the one or more processors 1201 and the memory 1202. The bus may also connect various other circuits such as peripherals, voltage regulators, and power management circuits, which are well known in the art, and therefore, will not be described any further herein. The bus interface provides an interface between the bus and the transceiver. The transceiver may be one element or may be a plurality of elements, such as a plurality of receivers and transmitters, providing a means for communicating with various other apparatus over a transmission medium. The data processed by the processor 1201 is transmitted over a wireless medium via an antenna, which further receives the data and transmits the data to the processor 1201.
The processor 1201 is responsible for managing the bus and general processing, and may provide various functions including timing, peripheral interfaces, voltage regulation, power management, and other control functions. And memory 1202 may be used to store data used by processor 1201 in performing operations.
The product may perform the method provided by the embodiment of the present application, and have corresponding functional modules and beneficial effects of the performing method, and technical details not described in detail in the embodiment of the present application may be referred to the method provided by the embodiment of the present application.
Embodiments of the present application also provide a computer-readable storage medium storing a computer program. The method for extracting the parameters of the InP HEMT small signal equivalent circuit model is realized when the computer program is executed by a processor.
Those skilled in the art will appreciate that all or part of the steps in implementing the methods of the embodiments described above may be implemented by a program stored in a storage medium, where the program includes several instructions for causing a device (which may be a single-chip microcomputer, a chip or the like) or a processor (processor) to perform all or part of the steps of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
The embodiments described hereinabove are intended to provide those of ordinary skill in the art with a variety of modifications and variations to the embodiments described above without departing from the inventive concepts of the present application, and thus the scope of the invention is not limited by the embodiments described hereinabove, but is to be accorded the broadest scope of the innovative features recited in the claims.

Claims (10)

1. An InP HEMT small signal equivalent circuit model is characterized in that,
the model comprises: the device comprises a grid electrode, a drain electrode, a source electrode, an intrinsic module, a grid electrode parasitic module, a source electrode parasitic module, a drain electrode parasitic module and a grid electrode drain parasitic module; the grid is connected to a grid internal node of the intrinsic module through the grid parasitic module, the drain is connected to a drain internal node of the intrinsic module through the drain parasitic module, and the source is connected to a source internal node of the intrinsic module through the source parasitic module; the first end of the gate-drain parasitic module is connected with the gate parasitic module, and the second end of the gate-drain parasitic module is connected with the drain parasitic module;
the model also comprises a grid distributed capacitance, a drain distributed capacitance and a grid-drain distributed capacitance; the first end of the grid distributed capacitor is grounded, and the second end of the grid distributed capacitor is connected to the joint of the first end of the grid drain parasitic module and the grid parasitic module; the first end of the drain distributed capacitor is grounded, and the second end of the drain distributed capacitor is connected to the connection part of the second end of the gate-drain parasitic module and the drain parasitic module; the first end of the gate-drain distribution capacitor is connected to the junction of the first end of the gate-drain parasitic module and the gate parasitic module, and the second end of the gate-drain distribution capacitor is connected to the junction of the second end of the gate-drain parasitic module and the drain parasitic module.
2. The InP HEMT small-signal equivalent circuit model of claim 1, wherein said gate parasitic modules comprise gate parasitic resistance, gate parasitic inductance, and gate parasitic capacitance; the drain parasitic module comprises a drain parasitic resistor, a drain parasitic inductance and a drain parasitic capacitance; the source parasitic module comprises a source parasitic resistor and a source parasitic inductor; the gate-drain parasitic module comprises a gate-drain parasitic capacitor;
the first end of the gate parasitic inductance and the first end of the gate parasitic capacitance are connected to the first end of the gate parasitic resistance, the second end of the gate parasitic inductance is connected to the gate of the model, the second end of the gate parasitic capacitance is connected to the source parasitic module, and the second end of the gate parasitic resistance is connected to the gate internal node;
the first end of the drain parasitic inductance and the first end of the drain parasitic capacitance are connected to the first end of the drain parasitic resistance, the second end of the drain parasitic inductance is connected to the drain of the model, the second end of the drain parasitic capacitance is connected to the junction of the source parasitic module and the second end of the gate parasitic capacitance, and the second end of the drain parasitic resistance is connected to the drain internal node;
the first end of the source parasitic resistor is connected with the first end of the source parasitic capacitor, the second end of the source parasitic resistor is connected with the source internal node, and the second end of the source parasitic inductor is connected with the source of the model;
the second end of the gate parasitic capacitor is connected to the source parasitic module, specifically, the second end of the gate parasitic capacitor is connected to a connection position of the source parasitic resistor and the source parasitic inductor in the source parasitic module.
3. The InP HEMT small-signal equivalent circuit model according to claim 2, wherein a first end of said gate-drain parasitic module is connected to said gate parasitic module, in particular a first end of said gate-drain parasitic capacitance is connected to a first end of a gate parasitic resistor in said gate parasitic module; the second end of the gate-drain parasitic module is connected with the drain parasitic module, and particularly, the second end of the gate-drain parasitic capacitor is connected with the first end of the drain parasitic resistor in the drain parasitic module.
4. An InP HEMT small-signal equivalent circuit model according to any one of claims 1-3, wherein said eigen-modules comprise: the gate-source intrinsic capacitance between the gate internal node and the drain internal node, the gate-source intrinsic capacitance between the gate internal node and the source internal node, and the gate-source intrinsic resistance connected in series with the gate-source intrinsic capacitance, the drain-source intrinsic resistance between the drain internal node and the source internal node, and the drain-source intrinsic capacitance connected in parallel with the drain-source intrinsic resistance.
5. A method for extracting parameters of an InP HEMT small-signal equivalent circuit model, wherein the InP HEMT small-signal equivalent circuit model is as set forth in any one of claims 1 to 4, comprising:
acquiring a first equivalent circuit model, and determining the value of parasitic inductance of the model according to the impedance parameter of the first equivalent circuit model; the first equivalent circuit model is an equivalent circuit model obtained by performing de-embedding treatment on the resistor in the model; the parasitic inductance comprises a grid parasitic inductance, a source parasitic inductance and a drain parasitic inductance; the resistor comprises a grid parasitic resistor, a source parasitic resistor, a drain parasitic resistor, a grid source intrinsic resistor and a drain source intrinsic resistor;
acquiring a second equivalent circuit model, and determining the values of parasitic capacitance and distributed capacitance of the model according to admittance parameters of the second equivalent circuit model; the second equivalent circuit model is an equivalent circuit model obtained by performing de-embedding treatment on the resistor and the parasitic inductor in the model; the parasitic capacitance comprises a grid parasitic capacitance, a source parasitic capacitance, a drain parasitic capacitance and a grid drain parasitic capacitance; the distributed capacitance comprises a grid distributed capacitance, a drain distributed capacitance and a grid-drain distributed capacitance;
acquiring a third equivalent circuit model, and determining the value of the parasitic resistance of the model according to the impedance parameter of the third equivalent circuit model; the third equivalent circuit model is an equivalent circuit model obtained by performing de-embedding treatment on the capacitance and the parasitic inductance in the model; the capacitance includes the parasitic capacitance, the distributed capacitance, and an intrinsic capacitance; the parasitic resistances include the gate parasitic resistance, the source parasitic resistance, and the drain parasitic resistance;
acquiring a fourth equivalent circuit model, and determining the numerical value of an intrinsic unit of the model according to the admittance parameter of the fourth equivalent circuit model; the fourth equivalent circuit model is an equivalent circuit model of an intrinsic module of the model; the intrinsic unit comprises a gate-drain intrinsic capacitance, a gate-source intrinsic resistance, a drain-source intrinsic resistance and a drain-source intrinsic capacitance.
6. The method for extracting parameters of an InP HEMT small-signal equivalent circuit model according to claim 5, wherein said determining the value of the parasitic inductance of the InP HEMT small-signal equivalent circuit model according to the impedance parameters of the first equivalent circuit model comprises:
obtaining an expression of the product of ω and the impedance parameter of the first equivalent circuit model, the imaginary part of the expression being related to ω 2 And the slope of (a) determines the value of the parasitic inductance.
7. The method for extracting parameters of InP HEMT small-signal equivalent circuit models according to claim 5, wherein said determining values of parasitic capacitance and distributed capacitance of said models according to admittance parameters of said second equivalent circuit models comprises:
determining the value of the total capacitance between the gate and the drain, the value of the total capacitance between the gate and the source, and the value of the total capacitance between the source and the drain according to the admittance parameter and the value of the intrinsic capacitance of the second equivalent circuit model;
determining the values of the parasitic capacitance and the distributed capacitance of the model according to the value of the total capacitance between the gate and the drain, the value of the total capacitance between the gate and the source, and the value of the total capacitance between the source and the drain; wherein the gate parasitic capacitance is equal to the source parasitic capacitance, and the gate distributed capacitance is equal to the drain distributed capacitance; the intrinsic capacitance comprises a gate-drain intrinsic capacitance, a gate-source intrinsic capacitance and a drain-source intrinsic capacitance.
8. The method for extracting parameters of InP HEMT small-signal equivalent circuit model according to claim 5, wherein said determining the value of parasitic resistance of said model according to the impedance parameters of said third equivalent circuit model comprises:
and determining the values of the source parasitic resistance, the drain parasitic resistance and the gate parasitic resistance according to the real part of the impedance parameter of the third equivalent circuit model.
9. An electronic device, comprising:
at least one processor; the method comprises the steps of,
a memory communicatively coupled to the at least one processor; wherein, the liquid crystal display device comprises a liquid crystal display device,
the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of extracting parameters of the InP HEMT small-signal equivalent circuit model according to any one of claims 5 to 8.
10. A computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the method for extracting parameters of the InP HEMT small-signal equivalent circuit model according to any one of claims 5 to 8.
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