CN115327825A

CN115327825A - Display substrate, display panel and display device

Info

Publication number: CN115327825A
Application number: CN202211064876.3A
Authority: CN
Inventors: 张俊伟; 董职福; 王孝林; 付鹏程; 王威杰; 樊琦月
Original assignee: BOE Technology Group Co Ltd; Chongqing BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Chongqing BOE Optoelectronics Technology Co Ltd
Priority date: 2022-08-31
Filing date: 2022-08-31
Publication date: 2022-11-11

Abstract

The embodiment of the application provides a display substrate, a display panel and a display device. The display substrate includes; the array substrate comprises a substrate and a plurality of sub-pixels, wherein the plurality of sub-pixels are arranged on the substrate in an array manner; the pixel electrode is arranged corresponding to the sub-pixel, the signal lines are intersected and arranged in an insulating mode, the signal lines and the auxiliary signal lines are arranged in an overlapping mode, orthographic projections of the auxiliary signal lines on the substrate are at least partially overlapped with orthographic projections of the signal lines on the substrate, and the signal lines and the auxiliary signal lines are in direct contact at the overlapping position; the signal auxiliary line and the pixel electrode are arranged in the same layer. Like this, can continue to transmit the signal through the signal auxiliary line that overlaps setting and direct contact with the signal line, and then make the signal can continue to transmit to reduce the bad emergence of signal conduction because of the foreign matter leads to a certain extent, guarantee display substrate's display effect.

Description

Display substrate, display panel and display device

Technical Field

The application relates to the technical field of display equipment, in particular to a display substrate, a display panel and a display device.

Background

With the continuous development of display devices, the display requirements of people on the display devices are gradually increased. How to ensure the stability of the display performance of the display device becomes an important index for measuring the quality of the display device. Currently, there is a risk of intrusion of foreign substances during a production process of a display substrate retained by a display device. For example, foreign matters introduced in the preparation process of the source-drain metal layer can cause disconnection of signal lines or abnormal signal transmission, which causes poor signal conduction and influences the display effect of the display substrate.

Disclosure of Invention

The embodiment of the application provides a display substrate, a display panel and a display device, and aims to solve the problem that signal transmission abnormality occurs on a signal line caused by foreign matters introduced into the display substrate in the preparation process in the related art.

In order to solve the technical problem, the present application is implemented as follows:

in a first aspect, an embodiment of the present application provides a display substrate, where the display substrate includes;

a substrate;

a plurality of sub-pixels arranged in an array on the substrate;

a pixel electrode disposed corresponding to the sub-pixel,

a plurality of signal lines which are intersected and arranged in an insulating mode, wherein orthographic projections of the signal lines on the substrate are at least partially overlapped with orthographic projections of the signal lines on the substrate, and the signal lines are in direct contact with the signal lines at the overlapped positions;

the signal auxiliary line and the pixel electrode are arranged in the same layer.

Optionally, the signal lines include a plurality of first-type signal lines and a plurality of second-type signal lines, the orthographic projections of the first-type signal lines and the second-type signal lines on the substrate intersect, the signal auxiliary lines include first-type auxiliary lines and/or second-type auxiliary lines, and the orthographic projections of the first-type auxiliary lines on the substrate at least partially overlap with the orthographic projections of the first-type signal lines on the substrate;

the orthographic projection of the second type auxiliary line on the substrate at least partially overlaps with the orthographic projection of the second type signal line on the substrate.

Optionally, the signal lines include a plurality of signal lines of a third type, the signal lines of the third type are aligned with the extending direction of the signal lines of the first type, and the signal auxiliary lines further include auxiliary lines of a third type, and an orthographic projection of the auxiliary lines of the third type on the substrate at least partially overlaps with an orthographic projection of the signal lines of the third type on the substrate.

Optionally, the display substrate includes a gate layer, a source-drain metal layer, and a pixel electrode layer stacked on the substrate; the source-drain metal layer is positioned on one side of the grid layer away from the substrate;

the second-type signal lines are located on the gate electrode layer, the first-type signal lines and the third-type signal lines are located on the source drain metal layer, and the pixel electrodes, the first-type auxiliary lines, the second-type auxiliary lines and the third-type auxiliary lines are located on the pixel electrode layer.

Optionally, the display substrate further includes a common electrode layer; the common electrode layer includes a common electrode, and one of the common electrode or the pixel electrode includes a plurality of slits;

the pixel electrode layer is positioned between the grid layer and the substrate, and the common electrode layer is positioned on one side of the source drain metal layer, which is far away from the substrate;

or the pixel electrode layer is positioned on one side of the source drain metal layer far away from the substrate, and the common electrode layer is positioned between the gate layer and the substrate.

Optionally, a sub-auxiliary line is disposed in the common electrode layer; the orthographic projection of the sub-auxiliary lines on the substrate is at least partially overlapped with the orthographic projection of the signal lines and/or the signal auxiliary lines on the substrate.

Optionally, an orthographic projection of the third type signal line on the substrate and an orthographic projection of the first type signal line on the substrate are not coincident;

the orthographic projection of the auxiliary line of the first type on the substrate and the orthographic projection of the auxiliary line of the third type on the substrate are not coincident.

Optionally, the first type signal lines are data lines, the second type signal lines are gate lines, and the third type signal lines are touch lines.

In a second aspect, an embodiment of the present application provides a display panel, where the display panel includes a display area, a fan-out area located on one side of the display area, and a bonding area located on one side of the fan-out area away from the display area;

the display area comprises the display substrate of any embodiment of the first aspect;

in a case where the display substrate includes an auxiliary signal line at least partially overlapping with an orthographic projection of the signal line on the base, a line width of the signal line is reduced, and a proportion of the fan-out area with respect to the display panel is reduced.

In a third aspect, the present application provides a display device, which includes the display panel of the second aspect.

As can be seen from the foregoing embodiments, in the embodiments of the present application, the display substrate includes the pixel electrodes disposed corresponding to the sub-pixels, the plurality of signal lines intersecting and disposed in an insulating manner, and the plurality of signal auxiliary lines, where an orthographic projection of the signal line on the substrate is at least partially overlapped with an orthographic projection of the signal auxiliary line on the substrate, and at an overlapping position, the signal line is in direct contact with the signal auxiliary line, so that when an open circuit occurs due to generation of a foreign object in a manufacturing process of the signal line, a signal can be continuously transmitted through the signal auxiliary line disposed in an overlapping manner and in direct contact with the signal line, and further the signal can be continuously transmitted, thereby reducing occurrence of signal conduction failure due to the foreign object to a certain extent, and ensuring a display effect of the display substrate.

Drawings

In order to more clearly illustrate the embodiments of the present disclosure or technical solutions in related arts, the drawings used in the description of the embodiments or related arts will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present disclosure, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a schematic flow chart of a process for manufacturing a display substrate;

FIG. 2 is a schematic diagram of a pixel structure of a display substrate;

FIG. 3 isbase:Sub>A schematic cross-sectional view ofbase:Sub>A display substrate taken along A-A in FIG. 2;

FIG. 4 is a schematic diagram of a portion of a display substrate;

fig. 5 is a schematic flow chart illustrating a manufacturing process of a display substrate according to an embodiment of the present disclosure;

FIG. 6-1 is a schematic diagram of a pixel structure of a display substrate according to an embodiment of the present disclosure;

fig. 6-2 is a second schematic view illustrating a pixel structure of a display substrate according to an embodiment of the present disclosure;

fig. 6-3 is a third schematic view illustrating a pixel structure of a display substrate according to an embodiment of the present disclosure;

fig. 6-4 are four schematic diagrams illustrating a pixel structure of a display substrate according to an embodiment of the present disclosure;

6-5 illustrate a fifth pixel structure of a display substrate according to an embodiment of the present disclosure;

6-6 illustrate a sixth embodiment of a pixel structure of a display substrate according to the present disclosure;

fig. 6-7 illustrate a seventh schematic view of a pixel structure of a display substrate according to an embodiment of the present disclosure;

fig. 6-8 illustrate an eighth schematic view of a pixel structure of a display substrate according to an embodiment of the present disclosure;

FIGS. 6-9 illustrate a ninth schematic view of a pixel structure of a display substrate according to an embodiment of the present disclosure;

FIG. 7 is a schematic cross-sectional view of the display substrate of the embodiment of the present application along the direction B-B in FIGS. 6-8;

fig. 8 is a schematic partial structure diagram of another display substrate provided in an embodiment of the present application;

fig. 9 is a schematic view illustrating a partial structure of another display substrate according to an embodiment of the present disclosure;

fig. 10 is a schematic structural diagram of a display panel according to an embodiment of the present application;

fig. 11 is a partial schematic view of a display substrate provided in an embodiment of the present application at step F in fig. 2.

Reference numerals:

1: a display area; 2 a fan-out area; 3: a binding region; 10: a pixel electrode layer; 20: a source drain metal layer; 30: a semiconductor active layer; 40: a gate layer; 50: a common electrode layer; 101: a pixel electrode; 102: a signal line; 103: a signal auxiliary line; 201: a source electrode; 202: drain 1021: a first-type signal line; 1022: a second-type signal line; 1023: a third type signal line; 1031: a first-type auxiliary line; 1032: a second type auxiliary line; 1033; and a third type of auxiliary line.

Detailed Description

Technical solutions in some embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present disclosure, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments provided in the present disclosure are within the scope of protection of the present disclosure.

Unless the context requires otherwise, throughout the description and the claims, the word "comprise" and its other forms, such as "comprises" and "comprising", will be interpreted as open, inclusive meaning that the word "comprise" and "comprises" will be interpreted as meaning "including, but not limited to", in the singular. In the description of the specification, the terms "one embodiment", "some embodiments", "example", "specific example" or "some examples" and the like are intended to indicate that a particular feature, structure, material, or characteristic associated with the embodiment or example is included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms are not necessarily referring to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be included in any suitable manner in any one or more embodiments or examples.

In the following, the terms "first", "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments of the present disclosure, "a plurality" means two or more unless otherwise specified.

In describing some embodiments, the expression "electrically connected" and its derivatives may be used. For example, the term "electrically connected" may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other.

"A and/or B" includes the following three combinations: a alone, B alone, and a combination of A and B.

The use of "configured to" herein means open and inclusive language that does not exclude devices that are suitable or configured to perform additional tasks or steps.

As used herein, "substantially" includes the stated value as well as an average value that is within an acceptable range of deviation from the specified value, as determined by one of ordinary skill in the art in view of the measurement in question and the error associated with the measurement of the specified quantity (i.e., the limitations of the measurement system).

The "same layer" herein refers to a layer structure formed by forming a film layer for forming a specific pattern by the same film forming process and then forming the film layer by a single patterning process using the same mask plate. Depending on the specific pattern, the single patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous, and the specific patterns may be at different heights or have different thicknesses. In contrast, the "different layers" refer to layer structures formed by respectively using corresponding film forming processes to form a specific pattern and then forming a pattern by a patterning process using corresponding masks, and for example, the "two-layer structure different layer arrangement" refers to two layer structures respectively formed in corresponding process steps (film forming process and patterning process).

Example embodiments are described herein with reference to cross-sectional and/or plan views as idealized example figures. In the drawings, the thickness of layers and regions are exaggerated for clarity. Variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.

Before introducing the display substrate provided in the embodiments of the present application, a description is first given of a manufacturing process of a display substrate and technical problems of the display substrate in the related art, specifically as follows:

fig. 1 is a flow chart of a manufacturing process of a display substrate in the related art, and as shown in fig. 1, a second-type signal line 1022, a semiconductor active layer 30, a pixel electrode layer 10, a source-drain metal layer 20, and a common electrode layer 50 are sequentially prepared. Fig. 2 shows a schematic diagram of a pixel structure of a display substrate prepared by the related art, wherein a second-type signal line 1022 is used for transmitting a switching signal of a semiconductor active layer 30 in the display substrate, a pixel electrode layer 10 achieves an optical display purpose by controlling liquid crystal deflection between the pixel electrode layer 10 and a common electrode layer 50, and the pixel electrode layer 10 is not electrically connected with the second-type signal line 1022 and the semiconductor active layer 30. The source-drain metal layer 20 is generally used for transmitting pixel signals and touch signals in the display substrate.

As shown in fig. 2 and 3, the source-drain metal layer 20 for transmitting pixel signals is divided into a source 201 and a drain 202, the source 201 and the drain 202 are both connected to the semiconductor active layer 30, and there is no direct connection between the source 201 and the drain 202. The drain electrode 202 is connected to the pixel electrode layer 10, and a pixel signal transmitted from the outside is transmitted to the drain electrode 202 through the semiconductor active layer 30 by the source electrode 201 and then conducted to the pixel electrode layer 10.

The deposition and etching of the source drain metal layer 20 are carried out after the pixel electrode layer 10 is manufactured by the existing display substrate manufacturing process. As shown in fig. 4, if a foreign substance is introduced during the process of depositing and etching the source-drain metal layer 20, a signal transmitted in the source-drain metal layer 20 is interrupted at a position of the foreign substance, that is, a signal line 102 in the source-drain metal layer 20 is short-circuited, and a related signal cannot be conducted at the source 201 near the foreign substance, thereby causing a defect and affecting the display effect of the display panel.

Based on this, in a first aspect, embodiments of the present application provide a display substrate to solve a problem in the related art that a foreign object introduced during a manufacturing process of the display substrate causes an abnormal signal transmission of a related signal line.

Fig. 5 is a schematic view illustrating a manufacturing process flow of a display substrate according to an embodiment of the present disclosure, and fig. 6 is a schematic view illustrating a pixel structure of a display substrate according to an embodiment of the present disclosure. As shown in fig. 5 and 6, the display substrate base; a plurality of sub-pixels arranged in an array on the substrate; a pixel electrode 101 arranged corresponding to the sub-pixel, a plurality of signal lines 102 arranged in an intersecting and insulating manner, a plurality of signal auxiliary lines 103, wherein the orthographic projection of the signal lines 102 on the substrate is at least partially overlapped with the orthographic projection of the signal auxiliary lines 103 on the substrate, and at the overlapped position, the signal lines 102 and the signal auxiliary lines 103 are in direct contact; the signal auxiliary line 103 is disposed in the same layer as the pixel electrode 101.

The pixel electrode layer 10 achieves optical display by controlling liquid crystal deflection with the common electrode layer 50, and the plurality of signal lines 102 are generally used for transmitting pixel signals, touch signals and other signals in the display substrate. In the process of manufacturing the display substrate, the plurality of signal lines 102 are usually wired after the pixel electrodes 101 are manufactured, and if a foreign object is introduced into the plurality of signal lines 102 during the process of wiring the plurality of signal lines 102, a signal transmitted in the signal lines 102 is interrupted at the position of the foreign object, and a corresponding signal returns to the vicinity of the foreign object and cannot be conducted, so that a defect is generated.

Based on this, in the embodiment of the present application, a plurality of signal auxiliary lines 103 are further provided, so that the orthographic projection of the signal line 102 on the substrate and the orthographic projection of the signal auxiliary line 103 on the substrate at least partially overlap, that is, the signal line 102 may be completely attached to the signal auxiliary line 103, the signal line 102 may be partially attached to the signal auxiliary line 103, the signal auxiliary line 103 may be attached to the signal line 102, or the signal auxiliary line 103 may be partially attached to the signal line 102, which is not limited in the embodiment of the present application. Further, since the signal line 102 and the signal auxiliary line 103 are in direct contact at the overlapping position, the signal line 102 and the auxiliary signal line 102 can collectively function as signal transmission. As shown in fig. 8 or 9, when a foreign object is present during the wiring of the signal line 102, the transmission can be performed through the auxiliary signal line 102, thereby reducing the occurrence of signal conduction failure due to the foreign object to some extent.

As can be seen from the foregoing embodiments, in the embodiments of the present application, since the display substrate includes the pixel electrode 101 disposed corresponding to the sub-pixel, the signal lines 102 intersecting and disposed in an insulating manner, and the signal auxiliary lines 103, the orthographic projection of the signal line 102 on the substrate at least partially overlaps the orthographic projection of the signal auxiliary line 103 on the substrate, and at the overlapping position, the signal line 102 and the signal auxiliary line 103 are in direct contact, when an open circuit occurs due to a foreign object being generated during the preparation process of the signal line 102, a signal can be continuously transmitted through the signal auxiliary line 103 disposed overlapping and in direct contact with the signal line 102, so that the signal can be continuously transmitted, thereby reducing the occurrence of signal conduction failure due to the foreign object to a certain extent, and ensuring the display effect of the display substrate.

It should be noted that, in the embodiment of the present application, the signal line 102 may be a signal line 102 deposited on any film layer on the substrate, such as a gate line deposited on a gate layer 40 on the substrate, or a data line deposited on the source drain metal layer 20, which is not limited in the embodiment of the present application.

In some embodiments, as shown in fig. 6, the signal lines 102 include a plurality of first-type signal lines 1021 and a plurality of second-type signal lines 1022, the first-type signal lines 1021 and the second-type signal lines 1022 intersect in an orthogonal projection of the substrate, the signal auxiliary lines 103 include first-type auxiliary lines 1031 and/or second-type auxiliary lines 1032, and the orthogonal projection of the first-type auxiliary lines 1031 on the substrate at least partially overlaps with the orthogonal projection of the first-type signal lines 1021 on the substrate; the orthographic projection of the auxiliary lines 1032 of the second type on the substrate at least partially overlaps the orthographic projection of the signal lines 1022 of the second type on the substrate.

In the above embodiment, the first auxiliary lines 1031 may be provided on the first-type signal lines 1021, the first auxiliary lines 1031 may not be provided, the second auxiliary lines 1032 may be provided on the second-type signal lines 1022, and the second auxiliary lines 1032 may not be provided. That is, the signal auxiliary line 103 may be provided over one of the first-type signal line 1021 and the second-type signal line 1022, or the signal auxiliary line 103 may be provided over both the first-type signal line 1021 and the second-type signal line 1022. The number and the arrangement position of the auxiliary signal lines 103 are determined according to the manufacturing processes of the first type signal lines 1021 and the second type signal lines 1022, that is, according to the probability of occurrence of a foreign object risk in the manufacturing processes of the first type signal lines 1021 and the second type signal lines 1022, which is not limited in this embodiment of the present application. In this way, since the orthographic projection of the first-type auxiliary lines 1031 on the substrate and the orthographic projection of the first-type signal lines 1021 on the substrate at least partially overlap, and the orthographic projection of the second-type auxiliary lines 1032 on the substrate and the orthographic projection of the second-type signal lines 1022 on the substrate at least partially overlap, when an open circuit occurs due to the generation of a foreign object in the preparation process of the first-type signal lines 1021, the transmission of signals can be continued through the first-type auxiliary lines 1031. In the case where a disconnection occurs due to generation of foreign matter during the preparation of the first-type signal line 1021, the transmission of signals can be continued through the second-type auxiliary line 1032. And further, the risk of the signal transmission of the display substrate being broken is further reduced, and the display effect of the display substrate is further ensured.

Further, as shown in fig. 6 and 7, the signal lines 102 include a plurality of third-type signal lines 1023, the third-type signal lines 1023 are aligned with the extending direction of the first-type signal lines 1021, the signal auxiliary lines 103 further include third-type auxiliary lines 1033, and the orthographic projection of the third-type auxiliary lines 1033 on the substrate at least partially overlaps with the orthographic projection of the third-type signal lines 1023 on the substrate.

Note that the signal transmitted by the third-type signal line 1023 is different from the signal transmitted by the second-type signal line 1022. Similarly, the third-type signal auxiliary line 103 may be disposed on the third-type signal, and when a disconnection occurs due to generation of a foreign object in the preparation process of the third-type signal line 1023, signal transmission may be continued through the third-type auxiliary line 1033, so that completeness of signal transmission of the display substrate is further improved.

In addition, taking the gate layer 40 and the source-drain metal layer 20 in the display substrate as an example, the display substrate includes the gate layer 40, the source-drain metal layer 20 and the pixel electrode layer 10 on the substrate; the source-drain metal layer 20 is positioned on one side of the grid layer 40 away from the substrate; the second-type signal lines 1022 are located in the gate layer 40, the first-type signal lines 1021 and the third-type signal lines 1023 are located in the source-drain metal layer 20, and the pixel electrodes 101, the first-type auxiliary lines 1031, the second-type auxiliary lines 1032 and the third-type auxiliary lines 1033 are all located in the pixel electrode layer 10.

It should be noted that the first auxiliary lines 1031 and the second auxiliary lines 1032 may be disposed on any surface of the source-drain metal layer 20, or the first auxiliary lines 1031 and the second auxiliary lines 1032 may be disposed on both surfaces of the source-drain metal layer 20, which is not limited in this embodiment. The source-drain metal layer 20 may be located between the signal auxiliary transmission layer formed by the first auxiliary line 1031 and the second auxiliary line 1032 and the pixel electrode layer 10, or the signal auxiliary transmission layer formed by the first auxiliary line 1031 and the second auxiliary line 1032 may be located between the source-drain metal layer 20 and the pixel electrode layer 10. In this way, if foreign matter exists in the first-type signal line 1021 in the source-drain metal layer 20 during the manufacturing process, the foreign matter can be transmitted through the first-type signal line 1021, thereby reducing the occurrence of signal conduction failure due to the foreign matter to a certain extent.

Specifically, as shown in fig. 6-1, the first auxiliary line 1031 may be disposed on a surface of the source-drain metal layer 20 away from the substrate, and as shown in fig. 6-2, the first auxiliary line 1031 may be disposed on a surface of the source-drain metal layer 20 close to the substrate. As shown in fig. 6-3, a first-type auxiliary line 1031 may be provided on both surfaces of the source-drain metal layer 20. Alternatively, as shown in fig. 6-4, the first-type auxiliary lines 1031 and the second-type auxiliary lines 1032 may be provided on the surface of the source-drain metal layer 20 away from the substrate. As shown in fig. 6-5, a first-type auxiliary line 1031 and a second-type auxiliary line 1032 may be provided on the surface of the source-drain metal layer 20 near the substrate. As shown in fig. 6 to 6, the first-type auxiliary lines 1031 and the second-type auxiliary lines 1032 may be provided on both surfaces of the source-drain metal layer 20. The specific arrangement positions of the first auxiliary lines 1031 and the second auxiliary lines 1032 are determined according to the manufacturing process of the display substrate, and this is not limited in this embodiment of the application.

Similarly, the auxiliary line 1033 of the third type may be disposed on any surface of the gate layer 40, or the auxiliary lines 1033 of the third type may be disposed on both surfaces of the gate layer 40, which is not limited in this embodiment of the application. The gate layer 40 may be located between the third-type auxiliary line 1033 and the pixel electrode layer 10, or the third-type auxiliary line 1033 may be located between the gate layer 40 and the pixel electrode layer 10. In this way, if foreign matter exists in the third type auxiliary line 1033 in the gate electrode layer 40 during the manufacturing process, the foreign matter can be transmitted through the third type auxiliary line 1033, thereby reducing the occurrence of signal conduction failure due to the foreign matter to some extent. It should be further noted that, in the embodiment of the present application, in order to reduce the process flow of manufacturing the display substrate, the signal auxiliary line 103 is disposed on only one surface of the gate layer or only one surface of the source-drain metal layer 20. Specifically, as shown in fig. 6 to 7, the auxiliary line 1033 of the third type may be disposed on a surface of the gate layer 40 away from the substrate, as shown in fig. 6 to 8, the auxiliary line 1033 of the third type may be disposed on a surface of the gate layer 40 close to the substrate, as shown in fig. 6 to 9, and the auxiliary line 1033 of the third type may be disposed on both surfaces of the gate layer 40.

Further, in the embodiment of the present application, the first type signal lines 1021 are data lines, the second type signal lines 1022 are gate lines, and the third type signal lines 1023 are touch lines.

It should be noted that the data lines are used for transmitting the switching signals of the pixel semiconductor active layer 30 in the display panel, and the pixel electrode layer 10 achieves the purpose of optical display by controlling the liquid crystal deflection of the common electrode layer 50. In the embodiment of the present application, the signal transmitted by the data line may be a pixel signal, and the pixel signal transmitted from the outside may be conducted to the pixel electrode layer 10 through the semiconductor active layer 30 via the data line. The signal transmitted by the touch line may be a touch signal, and the touch signal transmitted from the outside may be conducted to the touch region through the semiconductor active layer 30 via the touch line. In this way, since the auxiliary signal lines 103 can be disposed on the first type signal lines 1021, the second type signal lines 1022 and the third type signal lines 1023, the data lines, the gate lines and the touch lines can continue to transmit signals through the auxiliary signal lines 102 when there is a foreign object causing a short circuit.

In the embodiment of the present application, the display substrate further includes a common electrode layer 50; the common electrode layer 50 includes a common electrode, and one of the common electrode or the pixel electrode 101 includes a plurality of slits; the pixel electrode layer 10 is located between the gate layer 40 and the substrate, and the common electrode layer 50 is located on a side of the source drain metal layer 20 away from the substrate; or, the pixel electrode layer 10 is located on the side of the source-drain metal layer 20 away from the substrate, and the common electrode layer 50 is located between the gate layer 40 and the substrate.

In the embodiment, when the pixel electrode layer 10 is located between the gate layer 40 and the substrate, and the common electrode layer 50 is located on a side of the source-drain metal layer 20 away from the substrate, the common electrode layer 50 is located on an upper layer, the common electrode layer 50 is of a full-surface structure and has a slit, and the pixel electrode 101 is located on a lower layer and has no slit, in which the auxiliary signal line 102 is disposed on a side of the signal line 102 close to the substrate.

In the case that the pixel electrode layer 10 is located on the side of the source-drain metal layer 20 away from the substrate, and the common electrode layer 50 is located between the gate layer 40 and the substrate, the common electrode is located on the lower layer, the common electrode layer 50 is of a full-face structure, and the pixel electrode layer 10 is located on the upper layer and has a slit, in this embodiment, the auxiliary signal line 102 is disposed on the side of the signal line 102 away from the substrate. It should be noted that, no matter how the relative positions of the common electrode layer 50 and the pixel electrode layer 10 and the substrate are changed, the signal auxiliary line 103 can be disposed only in the same layer as the pixel electrode layer 10 because the common electrode is entirely planar. In addition, since the slits are designed in accordance with the inclination of the liquid crystal, the slits are always formed in the upper electrode layer regardless of the pixel electrode layer 10 or the common electrode layer 50.

In some embodiments, the sub auxiliary lines are provided in the common electrode layer 10; the orthographic projection of the sub auxiliary lines on the substrate is at least partially overlapped with the orthographic projection of the signal lines and/or the signal auxiliary lines on the substrate. In this way, the sub auxiliary lines of the common electrode layer 50 and the auxiliary line 103 of the limit sign in the pixel electrode layer 10 can transmit signals in common with the related signal line 102, and the stability of signal transmission of the display substrate is further improved.

In a possible implementation manner, in the case that the pixel electrode layer 10 is located between the gate electrode layer 40 and the substrate, and the common electrode layer 50 is located on the side of the source-drain metal layer 20 away from the substrate, the orthographic projection of the signal line 102 on the substrate is located within the orthographic projection of the signal auxiliary line 103 on the substrate, or the orthographic projection of the signal line 102 on the substrate and the orthographic projection of the signal auxiliary line 103 on the substrate overlap. In this embodiment mode, the auxiliary signal line 102 is provided on a side of the signal line 102 away from the substrate. In another possible implementation manner, in the case that the pixel electrode layer 10 is located on the side of the source-drain metal layer 20 away from the substrate, and the common electrode layer 50 is located between the gate layer 40 and the substrate, the orthographic projection of the signal auxiliary line 103 on the substrate is located within the orthographic projection of the signal line 102 on the substrate, or the orthographic projection of the signal auxiliary line 103 on the substrate and the orthographic projection of the signal line 102 on the substrate overlap. In this way, no matter how the relative positions of the common electrode layer 50, the pixel electrode layer 10 and the substrate are changed, the signal auxiliary line 103 can be arranged only in the same layer with the pixel electrode layer 10, and the signal line 102 has one auxiliary signal line 102 in overlapping contact with the signal line 102.

In some embodiments, the first type signal lines 1021 include a first line segment and a second line segment, the first line segment intersecting and insulated from the second type signal lines 1022, wherein a line width of the first line segment is less than or equal to a line width of the second line segment. Therefore, on one hand, the line width of the first-type signal line 1021 can be increased, and the probability of disconnection of the first-type signal line 1021 is reduced, and on the other hand, the line width of the position where the first-type signal line 1021 is overlapped with the second-type signal line 1022 is unchanged, so that the parasitic capacitance can be prevented from being increased, and the stability of signal transmission of the display substrate is improved.

Further, the second-type signal line 1022 includes a first line segment and a second line segment, the first line segment intersects and is insulated from the second-type signal line 1022, wherein a line width of the first line segment is less than or equal to a line width of the second line segment. Therefore, on one hand, the line width of the second-type signal line 1022 can be increased, and the disconnection probability of the second-type signal line 1022 is reduced, and on the other hand, the line width of the overlapping position of the second-type signal line 1022 is unchanged, so that the parasitic capacitance can be prevented from being increased, and the signal transmission stability of the display substrate is improved.

Optionally, the orthographic projection of the third type signal line 1023 on the substrate and the orthographic projection of the first type signal line 1021 on the substrate are not coincident; the orthographic projection of the first-type auxiliary lines 1031 on the substrate and the orthographic projection of the third-type auxiliary lines 1033 on the substrate are not coincident. Therefore, the mutual interference of signal transmission between the third-type signal lines 1023 and the first-type signal lines 1021 can be avoided, and the mutual interference of signal transmission between the first-type auxiliary lines 1031 and the third-type auxiliary lines 1033 can also be avoided, so that the stability of signal transmission of the display substrate is improved.

As can be seen from the foregoing embodiments, in the embodiments of the present application, since the display substrate includes the pixel electrode 101 disposed corresponding to the sub-pixel, the plurality of signal lines 102 disposed in an intersecting and insulating manner, and the plurality of signal auxiliary lines 103, the orthographic projection of the signal line 102 on the substrate at least partially overlaps the orthographic projection of the signal auxiliary line 103 on the substrate, and at the overlapping position, the signal line 102 and the signal auxiliary line 103 are in direct contact, when an open circuit occurs due to a foreign object generated during the preparation process of the signal line 102, a signal can be continuously transmitted through the signal auxiliary line 103 disposed in an overlapping manner and in direct contact with the signal line 102, so that the signal can be continuously transmitted, thereby reducing the occurrence of signal conduction failure due to the foreign object to a certain extent, and ensuring the display effect of the display substrate.

In addition, in the process of preparing a source drain metal layer and a pixel electrode layer which are included in the display substrate, the pixel electrode layer 10 and the source drain metal layer 20 can be deposited on the substrate by obtaining the substrate, photoresist is coated on the surface, far away from the pixel electrode layer 10, of the source drain metal layer 20, the source drain metal layer 20 and the pixel electrode layer 10 coated with the photoresist are subjected to halftone exposure, and the exposed source drain metal layer 20 and the exposed pixel electrode layer 10 are etched to form a full light-transmitting region, a partial light-transmitting region and a non-light-transmitting region.

It should be noted that the photoresist is used for transferring the pattern on the mask plate to the photoresist on the top layer of the wafer surface, and is used for protecting the source drain metal layer 20 and the pixel electrode layer 10 in the subsequent halftone exposure and etching processes. The photoresist may include resins, sensitizers, solvents, additives.

It should be noted that, since the source-drain metal layer 20 and the pixel electrode layer 10 are subjected to halftone exposure, one exposure step is reduced in the manufacturing process of the display substrate, so that the size deviation caused by the two exposure steps in the original process can be avoided. Illustratively, the lamination exposure precision of the source-drain metal layer 20 and the pixel electrode layer 10 is 1.5 microns, the unilateral etching precision of the pixel electrode layer 10 is 0.6 microns, and the unilateral etching precision of the source-drain metal layer 20 is 0.5 microns, so that the relative position precision of the pixel electrode layer 10 can be improved

The micron precision is about 2.3 microns, so that the competitiveness of the display substrate in terms of signal crosstalk is improved.

Further, a fully transparent region may be located between the partially transparent region and the opaque region, and the source/drain metal layer 20 and the pixel electrode layer 10 in the fully transparent region are etched so that light can pass through the region. The semi-transparent region is used for adjusting and etching the source-drain metal layer 20 according to the etching time, and the pixel electrode layer 10 is reserved, so that the light transmittance of the partial transparent region is between the light transmittance of the full transparent region and the light transmittance of the non-transparent region.

In addition, the photoresist in the first region of the source-drain metal layer 20 may be stripped, and the source-drain metal layer 20 and the pixel electrode layer 10 in the first region may be etched to form a fully transmissive region.

It should be noted that, in this step, since only the photoresist in the first region of the source-drain metal layer 20 is stripped, the source-drain metal layer 20 and the pixel electrode layer 10 in the first region are etched, and the source-drain metal layer 20 and the pixel electrode layer 10 in other regions are not affected. And the source-drain metal layer 20 and the pixel electrode layer 10 can be etched at one time to form a full light-transmitting region.

Further, by stripping the photoresist in the second region and a part of the photoresist in the third region of the source drain metal layer 20, and etching the source drain metal layer 20 in the second region, a part of light-transmitting region is formed, and a non-light-transmitting region is formed in the third region.

The process of stripping the photoresist may include two parts, namely, light irradiation and heating, and the fully light-transmitting region, the semi-light-transmitting region and the non-light-transmitting region may cause different degrees of curing of the photoresist when performing exposure. Therefore, after the etching of the full light-transmitting area is completed, the etching of the semi-light-transmitting area can be carried out, so that the two times of etching can not be influenced mutually, the etching precision can be ensured, the formed precision of the full light-transmitting area is higher, and the display effect of the display substrate can be ensured.

As can be seen from the foregoing embodiments, in the embodiments of the present application, a substrate is obtained, a pixel electrode layer 10 and a source-drain metal layer 20 are deposited on the substrate, a photoresist is coated on a surface of the source-drain metal layer 20 away from the pixel electrode layer 10, the source-drain metal layer 20 and the pixel electrode layer 10 coated with the photoresist are subjected to halftone exposure, and the exposed source-drain metal layer 20 and the exposed pixel electrode layer 10 are etched to form a full light transmission region, a partial light transmission region, and a non-light transmission region. Therefore, as the source-drain metal layer 20 and the pixel electrode layer 10 are subjected to halftone exposure, one exposure process is reduced in the preparation process of the display substrate, so that the size deviation caused by the original process in two exposure processes can be avoided, and the relative position precision of the pixel electrode layer 10 is improved, so that the competitiveness of the display substrate in the aspect of signal crosstalk is improved.

In a second aspect, as shown in fig. 10, an embodiment of the present application further provides a display panel, where the display panel includes a display area 1, a fan-out area 2 located on one side of the display area 1, and a bonding area 3 located on one side of the fan-out area 2 away from the display area 1, and the display area 1 includes the display substrate described in any one of the embodiments of the first aspect;

in case the display substrate comprises auxiliary signal lines 102 at least partially overlapping with the orthographic projection of the signal lines 102 on the substrate, the line width of the signal lines 102 is reduced by a first value, wherein the first value is between 0.01 and 0.04 micrometer.

In addition, in the embodiment of the present application, the signal auxiliary line 103 avoids the occurrence of poor signal conduction of the signal line 102 caused by a foreign object, so as to ensure the display effect of the display area 1 of the display panel, and meanwhile, the auxiliary signal line 102 can be used to improve the aperture opening ratio of the display panel and facilitate the narrow frame setting of the display panel.

Specifically, for increasing the aperture ratio of the display panel:

for the display panel, the larger the area of the display region 1, the higher the aperture ratio of the display panel, and the higher the transmittance of the display panel.

In the related art, in order to avoid the signal transmission problem of the signal line 102 being affected by the foreign object, the line width of the signal line 102 is usually increased to reduce the risk of short circuit in the signal transmission, however, the line width of the signal line 102 is increased while the relative area of the display area 1 of the display panel is reduced, which is not favorable for the high aperture ratio design of the display panel.

In view of this, in the embodiment of the present application, as shown in fig. 11, in order to avoid the signal transmission problem caused by the foreign matter in the signal line 102, an auxiliary signal line 102 at least partially overlapping with the orthographic projection of the signal line 102 on the base is provided in the display substrate. Taking the third-type signal line 1023 as an example, on the premise that the third-type auxiliary line 1033 and the pixel electrode 101 are arranged on the same layer, the line width AITO2 of the third-type auxiliary line 1033 and the line width of the third-type signal line 1023 are ASD2. In the case where the thickness BSD2 of the third type signal line 1023 is constant and the resistance of the third type signal line 1023 is constant, that is

Wherein the content of the first and second substances,

to increase the resistance of the signal line 102 before the auxiliary line 1033 of the third kind,

to increase the resistance of the signal line 102 after the auxiliary line 1033 of the third kind. The line width of the auxiliary line 1033 of the third type and the line width of the signal line 1023 of the third type are ASD2, that is, ASD2= AITO2. Thus, can obtain

Wherein, the ASD1 is the line width of the third type signal line 1023 before the third type auxiliary line 1033 is added, ρ sd is the density of the signal line 102, ρ ITO is the density of the auxiliary signal line 102, L1 is the length of the third type signal line 1023, and L2 is the third type auxiliary lineThe length of 1033 and BITO2 is the thickness of the third type auxiliary line 1033. Thus, it is possible to obtain a relational expression between the line widths of the third-type signal lines 1023 before and after the auxiliary signal line 102: ASD2= ASD1 ×

Taking the example that the line width of the third type auxiliary line 1033 is 3 micrometers, the line width of the third type signal line 1023 is 6 micrometers, and the thickness of the auxiliary signal line 102 under the new design is 700 micrometers to 1500 micrometers, the line width of the third type signal line can be reduced by 0.01 micrometers to 0.04 micrometers by the display panel provided by the embodiment of the present application.

It can be seen from the above embodiments that, in the embodiments of the present application, the risk of short circuit occurring during signal transmission may not be reduced by increasing the line width of the signal line 102, and the line width of the signal line 102 is favorably reduced, so that the relative area of the display area 1 of the display panel is reduced, and the high aperture ratio of the display panel is favorably improved.

Narrow frame setting to be convenient for display panel:

in the case where the distance between two adjacent signal lines 102 is not changed, since the line width of the signal line 102 can be reduced in the display substrate provided in the embodiment of the present application, the area occupied by all the signal lines 102 and the signal auxiliary line 103 becomes smaller. Taking HD resolution as an example, the existing signal lines 102 may be 1500 lines, and the space of about 15 microns may be reduced by reducing the line width of the signal lines 102, which achieves the purpose of reducing the lower frame and is beneficial to the narrow frame setting of the display panel.

In addition, if the line width of the signal line 102 is not changed, that is, the line width of the signal line 102 is not reduced, the line resistance of the signal line 102 in the embodiment of the present application is smaller, so that the signal transmission is faster, and thus the high refresh rate of the display panel can be improved, and the power consumption of the display panel is reduced.

In a third aspect, an embodiment of the present application further provides a display device, which includes the display panel described in the second aspect.

The display device may be a mobile display device such as a mobile phone, a tablet computer, a notebook computer, a palm computer, a vehicle-mounted display device, a wearable device, an ultra-mobile personal computer (UMPC), a netbook, or a Personal Digital Assistant (PDA), and the non-mobile display device may be a Personal Computer (PC), a Television (TV), a teller machine, or a self-service machine, and the embodiments of the present application are not limited in particular. The beneficial effects of the display device are consistent with those of the display panel, and the embodiment of the application is not repeated herein.

It should be noted that, in this specification, each embodiment is described in a progressive manner, and each embodiment focuses on differences from other embodiments, and portions that are the same as and similar to each other in each embodiment may be referred to.

While alternative embodiments of the present application have been described, additional variations and modifications of these embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including alternative embodiments and all such alterations and modifications as fall within the true scope of the embodiments of the application.

Finally, it should also be noted that, in this document, relational terms such as first and second, and the like are used solely to distinguish one entity from another entity without necessarily requiring or implying any actual such relationship or order between such entities. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or terminal apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or terminal apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of additional like elements in an article or terminal equipment comprising the element.

The technical solutions provided in the present application are described in detail above, and the principles and embodiments of the present application are described herein by using specific examples, and meanwhile, for a person of ordinary skill in the art, according to the principles and implementation manners of the present application, changes may be made in the specific embodiments and application ranges.

Claims

1. A display substrate, comprising;

a substrate;

a plurality of sub-pixels arranged in an array on the substrate;

a pixel electrode disposed corresponding to the sub-pixel,

a plurality of signal lines which are crossed and arranged in an insulating way,

a plurality of signal auxiliary lines, wherein orthographic projections of the signal auxiliary lines on the substrate are at least partially overlapped with orthographic projections of the signal lines on the substrate, and the signal lines and the signal auxiliary lines are in direct contact at the overlapped positions;

the signal auxiliary line and the pixel electrode are arranged on the same layer.

2. The display substrate of claim 1,

the signal lines include a plurality of first type signal lines and a plurality of second type signal lines,

the first type signal lines and the second type signal lines intersect in the orthographic projection of the substrate, the signal auxiliary lines comprise first type auxiliary lines and/or second type auxiliary lines,

the orthographic projection of the first auxiliary line on the substrate at least partially overlaps with the orthographic projection of the first signal line on the substrate;

3. The display substrate according to claim 2, wherein the signal lines comprise a plurality of signal lines of a third type, the signal lines of the third type being aligned with the extending direction of the signal lines of the first type, and the signal auxiliary lines further comprise auxiliary lines of a third type, and an orthographic projection of the auxiliary lines of the third type on the substrate at least partially overlaps with an orthographic projection of the signal lines of the third type on the substrate.

4. The display substrate according to claim 3, wherein the display substrate comprises a gate layer, a source drain metal layer and a pixel electrode layer which are stacked on the substrate;

the source drain metal layer is positioned on one side of the gate layer away from the substrate;

5. The display substrate according to claim 4, wherein the display substrate further comprises a common electrode layer; the common electrode layer comprises a common electrode, and the common electrode or the pixel electrode comprises a plurality of slits;

the pixel electrode layer is positioned between the grid layer and the substrate, and the public electrode layer is positioned on one side, far away from the substrate, of the source drain metal layer;

6. The display substrate according to claim 5, wherein a sub auxiliary line is provided in the common electrode layer; the orthographic projection of the sub-auxiliary lines on the substrate is at least partially overlapped with the orthographic projection of the signal lines and/or the signal auxiliary lines on the substrate.

7. The display substrate according to claim 3, wherein an orthographic projection of the third type signal line on the substrate and an orthographic projection of the first type signal line on the substrate are not coincident;

8. The display substrate according to claim 2, wherein the first type signal lines are data lines, the second type signal lines are gate lines, and/or the third type signal lines are touch lines.

9. The display panel is characterized by comprising a display area, a fan-out area positioned on one side of the display area, and a binding area positioned on one side, far away from the display area, of the fan-out area;

the display area comprises the display substrate of any one of claims 1-8;

in a case where the display substrate includes an auxiliary signal line at least partially overlapping with an orthographic projection of the signal line on the substrate, a line width of the signal line is reduced by a first value, wherein the first value is between 0.01 and 0.04 micrometers.

10. A display device characterized in that the display panel comprises the display panel according to claim 9.