CN115319637A - Polishing method and chemical mechanical polishing equipment - Google Patents
Polishing method and chemical mechanical polishing equipment Download PDFInfo
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- CN115319637A CN115319637A CN202211263753.2A CN202211263753A CN115319637A CN 115319637 A CN115319637 A CN 115319637A CN 202211263753 A CN202211263753 A CN 202211263753A CN 115319637 A CN115319637 A CN 115319637A
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B37/00—Lapping machines or devices; Accessories
- B24B37/04—Lapping machines or devices; Accessories designed for working plane surfaces
- B24B37/07—Lapping machines or devices; Accessories designed for working plane surfaces characterised by the movement of the work or lapping tool
- B24B37/10—Lapping machines or devices; Accessories designed for working plane surfaces characterised by the movement of the work or lapping tool for single side lapping
- B24B37/105—Lapping machines or devices; Accessories designed for working plane surfaces characterised by the movement of the work or lapping tool for single side lapping the workpieces or work carriers being actively moved by a drive, e.g. in a combined rotary and translatory movement
- B24B37/107—Lapping machines or devices; Accessories designed for working plane surfaces characterised by the movement of the work or lapping tool for single side lapping the workpieces or work carriers being actively moved by a drive, e.g. in a combined rotary and translatory movement in a rotary movement only, about an axis being stationary during lapping
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B37/00—Lapping machines or devices; Accessories
- B24B37/005—Control means for lapping machines or devices
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B49/00—Measuring or gauging equipment for controlling the feed movement of the grinding tool or work; Arrangements of indicating or measuring equipment, e.g. for indicating the start of the grinding operation
- B24B49/02—Measuring or gauging equipment for controlling the feed movement of the grinding tool or work; Arrangements of indicating or measuring equipment, e.g. for indicating the start of the grinding operation according to the instantaneous size and required size of the workpiece acted upon, the measuring or gauging being continuous or intermittent
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/10—Complex mathematical operations
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02013—Grinding, lapping
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02024—Mirror polishing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
Abstract
The invention discloses a polishing method and a chemical mechanical polishing device, wherein the polishing method comprises the following steps: after the wafer is ground, measuring the pre-value morphology of the thickness of the wafer before CMP, and determining the upper limit morphology of the thickness after the damage layer is removed according to the thickness of the damage layer, wherein the upper limit morphology is obtained by subtracting the thickness of the damage layer from the pre-value morphology; if the pre-stored reference thickness falls between the previous value morphology and the upper limit morphology, recalculating a target morphology of the thickness based on a constraint condition for optimizing the flatness and the polishing efficiency, wherein the target morphology is defined between the upper limit morphology and the lower limit thickness, and the lower limit thickness is the thinnest thickness of the wafer required by the manufacturing process; if the reference thickness falls between the upper limit morphology and the lower limit thickness, directly taking the reference thickness as the target morphology; and adjusting the polishing pressure according to the target appearance to perform polishing.
Description
Technical Field
The invention relates to the technical field of semiconductor wafer processing, in particular to a polishing method and chemical mechanical polishing equipment.
Background
Thinning (Grinding) of the back surface of a wafer refers to Grinding a plurality of materials such as a silicon wafer or a compound semiconductor before packaging with high precision to reduce the thickness to an appropriate ultra-thin form. The back thinning of the wafer mainly removes materials of a substrate, and two parts of grinding and Chemical Mechanical Polishing (CMP) are integrated in thinning equipment. After the wafer is ground, CMP is performed to further improve flatness, reduce Total Thickness Variation (TTV), and remove a damaged layer caused by grinding.
Before CMP, a target thickness is set, a target removal amount of each zone is calculated, and then the pressure value of each zone is adjusted according to the target removal amount of each zone. In order to achieve polishing and flattening, the target thickness is set to be a straight line or a plane with the same thickness in each zone, however, the setting of the target thickness value lacks theoretical guidance, if the setting is too large, the damaged layer caused by grinding cannot be completely removed, and if the setting is too small, the CMP time is too long, and the efficiency is affected. Therefore, how to balance the flatness and the polishing efficiency well is an urgent problem to be solved.
Disclosure of Invention
The embodiment of the invention provides a polishing method and chemical mechanical polishing equipment, and aims to at least solve one of technical problems in the prior art.
A first aspect of an embodiment of the present invention provides a polishing method including:
after the wafer is ground, measuring the pre-value morphology of the thickness of the wafer before CMP, and determining the upper limit morphology of the thickness after the damage layer is removed according to the thickness of the damage layer, wherein the upper limit morphology is obtained by subtracting the thickness of the damage layer from the pre-value morphology;
if the pre-stored reference thickness falls between the previous value morphology and the upper limit morphology, recalculating a target morphology of the thickness based on a constraint condition for optimizing the flatness and the polishing efficiency, wherein the target morphology is defined between the upper limit morphology and the lower limit thickness, and the lower limit thickness is the thinnest thickness of the wafer required by the manufacturing process;
if the reference thickness falls between the upper limit morphology and the lower limit thickness, directly taking the reference thickness as the target morphology;
and adjusting the polishing pressure according to the target appearance to perform polishing.
In one embodiment, it is determined whether the reference thickness falls between the pre-value profile and the upper-limit profile in the following manner:
calculating the minimum value of the difference values of the reference thickness and the previous value morphology to obtain the minimum difference;
if the minimum difference is less than the thickness of the damaged layer, determining that the reference thickness falls between a previous value profile and an upper limit profile;
and if the minimum difference is larger than or equal to the thickness of the damaged layer, judging that the reference thickness does not fall between the previous value morphology and the upper limit morphology.
In one embodiment, the constraints that optimize flatness and polishing efficiency include: and calculating a value representing flatness and a value representing polishing efficiency from the target topography, and minimizing a weighted sum or a product of the value representing flatness and the value representing polishing efficiency, or minimizing an exponentially weighted sum or an exponentially multiplied product, or minimizing a function calculation quantity related to the two values.
In one embodiment, the recalculating the target feature for thickness based on the constraints that optimize flatness and polishing efficiency comprises:
according to each subarea on the surface of the wafer, setting the target thickness corresponding to each subarea, calculating the difference value between the target thickness of each subarea and the reference thickness, and obtaining the difference value of each subarea
The difference values of each region are combined into a difference value array
，
Wherein, in the step (A),
is a natural number, and is provided with a plurality of groups,
is the total number of the subareas;
and optimizing the standard deviation and the mean value of the difference value array to obtain the difference value array.
In one embodiment, the constraints include:
wherein, the first and the second end of the pipe are connected with each other,
and
in order to preset the weight value, the weight value is set,
is an array of difference values
The standard deviation of (a) is determined,
is an array of difference values
The average value of (a) of (b),
as a result of the thickness of the damage layer,
the reference thickness is subtracted from the mean of the previous topography for each zone.
In one embodiment, the constraints further include:
；
wherein the content of the first and second substances,
and subtracting the lower limit thickness from the minimum value of the previous value morphology of each area.
In one embodiment, the constraints further include:
；
wherein, the first and the second end of the pipe are connected with each other,
is a preset flatness-related quantity.
In one embodiment, the constraints further include:
。
a second aspect of an embodiment of the present invention provides a chemical mechanical polishing apparatus, including:
a polishing disk covered with a polishing pad for polishing a wafer;
the bearing head is used for holding a wafer and pressing the wafer on the polishing pad;
the measuring module is used for acquiring the shape data of the wafer;
control means for implementing the polishing method as described above.
A third aspect of embodiments of the present invention provides a control apparatus comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, the processor implementing the steps of the polishing method as described above when executing the computer program.
A fourth aspect of embodiments of the present invention provides a computer-readable storage medium storing a computer program which, when executed by a processor, implements the steps of the polishing method as described above.
The embodiment of the invention has the beneficial effects that: by solving the multi-objective optimization problem, the flatness requirement and the polishing efficiency can be considered, the flatness requirement is met, the polishing efficiency is improved, and the polishing time is prevented from being too long due to the large removal amount.
Drawings
The advantages of the invention will become clearer and more readily appreciated from the detailed description given with reference to the following drawings, which are given by way of illustration only and do not limit the scope of protection of the invention, wherein:
fig. 1 is a schematic diagram of a wafer thinning system according to an embodiment of the present invention;
FIG. 2 is a schematic view of a chemical mechanical polishing apparatus according to one embodiment of the present invention;
FIG. 3 is a schematic view of a carrier head according to an embodiment of the invention;
FIG. 4 is a flowchart illustrating steps of a polishing method according to an embodiment of the present invention;
FIG. 5 is a schematic of a situation where the reference thickness falls between the pre-value profile and the upper limit profile;
FIG. 6 is an illustration of another situation where the reference thickness falls between the upper and lower limit thicknesses.
Detailed Description
The technical solution of the present invention will be described in detail with reference to the following embodiments and accompanying drawings. The embodiments described herein are specific embodiments of the present invention for the purpose of illustrating the concepts of the invention; the description is intended to be illustrative and exemplary and should not be taken to limit the scope of the invention. It should be noted that, in the present application, the embodiments and features of the embodiments may be combined with each other without conflict. In addition to the embodiments described herein, those skilled in the art will be able to employ other technical solutions which are obvious based on the disclosure of the claims and the specification thereof, and these technical solutions include technical solutions which make any obvious replacement or modification of the embodiments described herein. It should be understood that, unless otherwise specified, the following description of the embodiments of the present invention is made for the convenience of understanding, and the description is made in a natural state where relevant devices, apparatuses, components, etc. are originally at rest and no external control signals and driving forces are given.
Further, it is also noted that terms used herein such as front, back, up, down, left, right, top, bottom, front, back, horizontal, vertical, and the like, to denote orientation, are used merely for convenience of description to facilitate understanding of relative positions or orientations, and are not intended to limit the orientation of any device or structure.
In order to explain the technical solution of the present invention, the following description is made with reference to the accompanying drawings and examples.
In the present application, chemical Mechanical Polishing (Chemical Mechanical Planarization) is also called Chemical Mechanical Planarization (Chemical Mechanical Planarization), wafer (wafer) is also called wafer, silicon wafer, substrate or substrate (substrate), etc., and the meaning and the actual function are equivalent.
The wafer thinning technology provided by the embodiment of the disclosure is mainly applied to back thinning of a wafer, where the back refers to a side of the wafer where no device is laid, and is generally a substrate, and the substrate material may be silicon, silicon oxide, silicon nitride, silicon carbide, sapphire, and the like.
Fig. 1 illustrates a wafer thinning system according to an embodiment of the present invention, including:
the equipment front end module 1 is used for realizing the in and out of the wafer, and the equipment front end module 1 is arranged at the front end of the wafer thinning system. The equipment front-end module 1 is a transition module for carrying the wafer from the outside to the inside of the equipment machine, and is used for realizing the entrance and exit of the wafer so as to realize the dry entrance and dry exit of the wafer.
And the grinding module 3 is used for grinding the wafer, the grinding comprises rough grinding and fine grinding, the grinding module 3 is arranged at the tail end of the wafer thinning system, the wafer is supported and fixed by using a sucker, and the back of the wafer ground by using a grinding wheel is thinned.
And the polishing module 2 is used for carrying out chemical mechanical polishing on the wafer after the grinding is finished, and also has the function of transmitting the wafer among the three modules (the equipment front-end module 1, the grinding module 3 and the polishing module 2), and the polishing module 2 is arranged between the equipment front-end module 1 and the grinding module 3. As shown in fig. 1, the polishing module 2 includes a chemical mechanical polishing apparatus 4.
As shown in fig. 2, the chemical mechanical polishing apparatus 4 applied to the embodiment of the present invention includes a carrier head 10 for holding and rotating a wafer w, a polishing disk 20 covered with a polishing pad 21, a dresser 30 for dressing the polishing pad 21, a liquid supply portion 40 for supplying a polishing liquid, and a control device.
In the chemical mechanical polishing process, the carrier head 10 presses the wafer w against the polishing pad 21 covered by the surface of the polishing disk 20, and the carrier head 10 performs a rotation motion and a reciprocating motion along the radial direction of the polishing disk 20 so that the surface of the wafer w contacting with the polishing pad 21 is gradually polished away, and simultaneously the polishing disk 20 rotates, and the liquid supply part 40 sprays polishing liquid onto the surface of the polishing pad 21. Under the chemical action of the polishing liquid, the wafer w is rubbed against the polishing pad 21 by the relative movement of the carrier head 10 and the polishing platen 20 to perform polishing. During polishing, the dresser 30 serves to dress and activate the topography of the polishing pad 21. The use of the dresser 30 can remove foreign particles remaining on the surface of the polishing pad 21, such as abrasive particles in the polishing liquid and waste materials detached from the surface of the wafer w, and can also planarize the surface deformation of the polishing pad 21 due to polishing.
Fig. 3 is a schematic structural diagram of a carrier head 10. The carrier head 10 comprises an upper structure 11 and a lower structure 12, the upper structure 11 being connected to a drive shaft (not shown) of the carrier head, the upper structure 11 and the lower structure 12 being connected by a flexible connection. The lower structure 12 includes a balance frame 121, a base 122, an elastic membrane 123, and a retaining ring 124. Both the elastic membrane 123 and the retaining ring 124 are fixed on the lower surface of the base 122, and the annular retaining ring 124 is located outside the elastic membrane 123 and is disposed around the elastic membrane 123. The elastic membrane 123 is used to adsorb and apply a downward pressure to the wafer w, and the elastic membrane 123 may be made of an elastic material, for example, chloroprene or silicone rubber. The retaining ring 124 serves to retain the wafer w under the elastic membrane 123 to prevent the wafer w from slipping out. As shown in fig. 3, the elastic membrane 123 is provided with a plurality of concentric pressure-adjustable chambers inside, and is described by taking 7 pressure-adjustable chambers as an example in fig. 3, which are respectively a 1 st chamber Z1, a 2 nd chamber Z2, a 3 rd chamber Z3, a 4 th chamber Z4, a 5 th chamber Z5, a 6 th chamber Z6 and a 7 th chamber Z7 concentrically arranged in sequence from the outside to the center. The central 7 th chamber Z7 is circular, and the 6 th to 1 st chambers Z6 to Z1 are concentric rings. It is clear that the number of pressure-adjustable chambers shown in fig. 3 is only an example, and that other numbers, such as 2, 3, 4, 5, 6, 8, etc., are possible in practice.
As shown in fig. 3, the carrier head 10 used in this embodiment has 7 pressure-adjustable chambers at the bottom, so that the pressure applied to each zone on the surface of the wafer w can be adjusted by controlling the pressure in each pressure-adjustable chamber. The internal pressures of the 1 st chamber Z1 to the 7 th chamber Z7 are independent and can be respectively changed, and accordingly, different chambers of the carrier head 10 divide the surface of the wafer w into a plurality of corresponding partitions, thereby independently adjusting the polishing pressures of a plurality of concentric annular regions corresponding to the surface of the wafer w. Each chamber can apply different pressures to the corresponding surface regions of the wafer w, and the pressures of the fluids such as pressurized air supplied to the chambers are controlled respectively, so that different pressures can be applied to different regions of the surface of the wafer w.
Based on the above structure, embodiments of the present invention provide a polishing method for achieving optimization of flatness and polishing efficiency.
As shown in fig. 4, the polishing method provided by the embodiment of the invention includes:
s1, after the wafer is ground, measuring the pre-value morphology of the thickness of the wafer before CMP, and determining the upper limit morphology of the thickness after the damaged layer is removed according to the thickness of the damaged layer.
Wherein the upper limit morphology is the previous value morphology minus the thickness of the damage layer. As shown in fig. 5, the front value feature is a thickness feature after grinding and before CMP, and is generally a multi-segment curve, taking a two-dimensional coordinate axis as a reference system. The damaged layer is a layer with microcracks on the surface of the wafer after grinding, which is generated by the grinding stress of the grinding wheel, and needs to be removed in the CMP process, and the thickness of the damaged layer is a fixed value. The upper limit morphology is obtained by parallel downward shifting of the previous value morphology, and the downward shifting amount is equal to the thickness of the damaged layer.
And then, according to the prestored magnitude relation between the reference thickness and each shape, executing different operations to obtain the target shape. The reference thickness may be determined by the final thickness of the last batch of wafer polishing, or may be an empirical value.
Step S2, as shown in fig. 5, if the pre-stored reference thickness falls between the previous value profile and the upper limit profile, recalculating the target profile of the thickness based on the constraint conditions that optimize the flatness and the polishing efficiency.
Wherein the constraint conditions for optimizing the flatness and the polishing efficiency include: and calculating a value representing the flatness and a value representing the polishing efficiency from the target topography to minimize a weighted sum or a product of the value representing the flatness and the value representing the polishing efficiency, or minimize an exponentially weighted sum or an exponentially multiplied product, or minimize a function calculation quantity related to the two values.
It will be appreciated that this is an iterative process, and when the pre-stored reference thickness falls between the previous value profile and the upper limit profile, the first calculated target profile is set to the upper limit profile minimum value or the reference thickness for each zone, specifically which value is smaller and which value is, as shown in fig. 5, and then a numerical value representing the flatness and a numerical value representing the polishing efficiency are calculated. The second calculation gradually adjusts the target feature and then calculates a value representing the flatness and a value representing the polishing efficiency. And the rest can be done in the same way until the optimal solution is found.
The target topography is limited between an upper limit topography and a lower limit thickness, and the lower limit thickness is the thinnest thickness of the wafer required by the manufacturing process. The standard deviation of the reference thickness is zero, in other words, the reference thickness is a straight line or a plane.
And S3, as shown in FIG. 6, if the reference thickness falls between the upper limit profile and the lower limit thickness, directly taking the reference thickness as the target profile.
And S4, adjusting polishing pressure according to the target morphology to perform polishing.
The embodiment of the invention simultaneously meets the requirements of removing the damaged layer and planarization, can give consideration to both flatness and polishing efficiency, not only meets the requirement of flatness, but also improves the polishing efficiency, and avoids too long polishing time caused by large removal amount.
In one embodiment, after step S1, it is determined whether the reference thickness falls between the previous value profile and the upper limit profile in the following manner:
step S11, calculating the minimum value of the difference values of the reference thickness and the previous value feature to obtain the minimum difference, which is the Min TarRA shown in fig. 5 and 6.
Step S12, if the minimum difference Min TarRA is less than the damage layer thickness MinRA, determining that the reference thickness falls between the previous value profile and the upper limit profile, as shown in FIG. 5.
Step S13, if the minimum difference Min TarRA is more than or equal to the damage layer thickness MinRA, judging that the reference thickness does not fall between the previous value morphology and the upper limit morphology, as shown in FIG. 6.
Referring to fig. 5, a specific process of acquiring the target feature in step S2 will be described.
In one embodiment, step S2 comprises:
s21, setting target thicknesses corresponding to the partitions according to the partitions on the surface of the wafer, and calculating the target thicknesses of the partitions
And a reference thickness
To obtain difference values of each region
As shown in fig. 5, the difference values are combined into a difference value array
，
Wherein, in the process,
is a natural number，
Is the total number of the subareas; in the present embodiment, the first and second electrodes are,
，
。
step S22, making the difference array
To obtain the difference value array
. In other words, it is desired that both the standard deviation and the mean value are as small as possible, and a smaller standard deviation means higher flatness and a smaller mean value means smaller average removal amount, i.e., shorter polishing time and higher efficiency.
The embodiment of the invention respectively adjusts the target thickness of each area and balances the difference array
The standard deviation and the mean value of the method are minimum, so that the flatness is highest, the efficiency is highest, and the optimization problem under the constraint condition is solved.
As shown in fig. 5, the target thickness of each region constitutes a target feature, and the target feature obtained by the method is a polyline. Generally, the target features of the polishing device are all straight lines, but the target features obtained by the method are multi-segment lines, so that the requirement of flatness is met, the polishing efficiency is improved, and the problem that the polishing time is too long due to large removal amount is avoided.
In one embodiment, the constraints include:
wherein the content of the first and second substances,
and
in order to preset the weight value, the weight value is set,
is a difference array
The standard deviation of (a) is determined,
is a difference array
The average value of (a) of (b),
as a result of the thickness of the damage layer,
subtracting the reference thickness from the mean value of the previous value morphology of each region
。
In the formula (1), standard deviation
Smaller means higher flatness, mean value
Smaller means smaller average removal amount, shorter polishing time, higher efficiency,
in equation (1), the goal is to array the difference values
Standard deviation of (2)
Sum mean value
Weighted sum of
Minimum, standard deviation
Sum mean value
Respectively set weight values
And
the larger the weight value is, the more important the index is. Setting weight values according to different processes with different degrees of importance on flatness and polishing duration
And
the weight of (c).
In formula (1), when the reference thickness of a certain region
Above the upper limit profile, as shown in figure 5 at zone Z6,
is a positive number, then
. When the reference thickness of a certain region
Is located atBelow the upper limit profile, as shown in figure 5 in zone Z5,
is a negative number, then
。
In one embodiment, the constraints further include:
wherein, the first and the second end of the pipe are connected with each other,
and subtracting the lower limit thickness from the minimum value of the pre-value morphology of each region.
In equation (2), it is defined that the target feature cannot be below the lower limit thickness.
In one embodiment, the constraints further include:
wherein the content of the first and second substances,
is a preset flatness-related quantity.
In the formula (3), the first and second groups,
is composed of
Upper limit of (2) using flatness pairs
And the obtained target morphology can meet the requirement of flatness by limiting.
In one embodiment, the constraint furtherThe method comprises the following steps:
。
in one embodiment, the constraints include:
solving the optimization problem using a method such as the "Lagrange multiplier method" can result in
Then the target thickness can be obtained
Is equal to the reference thickness
Minus
。
An embodiment of the present invention further provides a control device, which includes: a processor, a memory, and a computer program stored in the memory and executable on the processor. The processor, when executing the computer program, performs the method steps as shown in fig. 4. The control device refers to a terminal with data processing capability, and includes but is not limited to a computer, a workstation, a server, and even some Smart phones, palm computers, tablet computers, personal Digital Assistants (PDAs), smart televisions (Smart TVs), and the like with excellent performance. The control device is generally installed with an operating system, including but not limited to: windows operating system, LINUX operating system, android (Android) operating system, symbian operating system, windows mobile operating system, and iOS operating system, among others. Specific examples of control devices are listed above in detail, and those skilled in the art will appreciate that control devices are not limited to the listed examples.
An embodiment of the present invention further provides a computer-readable storage medium, in which a computer program is stored, and the computer program, when executed by a processor, implements the method steps shown in fig. 4. The computer program may be stored in a computer readable storage medium, which when executed by a processor, may implement the steps of the various method embodiments described above. Wherein the computer program comprises computer program code, which may be in the form of source code, object code, an executable file or some intermediate form, etc. The computer-readable medium may include: any entity or device capable of carrying the computer program code, recording medium, usb disk, removable hard disk, magnetic disk, optical disk, computer Memory, read-Only Memory (ROM), random Access Memory (RAM), electrical carrier wave signals, telecommunications signals, software distribution medium, and the like.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The drawings accompanying this specification are for the purpose of illustrating the concepts of the invention and are not necessarily to scale, the drawings being schematic representations of the shapes of the parts and their interrelationships. It will be appreciated that in order to facilitate a clear presentation of the structure of the various elements of an embodiment of the invention, the figures are not drawn to scale and that like reference numerals have been used to indicate like parts in the figures.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an illustrative embodiment," "an example," "a specific example," or "some examples" or the like mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
While embodiments of the present invention have been shown and described, it will be understood by those of ordinary skill in the art that: various changes, modifications, substitutions and alterations can be made to the embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.
Claims (11)
1. A method of polishing, comprising:
after the wafer is ground, measuring the pre-value morphology of the thickness of the wafer before CMP, and determining the upper limit morphology of the thickness after the damage layer is removed according to the thickness of the damage layer, wherein the upper limit morphology is obtained by subtracting the thickness of the damage layer from the pre-value morphology;
if the pre-stored reference thickness falls between the previous value morphology and the upper limit morphology, recalculating a target morphology of the thickness based on a constraint condition for optimizing the flatness and the polishing efficiency, wherein the target morphology is defined between the upper limit morphology and the lower limit thickness, and the lower limit thickness is the thinnest thickness of the wafer required by the manufacturing process;
if the reference thickness falls between the upper limit morphology and the lower limit thickness, directly taking the reference thickness as the target morphology;
and adjusting the polishing pressure according to the target appearance to perform polishing.
2. The polishing method as recited in claim 1, wherein determining whether the reference thickness falls between the pre-value profile and the upper-limit profile is performed in the following manner:
calculating the minimum value of the difference values of the reference thickness and the previous value morphology to obtain the minimum difference;
if the minimum difference is less than the thickness of the damaged layer, determining that the reference thickness falls between a previous value profile and an upper limit profile;
and if the minimum difference is larger than or equal to the thickness of the damaged layer, judging that the reference thickness does not fall between the previous value morphology and the upper limit morphology.
3. The polishing method as set forth in claim 1, wherein the constraint condition for optimizing flatness and polishing efficiency comprises: and calculating a value representing the flatness and a value representing the polishing efficiency from the target topography to minimize a weighted sum or a product of the value representing the flatness and the value representing the polishing efficiency, or minimize an exponentially weighted sum or an exponentially multiplied product, or minimize a function calculation quantity related to the two values.
4. The polishing method of claim 1, wherein said recalculating the target feature for thickness based on constraints that optimize flatness and polishing efficiency comprises:
according to each subarea on the surface of the wafer, setting the target thickness corresponding to each subarea, calculating the difference value between the target thickness of each subarea and the reference thickness, and obtaining the difference value of each subarea
The difference values of each region are combined into a difference value array
，
Wherein, in the step (A),
is a natural number, and is provided with a plurality of groups,
is the total number of the subareas;
and optimizing the standard deviation and the mean value of the difference value array to obtain the difference value array.
5. The polishing method as set forth in claim 4, wherein the constraint condition includes:
wherein the content of the first and second substances,
and
in order to preset the weight value, the weight value is set,
is a difference array
The standard deviation of the (c) is,
is a difference array
The average value of (a) of (b),
as a result of the thickness of the damage layer,
the reference thickness is subtracted from the mean of the previous topography for each zone.
6. The polishing method as recited in claim 5, wherein the constraint further comprises:
；
wherein the content of the first and second substances,
and subtracting the lower limit thickness from the minimum value of the pre-value morphology of each region.
7. The polishing method as recited in claim 6, wherein the constraint further comprises:
；
wherein the content of the first and second substances,
is a preset flatness-related quantity.
8. The polishing method as recited in claim 7, wherein the constraint further comprises:
。
9. a chemical mechanical polishing apparatus, comprising:
a polishing disk covered with a polishing pad for polishing a wafer;
the bearing head is used for holding the wafer and pressing the wafer on the polishing pad;
the measuring module is used for acquiring the shape data of the wafer;
a control device for implementing the polishing method according to any one of claims 1 to 8.
10. A control apparatus comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, the processor implementing the steps of the polishing method according to any one of claims 1 to 7 when executing the computer program.
11. A computer-readable storage medium, characterized in that the computer-readable storage medium stores a computer program which, when being executed by a processor, realizes the steps of the polishing method according to any one of claims 1 to 8.
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| CN117592404A (en) * | 2024-01-18 | 2024-02-23 | 杭州广立微电子股份有限公司 | Wafer polishing simulation method and device with self-adaptive time step and readable medium |
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