CN115312397A - 用于芯片的封装方法 - Google Patents
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Abstract
本发明公开了涉及用于芯片的封装方法,芯片封装制备领域,包括S1在来料晶圆上涂布或粘贴第一有机绝缘层;S2对第一有机绝缘层进行开孔露出来料晶圆;S3切割成单颗芯片;S4单颗芯片粘贴在涂布有临时键合胶的载板上;S5对载板进行塑封,形成塑封层;S6塑封后的载板进行处理露出第一有机绝缘层的开孔;S7重布线层完成线路的导通;S8柱下金属层;S9在金属层上进行植球,获得成品芯片;芯片焊盘对位时,不存在芯片偏移问题,降低了芯片焊盘对位难度;无需在来料晶圆上制作铜柱;相比同样层数RDL的产品,要少一层种子层,芯片与临时键合胶无接触,避免了在去除临时键合胶时,去除不干净而造成残胶的情况。
Description
技术领域
本发明涉及芯片封装制备领域,尤其涉及用于芯片的封装方法。
背景技术
随着半导体技术的发展以及消费电子市场的驱动,封装技术向更轻、更薄、体积更小、电热性能更优良的方向发展。目前摩尔定律逐渐放缓,后摩尔时代到来,先进封装因能同时提高产品功能和降低成本是后摩尔时代的主流发展方向。由于先进封装的竞争愈发激烈,如何在保证质量的前提下进一步降低制造成本已成为产业发展的重要驱动力,因此应运而生了板级封装技术,该封装在单位时间内可大幅度提高生产效率及产能,并能满足整合更多异质芯片以达到封装小型化的需求。
按封装后产品面积与芯片面积相比,可划分为扇入型(Fan-in)和扇出型(Fan-out)两类,当芯片面积不能放下所有输入/输出(I/O)接口时,就需要采用Fan-out封装技术。扇出型技术按照芯片功能面朝向又可分为:芯片面朝下(Face down)、芯片面朝上(Faceup)。
但是,现有技术中,封装工艺均有在芯片焊盘对位时,受到芯片偏移的影响;并且Face up工艺来料晶圆需要制作铜柱;Face down工艺存在的问题是芯片需要与临时键合胶接触,有残胶风险。
发明内容
本发明的目的就在于为了解决上述问题设计了用于芯片的封装方法。
本发明通过以下技术方案来实现上述目的:
用于芯片的封装方法,包括:
S1、在来料晶圆的第一端上涂布或粘贴第一有机绝缘层;
S2、对第一有机绝缘层进行开孔露出来料晶圆;
S3、切割成单颗芯片;
S4、单颗芯片粘贴在涂布有临时键合胶的载板上;
S5、对载板进行塑封,形成塑封层;
S6、塑封后的载板进行处理露出第一有机绝缘层的开孔;
S7、重布线层完成线路的导通;
S8、柱下金属层;
S9、在金属层上进行植球,获得成品芯片。
本发明的有益效果在于:采用本方法制备芯片,进行芯片焊盘对位时,不存在芯片偏移的问题,有效的降低了芯片焊盘对位的难度;且无需在来料晶圆上制作铜柱;相比同样层数RDL的产品,要少一层种子层,亦无需芯片与临时键合胶接触,避免了在去除临时键合胶时,去除不干净而造成残胶的情况。
附图说明
图1是本发明实施例1的来料芯片流程;
图2是本发明实施例2的来料芯片流程;
图3是本发明实施例1的工艺流程;
图4是本发明实施例2的工艺流程;
图5是本发明制备出来的芯片结构;
图6是Face up工艺制备出来的芯片结构;
图7是Face down工艺制备出来的芯片结构。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚,下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述。显然,所描述的实施例是本发明一部分实施例,而不是全部的实施例。通常在此处附图中描述和示出的本发明实施例的组件可以以各种不同的配置来布置和设计。
因此,以下对在附图中提供的本发明的实施例的详细描述并非旨在限制要求保护的本发明的范围,而是仅仅表示本发明的选定实施例。基于本发明中的实施例,本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。
应注意到:相似的标号和字母在下面的附图中表示类似项,因此,一旦某一项在一个附图中被定义,则在随后的附图中不需要对其进行进一步定义和解释。
在本发明的描述中,需要理解的是,术语“上”、“下”、“内”、“外”、“左”、“右”等指示的方位或位置关系为基于附图所示的方位或位置关系,或者是该发明产品使用时惯常摆放的方位或位置关系,或者是本领域技术人员惯常理解的方位或位置关系,仅是为了便于描述本发明和简化描述,而不是指示或暗示所指的设备或元件必须具有特定的方位、以特定的方位构造和操作,因此不能理解为对本发明的限制。
此外,术语“第一”、“第二”等仅用于区分描述,而不能理解为指示或暗示相对重要性。
在本发明的描述中,还需要说明的是,除非另有明确的规定和限定,“设置”、“连接”等术语应做广义理解,例如,“连接”可以是固定连接,也可以是可拆卸连接,或一体地连接;可以是机械连接,也可以是电连接;可以是直接连接,也可以通过中间媒介间接连接,可以是两个元件内部的连通。对于本领域的普通技术人员而言,可以根据具体情况理解上述术语在本发明中的具体含义。
下面结合附图,对本发明的具体实施方式进行详细说明。
实施例1,如图1、图3所示,用于芯片的封装方法,包括:
S1、在来料晶圆的第一端涂布或粘贴第一有机绝缘层;
S2、对第一有机绝缘层进行开孔露出来料晶圆;
S3、在第一有机绝缘层上粘贴第二有机绝缘层,切割形成单颗芯片;
S4、单颗芯片的来料晶圆的第二端与涂布有临时键合胶的载板粘贴;
S5、对载板进行塑封,形成塑封层;
S6、研磨塑封层使载板露出第一有机绝缘层的开孔,并进行清洗;
S7、对清洗后的载板依次进行溅射、涂布PR光刻胶、电镀、去除PR光刻胶和刻蚀,完成重布线层;
S8、依次进行涂布PI胶、溅射、涂布PR光刻胶、电镀、去除PR光刻胶和刻蚀,完成柱下金属层,然后再去除载板并在来料晶圆的第二端粘贴背胶膜;
S9、在金属层上进行植球,获得成品芯片。
实施例2,如图2、图4所示,用于芯片的封装方法,包括:
S1、在来料晶圆的第一端涂布或粘贴第一有机绝缘层;
S2、对第一有机绝缘层进行开孔露出来料晶圆;
S3、切割形成单颗芯片;
S4、单颗芯片的第一有机绝缘层与涂布有临时键合胶的载板粘贴;
S5、对载板进行塑封,形成塑封层;
S6、去除载板露出第一有机绝缘层的开孔,并进行清洗;
S7、对清洗后的载板依次进行涂布PI胶、溅射金属层、涂布PR光刻胶、电镀铜、去除PR光刻胶和刻蚀金属层,完成重布线层;
S8、依次进行涂布PI胶、溅射金属层、涂布PR光刻胶、电镀铜、去除PR光刻胶和刻蚀金属层,完成柱下金属层;
S9、在金属层上进行植球,获得成品芯片。
如图5、图6、图7所示,本实施例1和实施例2制备出来的芯片:
芯片表面有一层同芯片尺寸(长宽)一致的有机绝缘层,且该层绝缘层被EMC(塑封料)4面包覆;
相较于传统的Face up工艺,本方法进行芯片焊盘对位时,不存在芯片偏移的问题,有效的降低了芯片焊盘对位的难度;且无需在来料晶圆上制作铜柱;
相较于传统的Face down工艺,同样层数RDL的产品,本方法要少一层种子层,亦无需芯片与临时键合胶接触,避免了在去除临时键合胶时,去除不干净而造成残胶的情况。
本发明的技术方案不限于上述具体实施例的限制,凡是根据本发明的技术方案做出的技术变形,均落入本发明的保护范围之内。
Claims (7)
1.用于芯片的封装方法,其特征在于,包括:
S1、在来料晶圆的第一端上涂布或粘贴第一有机绝缘层;
S2、对第一有机绝缘层进行开孔露出来料晶圆;
S3、切割成单颗芯片;
S4、单颗芯片粘贴在涂布有临时键合胶的载板上;
S5、对载板进行塑封,形成塑封层;
S6、塑封后的载板进行处理露出第一有机绝缘层的开孔;
S7、重布线层完成线路的导通;
S8、柱下金属层;
S9、在金属层上进行植球,获得成品芯片。
2.根据权利要求1所述的用于芯片的封装方法,其特征在于,在S4中,单颗芯片粘贴在载板上时,粘接方式为第一粘接方式或第二粘接方式,第一粘接方式为单颗芯片的来料晶圆的第二端与载板粘接,且在S3中,先在第一有机绝缘层上粘贴第二有机绝缘层,再切割成单颗芯片,第二粘接方式为单颗芯片的第一有机绝缘层与载板粘接。
3.根据权利要求2所述的用于芯片的封装方法,其特征在于,在S6中,当S4中为第一粘接方式时,研磨塑封层使载板露出第一有机绝缘层的开孔,并进行清洗;当S4中为第二粘接方式时,去除载板并清洗。
4.根据权利要求2所述的用于芯片的封装方法,其特征在于,当S4中为第一粘接方式时,在S8中,柱下金属层后,去除载板并在来料晶圆的第二端粘贴背胶膜。
5.根据权利要求1-4任一项所述的用于芯片的封装方法,其特征在于,在S7中,重布线层依次包括:溅射金属层、涂布PR光刻胶、电镀铜、去除PR光刻胶和刻蚀金属层。
6.根据权利要求5所述的用于芯片的封装方法,其特征在于,在S7中,在溅射金属层之前还包括涂布PI胶。
7.根据权利要求1-4任一项所述的用于芯片的封装方法,其特征在于,在S8中,柱下金属层依次包括涂布PI胶、溅射金属层、涂布PR光刻胶、电镀铜、去除PR光刻胶和刻蚀金属层。
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