CN115297089A - Full-automatic address allocation system and method - Google Patents
Full-automatic address allocation system and method Download PDFInfo
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Abstract
The invention provides a full-automatic address allocation system and a method, comprising the following steps: the programmer sends the comparison number to each decoder when address allocation is carried out; each decoder feeds back a response signal when the comparison number is larger than the random number of the decoder; when the programmer receives the response signal, the programmer reduces the comparison number and sends the reduced comparison number to each decoder after each reduction, when the programmer does not receive the response signal, the programmer increases the comparison number and sends the increased comparison number to each decoder after each increase, and the programmer sends the current comparison number to each decoder until the comparison number cannot be increased or decreased; and when the response signal is received subsequently and the time sequence is wrong, the programmer controls each decoder feeding back the response signal to regenerate random numbers for comparison, and when the time sequence of the response signal is correct, the programmer allocates addresses to the decoders feeding back the response signal until all the decoders finish address allocation. The method has the advantages that full-automatic address allocation can be carried out on all decoders on the DMX signal line, and manual operation is not needed.
Description
Technical Field
The invention relates to the technical field of decoder address allocation, in particular to a full-automatic address allocation system and a full-automatic address allocation method.
Background
The LED (light-emitting diode) dynamic control system is widely applied to decoration of scenes such as stages, streets, bridges, buildings, and the like, most of the LED dynamic control systems adopt a DMX512 (Digital Multiple X512) protocol, one of the key points in the DMX512 protocol is address setting of a decoder, and the address setting method of the decoder in the current market includes a physical setting method, a decoder series connection method, an address line adding method, and a programmer method.
Disclosure of Invention
Aiming at the problems in the prior art, the invention provides a full-automatic address allocation system, which comprises:
the two data dimming protocol signal lines are connected with a plurality of decoders in parallel;
the programmer is connected to the two data dimming protocol signal lines in parallel, is communicated with the decoders through the data dimming protocol signal lines, and is used for sending a preset comparison number to the decoders when address allocation is carried out on any one of the decoders;
each decoder is used for comparing the comparison number with a random number generated by the decoder, and feeding back a response signal to the programmer when the comparison number is larger than the random number;
the programmer is further used for reducing the comparison number and sending the reduced comparison number to each decoder after each reduction when any response signal is received, increasing the comparison number and sending the increased comparison number to each decoder after each increase when the response signal is not received, and sending the current comparison number to each decoder until the comparison number cannot be reduced or increased;
the programmer is further configured to control, when the response signal corresponding to the current comparison number is received and the time sequence of the response signal is incorrect, each of the decoders feeding back the response signal to regenerate the random number to compare the random number with the preset comparison number, and when the response signal corresponding to the current comparison number is received and the time sequence of the response signal is correct, perform address allocation on the decoders feeding back the response signal until all the decoders complete address allocation.
Preferably, the programmer comprises:
a comparison number adjusting module, configured to, when receiving any one of the response signals, reduce the comparison number by a bisection method and send the reduced comparison number to each of the decoders after each reduction, and when not receiving the response signal, increase the comparison number by a bisection method and send the increased comparison number to each of the decoders after each increase until the comparison number cannot be reduced or increased, send the current comparison number to each of the programmers;
the random number checking module is connected with the comparison number adjusting module and used for checking the response signal when receiving the response signal corresponding to the current comparison number and generating a control signal when a checking result shows that the time sequence of the response signal is wrong; and generating an address allocation signal when the verification result indicates that the time sequence of the response signal is correct;
the random number generating module is connected with the random number checking module and used for controlling each decoder which feeds back the response signal to regenerate the random number according to the control signal and comparing the random number with the preset comparison number;
the address storage module is used for sequentially storing a plurality of addresses to be distributed in an address set;
and the address distribution module is respectively connected with the random number verification module and the address storage module and is used for distributing the address which is sequenced last in the address set to the decoder associated with the address distribution signal according to the address distribution signal and deleting the address which is sequenced last in the address set.
Preferably, the programmer comprises:
the data dimming communication circuit is respectively connected with the decoders, the comparison number adjusting module, the random number verifying module and the address distributing module and is used for receiving the response signals sent by the decoders and distributing addresses to the decoders;
and the interface communication circuit is respectively connected with the data dimming communication circuit and the comparison number adjusting module and is used for receiving an externally input address allocation instruction to control the comparison number adjusting module to send the preset comparison number to each decoder.
Preferably, the programmer is connected to an upper computer, and the upper computer outputs the address assignment instruction to the interface communication circuit to control the comparator adjustment module to send the preset comparison number to each decoder.
Preferably, the data dimming communication circuit includes:
a first pin of the data dimming chip is connected with one of the data dimming protocol signal lines, a fourth pin of the data dimming chip is connected with the other data dimming protocol signal line, a second pin of the data dimming chip is connected with a third pin, a fifth pin of the data dimming chip is grounded, and an eighth pin of the data dimming chip is connected with an external power supply;
one end of the first resistor is connected with the sixth pin of the data dimming chip, and the other end of the first resistor is connected with the external power supply;
one end of the second resistor is connected with the sixth pin, and the other end of the second resistor is grounded;
one end of the third resistor is connected with a seventh pin of the data dimming chip, and the other end of the third resistor is connected with the external power supply;
one end of the fourth resistor is connected with one end of the third resistor, and the other end of the fourth resistor is grounded;
one end of the fifth resistor is connected with one end of the second resistor, and the other end of the fifth resistor is connected with one end of the fourth resistor;
the data dimming chip receives the response signals sent by the decoders through the first pin, and sends the comparison number or the address sequenced last to the decoders through the fourth pin.
Preferably, the fourth pin is a data transmission pin, and the first pin is a general input/output pin.
The invention also provides a full-automatic address allocation method, which is applied to the full-automatic address allocation system and comprises the following steps:
step S1, when the programmer distributes addresses to the decoders, a preset comparison number is sent to the decoders;
step S2, each decoder compares the comparison number with a random number generated by the decoder, and judges whether the comparison number is larger than the random number:
if yes, feeding back a response signal to the programmer, and then turning to the step S3;
if not, not replying;
step S3, the programmer judges whether the response signal is received:
if not, increasing the comparison number, sending the increased comparison number to each decoder after each increase, then returning to the step S2, sending the current comparison number to each decoder until the comparison number cannot be increased, and then turning to the step S4;
if so, reducing the comparison number, sending the reduced comparison number to each decoder after each reduction, then returning to the step S2, sending the current comparison number to each decoder until the comparison number cannot be reduced, and then turning to the step S4;
step S4, the programmer determines whether the received time sequence of the response signal corresponding to the current comparison number is correct:
if yes, address allocation is carried out on the decoder which feeds back the response signal, the decoder which has carried out address allocation is configured to quit receiving the comparison number, and then the step S5 is switched to;
if not, controlling each decoder feeding back the response signal to regenerate the random number, and then returning to the step S1;
step S5, the programmer sends a preset maximum value to each of the decoders as the comparison number, and determines whether the corresponding response signal is received:
if yes, returning to the step S1;
if not, all the programmers are represented to finish address allocation, and then the operation is exited.
Preferably, in the step S3, the programmer decreases the comparison number or increases the comparison number by a dichotomy.
The technical scheme has the following advantages or beneficial effects:
1) The full-automatic address allocation system and the method can perform full-automatic address allocation on all decoders on the DMX signal line without manual operation, thereby realizing high-efficiency address coding, saving the hardware cost of a dial switch of a decoder, and avoiding the complicated operation of setting the dial switch of the decoder;
2) The fully automatic address allocation system and the method connect the decoders on the DMX signal line in parallel, and the normal use of other decoders cannot be influenced due to the damage of one decoder.
Drawings
FIG. 1 is a schematic diagram of the system in accordance with the preferred embodiment of the present invention;
FIG. 2 is an electrical schematic diagram of a data dimming communication circuit in accordance with a preferred embodiment of the present invention;
FIG. 3 is a flowchart illustrating the steps of the method according to the preferred embodiment of the present invention.
Detailed Description
The invention is described in detail below with reference to the figures and specific embodiments. The present invention is not limited to the embodiment, and other embodiments may be included in the scope of the present invention as long as the gist of the present invention is satisfied.
In accordance with the above-mentioned problems occurring in the prior art, there is provided a fully automatic address allocation system, as shown in fig. 1, comprising:
two data dimming protocol signal lines 1, wherein a plurality of decoders 2 are connected in parallel on the two data dimming protocol signal lines 1;
the programmer 3 is connected to the two data dimming protocol signal lines 1 in parallel, is communicated with the decoders 2 through the data dimming protocol signal lines 1, and is used for sending a preset comparison number to the decoders 2 when any one of the decoders 2 is subjected to address allocation;
each decoder 2 is used for comparing the comparison number with a random number generated by the decoder, and feeding back a response signal to the programmer 3 when the comparison number is greater than the random number;
the programmer 3 is further configured to, when receiving any one of the response signals, decrease the comparison number and send the decreased comparison number to each of the decoders 2 after each decrease, and when not receiving the response signal, increase the comparison number and send the increased comparison number to each of the decoders 2 after each increase, until the comparison number cannot be decreased or increased, send the current comparison number to each of the decoders 2;
the programmer 3 is further configured to, when receiving a response signal corresponding to the current comparison number and the time sequence of the response signal is incorrect, control each decoder 2 feeding back the response signal to regenerate a random number to compare with the preset comparison number, and when receiving a response signal corresponding to the current comparison number and the time sequence of the response signal is correct, perform address allocation on the decoders 2 feeding back the response signal until all the decoders 2 complete address allocation.
Specifically, in this embodiment, it is considered that the address setting method for the decoder 2 in the current market includes a physical setting method, a decoder serial method, an address line adding method and a programmer method, where the physical setting method uses a dial switch to set the address of the decoder 2, or the decoder 2 uses a nixie tube to display and add keys to set the address, the former needs a 9-bit dial switch to represent 512 addresses, and needs a corresponding table of dial switch codes (2 system) and device addresses (10 system), and the latter uses a nixie tube to visually display the addresses, so as to omit the tedious operations of table lookup, but compared with the former, the latter has higher hardware cost of the decoder 2, and this physical setting method has the obvious disadvantages that an operator needs to set the addresses for the decoders 2 one by one on site, and is inefficient, and the order of the decoders 2 having set the addresses cannot be mistakenly installed, whereas the fully automatic address allocation system in this embodiment can complete the address allocation of all the decoders 2 fully automatically, and does not need human operations, which is more convenient and has a low rate.
Preferably, the decoder tandem method corresponds the addresses and the tandem positions of the decoders 2 one by one, the 1 st decoder 2 cuts off the 1 st data and forwards the rest of other data as it is when receiving the DMX512 data, the method changes the original parallel connection line mode of the decoders 2 as the 1 st decoder 2 does, the method has obvious and fatal disadvantages, firstly, the decoder 2 increases the hardware cost of a DMX signal transmission module, then, the response speed of the decoder 2 is slow, because the signals are transmitted in series, the decoders 2 cannot realize the dynamic effect at the same time, and when one of the decoders 2 is damaged, the latter decoder 2 cannot receive the DMX signal, the full-automatic address allocation system in the embodiment connects the decoders 2 in parallel on the DMX signal line, and the normal use of the other decoders 2 is not influenced by the damage of one of the decoders 2.
Preferably, the method for adding the address lines is to sequentially connect the decoders 2 in series by adding an address line, and similar to the serial connection method of the decoders 2 in the thought, only address allocation and data communication are separately processed, which solves the problem of slow response speed of the decoders 2, but the decoders 2 also newly add the hardware cost of a group of address transceiver circuits, and add an address line to the wiring of the system to increase workload, and at the same time, the problem that when one of the decoders 2 is damaged, the later decoder 2 cannot receive the address signal is not solved, and the fully automatic address allocation system in this embodiment only uses two data dimming protocol signal lines 1, so that the cost is low, and the problem of receiving the address signal does not exist.
Preferably, the programmer method uses the programmer 3 to write the address of the decoder 2, so that the hardware cost of a physical setting method is saved, and the hardware cost of the whole decoding system of a newly-added address line method is also saved, the defect of the method is similar to the physical setting method, an operator needs to write the address of the decoder 2 one by using the programmer 3 and then paste an address label, and during installation, the address labels are found and installed one by one according to the address sequence, if the installation sequence of a certain decoder 2 in the front is wrong, the decoder 2 in the back needs to be installed again, and the full-automatic address allocation system in the embodiment can complete the address allocation of all the decoders 2 fully automatically, does not need manual operation, and is more convenient and has low error rate.
Specifically, in this embodiment, the fully-automatic address allocation system performs fully-automatic address allocation on all the decoders 2 connected in parallel by using the original data dimming protocol signal line 1, which not only realizes efficient address coding, but also saves the hardware cost of the dial switches of the decoders 2, and particularly avoids the tedious operation (searching address tables) of setting the dial switches of the decoders 2, and because the decoders 2 are connected in parallel to the data dimming protocol signal line 1, the use of other decoders 2 cannot be affected by the damage of one decoder 2 no matter the address allocation or the signal control is performed, and when the decoder 2 is installed, the decoder 2 leaves the factory without an address, so that the decoder can be installed at will, and after the installation is completed, an operator can sit in a computer to perform very intuitive address allocation and modification on the decoders 2 on a construction site.
Preferably, the decoder 2 that completed the address assignment will exit the comparison of the comparison numbers.
Specifically, in this embodiment, the programmer 3 may send an address scan instruction to query the decoder 2 corresponding to the address, where the address scan instruction is the start code (= 1) + sub-instruction (01) + address, and for example, the programmer 3 sends 0x010x010x02 to query the decoder 2 with address 2.
Preferably, the programmer 3 may send an address modification instruction to modify the decoder 2 of the corresponding address, the address modification instruction being start code (= 1) + sub-instruction (02) + address, for example, the programmer 3 sends 0x010x020x0203 may modify the decoder 2 of address 2 to address 3.
Preferably, the programmer 3 may transmit an address deletion instruction to delete the address corresponding to the decoder 2, the address deletion instruction being a start code (= 1) + sub-instruction (03) + address, for example, the programmer 3 transmits an address of the decoder 2 with a deletion address of 3 of 0x010x030x 03.
Preferably, the address assignment instruction sent by the programmer 3 is a start code (= 1) + sub-instruction (04); all address allocation instructions are start codes (= 1) + sub-instructions (04) + sub-instructions (01); the extended address assignment instruction is a start code (= 1) + sub-instruction (04) + sub-instruction (02); the starting distribution instruction is a start code (= 1) + sub-instruction (04) + sub-instruction (03), the decoder enters an address distribution mode after receiving the starting address distribution instruction, automatically exits the address distribution mode after 10 minutes, and returns to the DMX normal instruction mode. And when the exit comparison instruction is received, immediately exiting the address allocation mode. The quit comparison instruction is a start code (= 1) + sub-instruction (04), the programmer finds a decoder with the only minimum random number, and after the decoder is allocated with an unallocated address, the quit comparison instruction is sent, and the current decoder does not respond to the comparison instruction of the programmer any more. The address programming instruction is a start code (= 1) + sub-instruction (04) + sub-instruction (05) + address, and the programmer assigns an address to the current decoder according to the address programming instruction. The random number check command is start code (= 1) + sub command (04) + sub command (06) + address, and the decoder random value is determined to be equal to the programmer comparison value, equal to return YES, not equal to return. The random number transmission instruction is a start code (= 1) + subcommand (04) + subcommand (07) + random number, and the programmer transmits a random number of 24 bits as a programmer random number to the decoder by the random number transmission instruction. The random number generating instruction is a start code (= 1) + sub-instruction (04) + sub-instruction (08), after the decoder receives the instruction, a 24-bit random number (0 < random number <0 xFFFFF) is generated, when the random numbers generated by a plurality of decoders are the same, namely the reply received by the programmer is always wrong in time sequence, at the moment, the programmer sends the instruction once again, and the decoder generates the random number once again. And comparing the random number instruction with a start code (= 1) + sub-instruction (04) + sub-instruction (09), comparing the random number of the decoder with the random number of the programmer after the decoder receives the instruction, and returning YES when the random number of the decoder < = the compared number of the programmer, otherwise, not returning information.
Preferably, the maximum value of the comparison number is 0xFFFFF, the minimum value is 0, and the range of the random number is 0 to 0 xffff.
In a preferred embodiment of the present invention, the programmer 3 comprises:
a comparison number adjusting module 31, configured to, when receiving any response signal, reduce the comparison number by a bisection method and send the reduced comparison number to each decoder 2 after each reduction, and, when not receiving a response signal, increase the comparison number by a bisection method and send the increased comparison number to each decoder 2 after each increase, until the comparison number cannot be reduced or increased, send the current comparison number to each decoder;
a random number checking module 32, connected to the comparison number adjusting module 31, for checking the response signal when receiving the response signal corresponding to the current comparison number, and generating a control signal when the checking result indicates that the time sequence of the response signal is incorrect; and generating an address assignment signal when the verification result indicates that the timing sequence of the response signal is correct;
a random number generating module 33 connected to the random number verifying module 32 for controlling each decoder 2 feeding back the response signal according to the control signal to regenerate the random number and compare the random number with the preset comparison number;
an address storage module 34, configured to store a plurality of addresses to be allocated in an address set in sequence;
and the address allocation module 35 is respectively connected with the comparison number adjusting module 31 and the address storage module 34, and is used for allocating the address with the last ordering in the address set to the decoder 2 associated with the address allocation signal according to the address allocation signal and deleting the address with the last ordering in the address set.
In a preferred embodiment of the present invention, the programmer 3 comprises:
the data dimming communication circuit 36 is respectively connected with each decoder 2, the comparison number adjusting module 31, the random number verifying module 32 and the address allocating module 35, and is used for receiving the response signals sent by each decoder 2 and allocating addresses to each decoder 2;
the interface communication circuit 37 is connected to the data dimming communication circuit 36 and the comparison number adjusting module 31, and is configured to receive an address assignment command input from the outside to control the comparison number adjusting module 31 to send a preset comparison number to each decoder 2.
In the preferred embodiment of the present invention, the programmer 3 is connected to an upper computer 4, and the upper computer 4 outputs an address assignment command to the interface communication circuit 37 to control the comparison number adjusting module 31 to send the preset comparison number to each decoder 2.
Specifically, in this embodiment, the data dimming communication circuit 36 is responsible for communicating with the decoder 2, and has a main function of completing address allocation and collection, the interface communication circuit 37 is responsible for communicating with the upper computer 4, and has a main function of uploading collected information to the upper computer 4 and receiving parameters of the upper computer 4 to complete address modification.
Preferably, the upper computer 4 can be used for custom modification of the address of the decoder 2.
In a preferred embodiment of the present invention, as shown in fig. 2, the data dimming communication circuit 36 includes:
a data dimming chip U1, wherein a first pin of the data dimming chip U1 is connected with one of the data dimming protocol signal lines 1, a fourth pin of the data dimming chip U1 is connected with the other data dimming protocol signal line 1, a second pin of the data dimming chip U1 is connected with a third pin, a fifth pin of the data dimming chip U1 is grounded, and an eighth pin of the data dimming chip U1 is connected with an external power supply;
one end of the first resistor R1 is connected with the sixth pin of the data dimming chip U1, and the other end of the first resistor R1 is connected with an external power supply;
one end of the second resistor R2 is connected with the sixth pin, and the other end of the second resistor R2 is grounded;
one end of the third resistor R3 is connected with a seventh pin of the data dimming chip U1, and the other end of the third resistor R3 is connected with an external power supply;
one end of the fourth resistor R4 is connected with one end of the third resistor R3, and the other end of the fourth resistor R4 is grounded;
one end of the fifth resistor R5 is connected with one end of the second resistor R2, and the other end of the fifth resistor R5 is connected with one end of the fourth resistor R4;
the data dimming chip U1 receives the response signal sent by each decoder 2 through the first pin, and sends the comparison number or the last address of the sequence to each decoder 2 through the fourth pin.
Specifically, in this embodiment, the external power supply may be a 5V power supply.
In a preferred embodiment of the present invention, the fourth pin is a data transmission pin, and the first pin is a general purpose input/output pin.
Specifically, in this embodiment, the fourth pin only uses the data transmission function, and the first pin must be used as a general input/output pin and has an interrupt enable function and a timer timing function.
In a preferred embodiment of the present invention, a full-automatic address allocation method is further provided, which is applied to the full-automatic address allocation system, as shown in fig. 3, and includes the following steps:
step S1, when a programmer allocates addresses to decoders, a preset comparison number is sent to the decoders;
s2, each decoder compares the comparison number with a random number generated by the decoder, and judges whether the comparison number is greater than the random number:
if yes, feeding back a response signal to the programmer, and then turning to the step S3;
if not, not replying;
step S3, the programmer judges whether a response signal is received:
if not, increasing the comparison number, sending the increased comparison number to each decoder after each increase, then returning to the step S2, sending the current comparison number to each decoder until the comparison number cannot be increased or decreased, and then turning to the step S4;
if yes, reducing the comparison number, sending the reduced comparison number to each decoder after each reduction, then returning to the step S2, sending the current comparison number to each decoder until the comparison number cannot be increased or decreased, and then turning to the step S4;
step S4, the programmer judges whether the time sequence of the received response signal corresponding to the current comparison number is correct:
if yes, address allocation is carried out on the decoder feeding back the response signal, the decoder with the address allocation is configured to quit receiving comparison numbers, and then the step S5 is turned to;
if not, controlling each decoder for feeding back the response signal to regenerate the random number, and then returning to the step S1;
step S5, the programmer sends a preset maximum value to each decoder as a comparison number and judges whether a corresponding response signal is received:
if yes, returning to the step S1;
if not, all programmers are represented to finish the address allocation, and then the operation is exited.
In the preferred embodiment of the present invention, in step S5, the programmer decreases the comparison number or increases the comparison number by binary.
Specifically, in this embodiment, the maximum value of the comparison number is 0 xfffffff, the minimum value is 0, the preset comparison number is a middle value of a data interval formed by 0 xfffffff and 0, in step S3, in order to receive the response signal, because the comparison number needs to be increased, the middle value of the previous data interval and the middle value of the data interval formed by 0 xfffffff are taken, and so on, until the difference between the maximum value and the minimum value of the formed data interval is less than or equal to one, it is determined that the comparison number cannot be increased or decreased. The comparison number is reduced by analogy, and details are not repeated here.
As a preferred embodiment, a specific process example of the full-automatic address allocation method in the present technical solution is as follows:
step 1: and the programmer sends a 2-division comparison value 0x800000 to be compared with the random number of the decoder, the value range of the random number of the decoder is 0-0 xFFFFF, if the random number of the decoder on the DMX bus is smaller than or equal to the comparison value 0x800000, data YES is replied, and if not, data YES is not replied.
Step 2: if there is no reply, it indicates that the comparison value is small, and the 2-division method increases the comparison value to 0xC00000. If there is a reply, the comparison value is further reduced by 2 minutes to 0x400000.
And 3, step 3: and repeating the step 2 until the size of the comparison value cannot be changed by using a 2-division method, which indicates that the minimum random number is found.
And 4, step 4: and (4) after finding the equipment with the minimum random number, using a random number checking instruction, returning the response data YES by the current decoder, analyzing the time sequence of the returned data, and if the state is in the 3 rd state, enabling the current decoder to regenerate the random number and returning to the step 1. If the state is 2, the current decoder is unique, and the step 5 is entered.
And 5, step 5: an address is assigned to the device using an address assignment instruction.
And 6, step 6: and after the address allocation is finished, the equipment with the allocated address is quitted from the comparison command by using a quit comparison instruction.
And 7, step 7: repeating the above steps, and comparing to find other decoders. Until no device replies by sending 0xFFFFF.
The non-reply means that the decoder does not reply any data on the DMX bus, and the level of the RXD pin is always high in one receiving period of the programmer, and no data reply is received. The above-mentioned reply, that is, reply YES, means that the decoder replies data 0xAA on the DMX bus, the programmer can resolve the signal of RXD pin in one receiving period, if data 0xAA can be resolved, it means that there is reply, otherwise, since multiple decoders reply data on the DMX bus at the same time, and the reply signals are superimposed, timing error will occur on the signal of RXD pin.
While the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the invention.
Claims (8)
1. A fully automatic address assignment system, comprising:
the two data dimming protocol signal lines are connected with a plurality of decoders in parallel;
the programmer is connected to the two data dimming protocol signal lines in parallel, is communicated with the decoders through the data dimming protocol signal lines, and is used for sending a preset comparison number to the decoders when address allocation is carried out on any one of the decoders;
each decoder compares the comparison number with a random number generated by the decoder, and feeds back a response signal to the programmer when the comparison number is greater than the random number;
the programmer is further configured to reduce the comparison number and send the reduced comparison number to each of the decoders after each reduction when receiving any one of the response signals, and increase the comparison number and send the increased comparison number to each of the decoders after each increase when not receiving the response signal, until the comparison number cannot be increased or decreased, send the current comparison number to each of the decoders;
the programmer is further configured to, when the response signal corresponding to the current comparison number is received and the time sequence of the response signal is incorrect, control each of the decoders feeding back the response signal to regenerate the random number to compare the random number with the preset comparison number, and when the response signal corresponding to the current comparison number is received and the time sequence of the response signal is correct, perform address allocation on the decoders feeding back the response signal until all the decoders complete address allocation.
2. The fully automatic address assignment system of claim 1, wherein the programmer comprises:
a comparison number adjusting module, configured to, when receiving any one of the response signals, reduce the comparison number by a binary method and send the reduced comparison number to each of the decoders after each reduction, and when not receiving the response signal, increase the comparison number by a binary method and send the increased comparison number to each of the decoders after each increase until the comparison number cannot be reduced or increased, and send the current comparison number to each of the decoders;
the random number checking module is connected with the comparison number adjusting module and used for checking the response signal when receiving the response signal corresponding to the current comparison number and generating a control signal when a checking result shows that the time sequence of the response signal is wrong; and generating an address assignment signal when the verification result indicates that the time sequence of the response signal is correct;
the random number generating module is connected with the random number checking module and used for controlling each decoder which feeds back the response signal to regenerate the random number according to the control signal and comparing the random number with the preset comparison number;
the address storage module is used for sequentially storing a plurality of addresses to be distributed in an address set;
and the address allocation module is respectively connected with the random number checking module and the address storage module and is used for allocating the address which is sequenced last in the address set to the decoder which is associated with the address allocation signal according to the address allocation signal and deleting the address which is sequenced last in the address set.
3. The fully automatic address assignment system of claim 2, wherein the programmer comprises:
the data dimming communication circuit is respectively connected with the decoders, the comparison number adjusting module, the random number verifying module and the address distributing module and is used for receiving the response signals sent by the decoders and distributing addresses to the decoders;
the interface communication circuit is respectively connected with the data dimming communication circuit and the comparison number adjusting module and is used for receiving an address allocation instruction input from the outside to control the comparison number adjusting module to send the preset comparison number to each decoder.
4. The system according to claim 3, wherein the programmer is connected to an upper computer, and the upper computer outputs the address assignment command to the interface communication circuit to control the comparison number adjusting module to send the preset comparison number to each of the decoders.
5. The fully automatic address assignment system of claim 4, wherein the data dimming communication circuit comprises:
a first pin of the data dimming chip is connected with one of the data dimming protocol signal lines, a fourth pin of the data dimming chip is connected with the other data dimming protocol signal line, a second pin of the data dimming chip is connected with a third pin, a fifth pin of the data dimming chip is grounded, and an eighth pin of the data dimming chip is connected with an external power supply;
one end of the first resistor is connected with the sixth pin of the data dimming chip, and the other end of the first resistor is connected with the external power supply;
one end of the second resistor is connected with the sixth pin, and the other end of the second resistor is grounded;
one end of the third resistor is connected with the seventh pin of the data dimming chip, and the other end of the third resistor is connected with the external power supply;
one end of the fourth resistor is connected with one end of the third resistor, and the other end of the fourth resistor is grounded;
one end of the fifth resistor is connected with one end of the second resistor, and the other end of the fifth resistor is connected with one end of the fourth resistor;
the data dimming chip receives the response signals sent by the decoders through the first pin, and sends the comparison number or the address sequenced last to the decoders through the fourth pin.
6. The system according to claim 5, wherein the fourth pin is a data-sending pin and the first pin is a general-purpose input/output pin.
7. A fully automatic address allocation method applied to the fully automatic address allocation system according to any one of claims 1 to 6, comprising the steps of:
step S1, when the programmer carries out address allocation on each decoder, a preset comparison number is sent to each decoder;
step S2, each decoder compares the comparison number with a random number generated by the decoder, and judges whether the comparison number is larger than the random number:
if yes, feeding back a response signal to the programmer, and then turning to step S3;
if not, not replying;
step S3, the programmer judges whether the response signal is received:
if not, increasing the comparison number, sending the increased comparison number to each decoder after each increase, then returning to the step S2, sending the current comparison number to each decoder until the comparison number cannot be increased or decreased, and then turning to the step S4;
if yes, reducing the comparison number, sending the reduced comparison number to each decoder after each reduction, then returning to the step S2, sending the current comparison number to each decoder until the comparison number cannot be increased or decreased, and then turning to the step S4;
step S4, the programmer determines whether the received time sequence of the response signal corresponding to the current comparison number is correct:
if yes, performing address allocation on the decoder feeding back the response signal, configuring the decoder having performed address allocation to quit receiving the comparison number, and then turning to step S5;
if not, controlling each decoder feeding back the response signal to regenerate the random number, and then returning to the step S1;
step S5, the programmer sends a preset maximum value to each of the decoders as the comparison number, and determines whether the corresponding response signal is received:
if yes, returning to the step S1;
if not, all the programmers are represented to finish address allocation, and then the operation is exited.
8. The method according to claim 7, wherein in step S3, the programmer decreases the number of comparisons or increases the number of comparisons by a binary method.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100231262A1 (en) * | 2009-03-10 | 2010-09-16 | Freescale Semiconductor, Inc. | Address decoder and method for setting an address |
| CN109041349A (en) * | 2018-09-03 | 2018-12-18 | 深圳市汇德科技有限公司 | It is a kind of that address device and system are write based on LED decoding circuit automatically |
| CN110072322A (en) * | 2019-04-29 | 2019-07-30 | 广州市浩洋电子股份有限公司 | A kind of method of the quick address setting lamps and lanterns DMX |
| CN111147619A (en) * | 2019-12-20 | 2020-05-12 | 海丰通航科技有限公司 | Method and system for realizing automatic address allocation of RS485 slave equipment locally |
-
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100231262A1 (en) * | 2009-03-10 | 2010-09-16 | Freescale Semiconductor, Inc. | Address decoder and method for setting an address |
| CN109041349A (en) * | 2018-09-03 | 2018-12-18 | 深圳市汇德科技有限公司 | It is a kind of that address device and system are write based on LED decoding circuit automatically |
| CN110072322A (en) * | 2019-04-29 | 2019-07-30 | 广州市浩洋电子股份有限公司 | A kind of method of the quick address setting lamps and lanterns DMX |
| CN111147619A (en) * | 2019-12-20 | 2020-05-12 | 海丰通航科技有限公司 | Method and system for realizing automatic address allocation of RS485 slave equipment locally |
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