CN102799547B - DMX (digital dimmer protocol) 512-based chip addressing system and addressing mode thereof - Google Patents
DMX (digital dimmer protocol) 512-based chip addressing system and addressing mode thereof Download PDFInfo
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- CN102799547B CN102799547B CN201210233009.8A CN201210233009A CN102799547B CN 102799547 B CN102799547 B CN 102799547B CN 201210233009 A CN201210233009 A CN 201210233009A CN 102799547 B CN102799547 B CN 102799547B
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Abstract
The invention discloses a DMX (digital dimmer protocol) 512-based chip addressing system and an addressing mode thereof. The chip addressing system comprises a controller and a plurality of chips to be addressed, wherein the controller is provided with a control end, a detection end and a data output end; each chip is provided with a data end, an input end and an output end; the plurality of chips are sequentially connected with one another in series and then connected between the control end and the detection end of the controller, and the data ends of the plurality of chips are respectively connected with the data output end of the controller; and the controller is used for sending address data to the chips through the data output end in sequence, and after the chips receive an addresses, the address is burn in an EEPROM (Electrically Erasable Programmable Read-Only Memory). According to the invention, the address is set only once directly through the controller during the initial use of the system and does not need to be set during subsequent use, and the manual address setting for every node is not required either, so that the workload for system installation is reduced, the possibility of errors caused by dynamic addressing is avoided, and the convenience in the use of the system is greatly improved.
Description
Technical field
The present invention relates to chip addressing field, particularly relate to a kind of chip addressing system based on DMX512 agreement and addressing mode thereof.
Background technology
DMX512 agreement is at first by theater technology association of the USITT(U.S.) propose, as light modulation and light control console data transmission standard, the international agreement of the universal signal control of light industry digitizer, DMX512 agreement is simple and reliable with it, dirigibility is used widely in stage, theater, studio lights control field, and has more and more been applied in the control system of multichannel LED landscape lamp now.
The prerequisite of DMX512 application is to each controlled device allocated physical address intrasystem, the classic method arranging equipment physical address is configuration address toggle switch or provide special and supportingly write location device on each device, when control channel quantity is various, the first method arranging physical address needs the careful layout of in-site installation personnel, dials the physical address establishing large number quipments passage, leakage easily occurs and the situation such as to dial the wrong number; Another kind method is by writing location device directly by the physical address of device channels write controlled device, although eliminate the loaded down with trivial details of manual dial-up, the ease for use directly perceived arranging address is not good enough, and once on-the-spot generation device damage, effort during upkeep cost, affects Consumer's Experience; A kind of method is also had to increase a serial connection signal wire, adopt the mode of dynamic addressing, all to re-address when system electrification each time, but once certain node in system damages the addressing action that will affect this, the mistake of system likely occurrence of large-area.
Summary of the invention
For to solve in above-mentioned addressing technology or manual setting is easily made mistakes or not good enough or adopt dynamic addressing node to damage the problem that just may cause system large area mistake by writing location device ease for use, the invention provides a kind of chip addressing system based on DMX512 agreement and addressing mode thereof, improve the convenience that system uses.
For solving the problems of the technologies described above, the technical scheme that the present invention adopts is: provide a kind of chip addressing system based on DMX512 agreement, comprise controller and multiple chip to be addressed; Described controller has control end, test side and data output end; Described chip has data terminal, input end and output terminal; Be connected between the control end of controller and test side after described multiple chip is connected in series successively, and the data terminal of described multiple chip also distinguishes the data output end of connection control device; Described controller is used for sending address date to described chip successively by described data output end, and address is burned onto in EEPROM by described chip after receiving address.
Wherein, connected by handshaking line between described chip, the input end of the first chips is connected by handshaking line with the control end of controller, the output terminal of last chips is connected by handshaking line with the test side of controller, and whether the chip controls that the level of described handshaking line is connected with this handshaking line by controller or output terminal can receive with the chip that indicative input end is connected with this handshaking line the address date that controller sends.
Wherein, described chip also comprises the ADD signal end being used to indicate and whether receiving address, and in chip, during zero-address, described ADD signal end is low level, and after chip receives address, ADD signal end is set to high level.
For solving the problems of the technologies described above, another technical solution used in the present invention is: provide a kind of addressing mode based on said chip addressing system, comprise step:
Choose chip successively, by the data output end of controller, address is sent to corresponding chip until controller test side detects that all chips receive address all;
The address received is burnt in the EEPROM of each chip by each chip.
Wherein, describedly choose chip successively and by the data output end of controller, address sent to corresponding chip until controller test side detects that the step that all chips have received address all is specially:
The handshaking line of connection control device control end and the first chips input end is set to high level makes the first chips selected, controller data output terminal sends address, first chips receives address set ADD signal and draws high output terminal level and makes the second chips selected, controller data output terminal sends the address of the second chips, set ADD signal after second chips receives address is also drawn high output terminal level and is made the 3rd chips selected, by that analogy until last chips receives address post-tensioning high output terminal level, controller test side detects that connected handshaking line is that high level stops sending address date.
Wherein, the concrete steps of the address of described chip reception controller output are:
Detect and determine whether address reset signal by the address date that controller sends, if so, then output terminal handshaking line is set to low level, and remove address in chip, reset ADD signal; If judge, address date is not address reset signal, then judge whether input end handshaking line is high level further, if not, then return detection control device and whether send address date; If input end handshaking line is high level, then judges whether ADD signal is low further, if not, then return detection control device and whether send address date; If ADD signal is low level, then receiver address, set ADD signal, is set to high level by output terminal handshaking line.
Wherein, describedly choose chip successively and by the data output end of controller, address sent to corresponding chip until controller test side detects that all chips have received the step of address repeatedly all.
Wherein, this multiple step multiplicity described is three times.
The invention has the beneficial effects as follows: in addressing system of the present invention, after controller and chip are connected, directly successively chip is carried out to the Lookup protocol of address by the mode of the controller transmission address frame sending data-signal, extra setting can not be needed to write location device, to address data recording successfully in EEPROM, as the work address of chip, even if still can preserve after power-off, namely only need to arrange primary address when system uses at first, no longer need to reset in follow-up use, do not need manually to arrange in turn each node yet, substantially increase the convenience that system uses, enhance Consumer's Experience.Compared with traditional approach, greatly reduce workload when system is installed, avoid the wrong possibility all needing this process of re-mapping to bring when dynamic addressing powers at every turn, possess good using value.
Accompanying drawing explanation
Fig. 1 is the structural representation of the chip addressing system that the present invention is based on DMX512 agreement;
Fig. 2 is the sequential chart of signal in the chip addressing system that the present invention is based on DMX512 agreement;
Fig. 3 is the process flow diagram of addressing mode chips receiver address of the present invention;
Fig. 4 is chip status transition diagram of the present invention.
Embodiment
By describing technology contents of the present invention, structural attitude in detail, realized object and effect, accompanying drawing is coordinated to be explained in detail below in conjunction with embodiment.
Refer to Fig. 1, the system architecture of present embodiment comprises controller and multiple chip to be addressed; Controller has control end A, test side B and data output end D+/D-; The input end of chip U1 is by handshaking line 1 connection control device control end A, the output terminal of chip U1 connects the input end of chip U2 by handshaking line 2, the output terminal of chip U2 connects the input end of next chip by handshaking line 3, be connected in series successively between chip, the output terminal of last chips UN is by handshaking line N+1 connection control device test side B.Each chip is also connected to the data output end D+/D-of controller respectively in order to receiver address data and other data-signals.Handshaking line 1 to handshaking line N is similar to chip selection signal, is indicated which chip is selected addresses by the height of level, and namely controller sends address date by data output end D+/D-to it.And in order to indicate chip whether to receive address, each chip also comprises the ADD signal end being used to indicate and whether receiving address, in chip, during zero-address, described ADD signal end is low level, and after chip receives address, ADD signal end is set to high level; If chip needs re-mapping, also ADD signal end can be set to low level (reset) can receiver address to indicate.
Particularly, when system starts, first all chips are powered on, then power on to controller.When controller is ready for sending address, controller control end A is set to high level, then handshaking line 1 is high level, represent the first chips U1 and currently choose chip, now handshaking line 2 is low level, sends address with Time Controller, then the first chips U1 receiver address, and address is recorded.And other chip is low due to the handshaking line signal be connected with respective input end, do not receive address now.After the first chips U1 has addressed, the handshaking line 2 connected by its output terminal has drawn as high level, and set ADD signal (ADD signal end is set to high level), represent and accept address, no longer accept subsequent address.The handshaking line 2 be connected with the second chips U2 input end is high level, represent that the second chips U2 is selected, this Time Controller sends the address of the second chips U2, then the second chips U2 receiver address record, draw high handshaking line 3 level makes the 3rd chips selected simultaneously, by that analogy, until complete all address writes.When last chips UN receives the level of address post-tensioning high output terminal handshaking line N+1, controller test side B detects the change of handshaking line N+1 level, and represent and address successfully, can send data-signal, then controller can start the transmission of data-signal.For each chip, from receiver address data to have addressed and to draw high time interval of output terminal handshaking line certain, therefore only need set the transmission interval time of address in the controller, send continuously, as shown in Figure 2.In the present system, chip addresses successfully, is burnt to address in EEPROM, as the work address of chip, even if still can preserve after power-off, need not again address, the mistake may brought when avoiding dynamic addressing when ensureing lower task.In order to ensure that system uses dirigibility, the present invention is also compatible manually to be addressed single chips, and this directly can be realized by addressing device.
Based on above-mentioned addressing system, the present invention also provides a kind of addressing mode, comprises step:
S10: choose chip successively, sends to corresponding chip until controller test side detects that all chips receive address all by the data output end of controller by address, particularly, in this step, first the handshaking line of connection control device control end output terminal and the first chips input end being set to high level makes the first chips selected, controller data output terminal sends address, first chips receives address set ADD signal and draws high output terminal level and makes the second chips selected, controller data output terminal sends the address of the second chips, set ADD signal after second chips receives address is also drawn high output terminal level and is made the 3rd chips selected, by that analogy until last chips receives address post-tensioning high output terminal level, controller test side detects that connected handshaking line is that high level stops sending address date.
S20: the address received is burnt in the EEPROM of each chip by each chip.
In this addressing mode, chip, from receiver address data to have addressed and to draw high time interval of output terminal handshaking line certain, therefore only need set the transmission interval time of address in the controller, send continuously.Whole addressing process simple and flexible.
Consult Fig. 3, in above-mentioned steps S10, the concrete steps that chip receives the address that controller exports are:
Detect and determine whether address reset signal by the address date that controller sends, if so, then output terminal handshaking line is set to low level, and remove address in chip, reset ADD signal; If judge, address date is not that address reset signal is no, then judge whether input end handshaking line is high level further, if not, then return detection control device and whether send address date; If input end handshaking line is high level, then judges whether ADD signal is low further, if not, then return detection control device and whether send address date; If ADD signal is low level, then receiver address, set ADD signal, is set to high level by output terminal handshaking line.
In this flow process, mention the step of chip being carried out to address reset, after chip carries out address reset, re-mapping can be carried out to chip.Single chips because of its handshaking line level height connected and the State Transferring that carries out according to the difference of Received signal strength thereof as shown in Figure 4, under original state, address is zero (i.e. zero-address in chip), and handshaking line signal is low level; When the handshaking line of input end is high level, when the handshaking line of output terminal is low level, chip can address, writing address, and addressing completes; If receive address reset signal, then remove address and transform back into original state.
Because chip allows address reset to re-start addressing, in a preferred embodiment, adopt the mode addressed for three times, namely step S10 tri-times are repeated, ensure that every chips can effectively address, ensure the correctness of chip addressing, to address successfully again by data recording in EEPROM.
In addressing system of the present invention, after controller and chip are connected, directly successively chip is carried out to the Lookup protocol of address by the mode of the controller transmission address frame sending data-signal, extra setting can not be needed to write location device, to address data recording successfully in EEPROM, as the work address of chip, even if still can preserve after power-off, namely only need to arrange primary address when system uses at first, no longer need to reset in follow-up use, do not need manually to arrange in turn each node yet, substantially increase the convenience that system uses, enhance Consumer's Experience.Compared with traditional approach, greatly reduce workload when system is installed, avoid the wrong possibility all needing this process of re-mapping to bring when dynamic addressing powers at every turn, possess good using value.
The foregoing is only embodiments of the invention; not thereby the scope of the claims of the present invention is limited; every utilize instructions of the present invention and accompanying drawing content to do equivalent structure or equivalent flow process conversion; or be directly or indirectly used in other relevant technical fields, be all in like manner included in scope of patent protection of the present invention.
Claims (5)
1. based on a chip addressing system for DMX512 agreement, it is characterized in that, comprise controller and multiple chip to be addressed; Described controller has control end, test side and data output end; Described chip has data terminal, input end and output terminal;
Be connected between the control end of controller and test side after described multiple chip is connected in series successively, and the data terminal of described multiple chip also distinguishes the data output end of connection control device;
Described controller is used for sending address date to described chip successively by described data output end, and address is burned onto in EEPROM by described chip after receiving address;
Connected by handshaking line between described chip, the input end of the first chips is connected by handshaking line with the control end of controller, the output terminal of last chips is connected by handshaking line with the test side of controller, whether the chip controls that the level of described handshaking line is connected with this handshaking line by controller or output terminal can receive with the chip that indicative input end is connected with this handshaking line the address date that controller sends, the testing process of controller is specially: the address date that controller sends detected, determine whether address reset signal, if, then output terminal handshaking line is set to low level, and remove address in chip, reset ADD signal, if judge, address date is not that address reset signal is no, then judge whether input end handshaking line is high level further, if not, then return detection control device and whether send address date, if input end handshaking line is high level, then judges whether ADD signal is low further, if not, then return detection control device and whether send address date, if ADD signal is low level, then receiver address, set ADD signal, is set to high level by output terminal handshaking line.
2. the chip addressing system based on DMX512 agreement according to claim 1, is characterized in that:
Described chip also comprises the ADD signal end being used to indicate and whether receiving address, and in chip, during zero-address, described ADD signal end is low level, and after chip receives address, ADD signal end is set to high level.
3., based on an addressing mode for chip addressing system described in any one of claim 1-2, it is characterized in that, comprise step:
Choose chip successively, by the data output end of controller, address is sent to corresponding chip until controller test side detects that all chips receive address all, specifically comprise, the handshaking line of connection control device control end and the first chips input end is set to high level makes the first chips selected, controller data output terminal sends address, first chips receives address set ADD signal and draws high output terminal level and makes the second chips selected, controller data output terminal sends the address of the second chips, set ADD signal after second chips receives address is also drawn high output terminal level and is made the 3rd chips selected, by that analogy until last chips receives address post-tensioning high output terminal level, controller test side detects that connected handshaking line is that high level stops sending address date, wherein, the concrete steps that described chip receives the address that controller exports are:
Detect and determine whether address reset signal by the address date that controller sends, if so, then output terminal handshaking line is set to low level, and remove address in chip, reset ADD signal; If judge, address date is not address reset signal, then judge whether input end handshaking line is high level further, if not, then return detection control device and whether send address date; If input end handshaking line is high level, then judges whether ADD signal is low further, if not, then return detection control device and whether send address date; If ADD signal is low level, then receiver address, set ADD signal, is set to high level by output terminal handshaking line;
The address received is burnt in the EEPROM of each chip by each chip.
4. addressing mode according to claim 3, is characterized in that:
Describedly choose chip successively and by the data output end of controller, address sent to corresponding chip until controller test side detects that all chips have received the step of address repeatedly all.
5. addressing mode according to claim 4, is characterized in that:
This multiple step multiplicity described is three times.
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| CN201210233009.8A CN102799547B (en) | 2012-07-06 | 2012-07-06 | DMX (digital dimmer protocol) 512-based chip addressing system and addressing mode thereof |
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| CN201210233009.8A CN102799547B (en) | 2012-07-06 | 2012-07-06 | DMX (digital dimmer protocol) 512-based chip addressing system and addressing mode thereof |
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| CN102799547B true CN102799547B (en) | 2015-06-17 |
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| CN104867298B (en) * | 2014-02-20 | 2018-03-06 | 北京硕人时代科技股份有限公司 | A kind of device and method of address matching |
| CN105282904B (en) * | 2014-06-25 | 2019-05-03 | 欧普照明股份有限公司 | A kind of control system and its control method based on DMX512 agreement |
| CN104833924A (en) * | 2015-04-29 | 2015-08-12 | 深圳市共济科技有限公司 | Serial automatic addressing method and system of lead storage battery internal resistance detection modules |
| CN105392228B (en) * | 2015-10-22 | 2017-12-22 | 四川九洲光电科技股份有限公司 | The automatic write address method of light fixture based on DMX512 agreements |
| CN108513405A (en) * | 2018-04-28 | 2018-09-07 | 周社吉 | A kind of DMX512 decoders and communication system and address distribution method |
| CN111741579B (en) * | 2020-08-26 | 2020-11-10 | 杭州罗莱迪思科技股份有限公司 | Method for recognizing address writing fault during address writing of intelligent lamp based on broadcasting mode |
| CN112654109B (en) * | 2020-12-30 | 2023-02-28 | 深圳市天微电子股份有限公司 | Light-emitting module, display screen and control method for signal transmission among light-emitting chips |
| CN112557882B (en) * | 2021-02-19 | 2021-05-28 | 深圳市明微电子股份有限公司 | Chip initial address self-adaptive detection method, device, equipment and storage medium |
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| CN101742757A (en) * | 2008-11-20 | 2010-06-16 | 广闳科技股份有限公司 | Light-dimmer and addressing method thereof |
| CN201765779U (en) * | 2010-07-19 | 2011-03-16 | 广州中大中鸣科技有限公司 | LED (light emitting diode) luminaire and cascading structure thereof |
| CN102361527A (en) * | 2011-11-10 | 2012-02-22 | 四川九洲光电科技股份有限公司 | Circuit with microprogrammed control unit (MCU) address automatically written according to DMX512 protocol and implementation method for circuit |
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| CN101742757A (en) * | 2008-11-20 | 2010-06-16 | 广闳科技股份有限公司 | Light-dimmer and addressing method thereof |
| CN201765779U (en) * | 2010-07-19 | 2011-03-16 | 广州中大中鸣科技有限公司 | LED (light emitting diode) luminaire and cascading structure thereof |
| CN102361527A (en) * | 2011-11-10 | 2012-02-22 | 四川九洲光电科技股份有限公司 | Circuit with microprogrammed control unit (MCU) address automatically written according to DMX512 protocol and implementation method for circuit |
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