CN115295534A

CN115295534A - Flip chip and alignment method

Info

Publication number: CN115295534A
Application number: CN202211221749.XA
Authority: CN
Inventors: 不公告发明人
Original assignee: Origin Quantum Computing Technology Co Ltd
Current assignee: Origin Quantum Computing Technology Co Ltd
Priority date: 2022-10-08
Filing date: 2022-10-08
Publication date: 2022-11-04
Anticipated expiration: 2042-10-08
Also published as: CN115295534B

Abstract

The application discloses a flip chip and an alignment method, and belongs to the field of quantum chip manufacturing. The flip chip includes opposing first and second chips. Wherein the first chip is provided with a first marking means and the second chip has a transparent substrate and a film layer formed on the substrate. The film layer has a through opening facing the first marker feature. The flip chip can conveniently execute the alignment operation in the manufacturing process, thereby obtaining higher alignment quality and further being beneficial to improving the yield of the flip chip.

Description

Flip chip and alignment method

Technical Field

The application belongs to the field of quantum chip preparation, and particularly relates to a flip chip and an alignment method.

Background

As the number of quantum bits in a designed quantum chip is increased, the content (various lines, elements, etc.) etched on the quantum chip is increased. Therefore, the design of a single chip has been difficult to meet. In the face of such current situation, the use of flip chip bonding process is more and more urgent. In the superconducting quantum chip based on flip chip bonding, a top chip is flip-chip bonded on a bottom chip, and the top chip and the bottom chip are connected through indium columns for signal connection and common grounding.

The use of a flip-chip bonding process can present a problem: the double-layer chip is too close to each other (for example, on a micrometer scale), and the overlapped part of the front surfaces of the two layers of chips cannot be observed (because the chip substrate is opaque and the surface of the chip is provided with the opaque metal or dielectric layer for manufacturing various circuits and devices), so that the relevant manufacturing process level, including the alignment condition, of the part of the area cannot be judged.

In such cases where the chip cannot be observed with an electron microscope, electrical performance testing is often the best practice. The quality of the chip is judged by testing the on-off of the circuit, or a test structure is designed in the chip in advance, and the process level is judged by the test structure.

However, this testing method has certain limitations, for example, the testing range is limited, and the location and link of the problem cannot be accurately located. In addition, the indium column is an important link for flip chip bonding, and plays roles of signal transmission, chip common ground, chip stabilization and the like, but at present, no good method is provided for observing the manufacturing condition of the indium column, and no method is provided for testing the manufacturing process level of the indium column.

Therefore, a more convenient detection method is needed, which can quickly and effectively detect the manufacturing condition of the chip and can be used for the process level test of the indium columns.

Disclosure of Invention

In view of the above, the present application discloses a flip chip and an alignment method, which have features to conveniently achieve alignment during fabrication, and thus have higher quality achieved in a more efficient and simple way. Further, the design scheme of the flip chip allows the condition of the indium columns used in the flip chip to be inspected, and the manufacturing quality of the indium columns or the alignment condition of the indium columns to be judged.

The scheme exemplified in the present application is implemented as follows.

In a first aspect, the present examples are directed to a flip chip.

This flip chip includes: a first chip and a second chip which are opposite;

the first chip is defined with a functional area at least used for configuring a first quantum component, and the functional area is also configured with a first marking component;

the second chip has a transparent substrate and a film layer at least for configuring a second quantum component;

the substrate has a front surface and a back surface which are distributed along the opposite direction, the front surface faces the functional region in a face-to-face manner, the film layer is formed on the front surface, and the film layer has a through opening facing the first marking member.

In the above flip chip, the first marking member is provided on the first chip, and the transparent substrate and the film layer formed on the substrate and having the opening are provided on the second chip. Thus, during the manufacture of the flip chip, the first chip and the second chip can be manipulated so as to allow the first marking means located on the first chip to be viewed sequentially through the transparent substrate and the opening of the second chip.

Then, the alignment of the first chip and the second chip can be evaluated based on the observed relative position relationship between the first marking member and the opening, so that the quality of the flip chip can be estimated.

Accordingly, when the indium columns are applied to a flip chip designed in, for example, a superconducting quantum computing device, the fabrication quality and alignment of the indium columns can also be evaluated using this scheme.

In short, the above-mentioned flip-chip scheme of the present application provides important basis for alignment by the chip itself (rather than by electrical measurement), so that alignment operation and verification of alignment can be conveniently and quickly performed.

According to some examples of the present application, the opening has the same shape as the first marker member; and/or the first marking part is columnar; and/or the first marking parts are a plurality of cylinders, and the diameters of the first marking parts are different.

According to some examples of the present application, the first marker member and the opening are each cross-shaped.

According to some examples of the application, the openings cover at least the first marker feature in a projection area of the functional zone in the opposite direction.

According to some examples of the present application, the flip chip further comprises: a second marking member configured to be aligned with the first marking member; the second marking member is formed on the front surface of the substrate and is located within an area defined by the opening.

According to some examples of the present application, the first marker member and the second marker member are each linear.

According to some examples of the present application, the number of the first marking members is equal to the number of the second marking members, and is at least three, respectively;

the first marking parts are arranged at equal intervals along the first path;

the second marking parts are arranged along the second path at equal intervals or variable intervals;

the first path is parallel to the second path.

According to some examples of the present application, the respective second marking members are arranged at varying intervals along the second path;

the flip chip is defined with a first direction and a second direction which are opposite to each other along a second path;

all the second marking members are composed of a main member, and first and second sub-members located on both sides of the main member;

the spacing between two adjacent first sub-members in the first direction gradually increases and the spacing between two adjacent second sub-members in the second direction gradually decreases.

According to some examples of the present application, the number of the first marking members is equal to the number of the second marking members, and is at least two, respectively.

According to some examples of the present application, the first and second marking members are arranged in pairs to form an alignment structure assembly, and the first and second marking members of the same pair are cylinders of the same diameter;

the flip chip is provided with at least two groups of alignment structure components, and the diameters of cylinders in different groups are different.

In a second aspect, the present examples propose an alignment method for fabricating a flip chip. The alignment method comprises the following steps:

providing a first chip having a first marking element;

providing a second chip, wherein the second chip is provided with a substrate and a film layer, the substrate is transparent, the film layer is formed on the surface of the substrate and has a preset thickness, and the film layer is provided with an opening which is arranged in a penetrating manner along the thickness direction;

the first chip and the second chip are distributed in a layered mode along the preset direction, and the first marking part is opposite to at least part of the opening along the preset direction.

According to some examples of the application, the alignment method further comprises: and adjusting the first chip and/or the second chip so that the projection of the first marking part along the preset direction is positioned in the opening.

According to some examples of the present application, the second chip further includes a second marker feature formed on the surface of the substrate, the second marker feature having the same shape as the first marker feature, the second marker feature being located within the opening;

the alignment method further comprises a first operation or a second operation;

the first operation includes: causing the first marking member to coincide with the second marking member in a preset direction;

the second operation includes: one of the first and second marking members is completely covered by the other in a preset direction.

Has the advantages that:

compared with the prior art, the flip chip of the application example is characterized in that the marking component is arranged in one layer of the chip, the transparent substrate is selected in the other layer of the chip adjacent to the transparent substrate, and the film layer with the opening is arranged on the substrate. The marking member also corresponds to the opening of the film layer. Therefore, the marking member can be observed through the opening from the transparent substrate side when the flip chip is manufactured. According to the observed distribution of the marking parts and the openings, the alignment condition of the flip chip can be further estimated, and accordingly, the quality of the flip chip can be reflected.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments or the prior art of the present application, the drawings used in the embodiments or the prior art description will be briefly described below.

Fig. 1 is a schematic structural diagram of a first flip chip provided in an embodiment of the present application at a viewing angle;

FIG. 2 is a schematic diagram of the flip chip of FIG. 1 from another perspective;

fig. 3 is a schematic structural diagram of a second flip chip provided in an embodiment of the present application at a viewing angle;

fig. 4 is a schematic structural diagram of a third flip chip provided in an embodiment of the present application at a viewing angle;

fig. 5 isbase:Sub>A schematic structural diagram ofbase:Sub>A fourth flip chip provided in the present embodiment (fig. ii isbase:Sub>A schematic cross-sectional structural diagram alongbase:Sub>A planebase:Sub>A-base:Sub>A);

fig. 6 is a schematic structural diagram of a fifth flip chip provided in the embodiment of the present application;

fig. 7 discloses a schematic layout of a first and a second marking feature in the flip chip of fig. 6;

fig. 8 discloses schematic diagrams of three alignment conditions of a single first mark component and a single second mark component in another flip chip provided by an embodiment of the application.

Icon: 101-a first chip; 1011-a first marker component; 102-a second chip; 1021-a film layer; 1022-an opening; 103-cylindrical marker means; 1033-second marking means.

Detailed Description

Flip chip technology is an important means to achieve the expansion of the number of qubits integrated in a quantum chip. But due to the vulnerability of qubits-which are very susceptible to the adverse effects of noise-the application of flip-chip technology places very high demands on its maturity and consistency. However, as far as the present inventors know, the current flip chip technology has not been able to meet the above requirements well. Therefore, the quantum chips fabricated by the flip chip technology require complex and extensive testing to ensure that they meet the design requirements and are consistent with the design goals.

In particular to superconducting quantum chips, flip chip technology requires the use of indium pillars as an interconnect structure between chips in adjacent layers in current practice. And the indium columns may also be selectively configured to support the upper and lower chips or to distribute lines (e.g., various transmission lines; read buses) or components out-of-plane to the upper and lower chips.

Therefore, when the indium columns are tilted or the upper and lower layers to be connected are not accurately connected, the indium columns can cause potential failures of various lines and components. In other words, when applying the flip chip technique, the alignment of the indium studs needs to be considered specifically. However, as mentioned above, the distance between the upper and lower chips flipped in the chip, especially in the quantum chip, is short, and it is difficult to directly observe the posture and structure of the indium columns in the flipped chip, and the alignment.

Based on such current situation, one possible solution is to configure a corresponding test circuit structure when designing a chip, and perform electrical measurement to obtain corresponding measurement response data, so as to analyze the potential problems of the indium columns from the response data.

However, it is foreseeable that, since the measurement circuit structure needs to be configured in the chip, how to design the measurement circuit structure and how to reduce the adverse effect of the measurement circuit on the chip to be smaller is an important issue. In addition, since the measurement circuit structure is additionally configured, it necessarily occupies a limited space of the chip, thereby possibly causing the scalability of the chip to be limited to some extent.

In view of the above, through practical studies, the inventors propose a scheme for confirming the alignment condition of the indium columns in the present application; which will be described in detail later. It should be noted that although the foregoing has been described primarily in terms of a flip-chip configuration using indium pillars in a superconducting quantum chip. This is not intended to limit the exemplary aspects of the present disclosure to be applicable only to the examination of alignment of indium columns (or other components, such as through-silicon-via structures, etc.) in superconducting quantum chips.

In fact, the scheme of the present example can also be applied to flip-chip interconnection operations of other types of quantum chips, so as to confirm the components that need to be considered in terms of alignment. And further, the present exemplary scheme is equally applicable to the confirmation of alignment during application of the flip-chip solution in conventional/classical chips other than quantum chips.

In general, the scheme of the present example is proposed based on the following consideration:

in the flip-chip structure, it is selected to confirm whether the upper and lower chips are aligned by direct observation (observation with an electron microscope is generally selected in consideration of the size of the chip). And accordingly, a mark for identifying whether or not to be aligned, and a visible region for performing observation are configured.

In contrast, in the existing flip-chip configuration, since the substrate of each chip and the components and lines thereon are non-transparent (i.e., non-visible/non-visible), the use of the measurement circuit configuration for alignment verification as described above is selected. The transparent substrate capable of providing the visible area is selected, and the area to be observed is configured to be free of lines or elements, so that the shielding is avoided, and the observation is allowed.

Thus, in the example a flip chip is proposed to which the above described alignment scheme is applied. The flip chip of this alignment scheme includes a first chip 101 and a second chip 102. The first chip 101 and the second chip 102 are arranged facing each other, i.e., facing each other, in a layered structure distribution. In the present example, the first chip 101 is described as a lower chip, and the second chip 102 is described as an upper chip.

For a quantum chip, such as a superconducting quantum chip, the first chip 101 has a substrate (e.g., a silicon substrate or a sapphire substrate; either transparent or non-transparent), and various structures, such as quantum wires and devices, are disposed on the surface of the substrate (facing the second chip 102). Similarly, the second chip 102 also has a substrate (transparent material to provide a viewing area for viewing; sapphire in the present example), and the surface of the substrate (facing the first chip 101) may also be configured with various quantum wires and devices as desired.

As a differential description, the quantum wire and the device configured in the first chip 101 may be described as a first quantum member, and the quantum wire and the device configured in the second chip 102 may be described as a second quantum member. These quantum components are, for example, signal lines, such as coplanar waveguide transmission lines, or coplanar waveguide resonant cavities, which may serve as read cavities, or read buses, or various control lines, etc., or various capacitive elements, etc.

The bottom chip generally has a larger plane size than the upper chip in consideration of facilitating connection of the chip with various measurement and control systems outside, that is, along the opposite direction of the two, the projection of the upper chip occupies only a certain area on the lower chip, and usually not the surface area of the entire lower chip. Therefore, the projection overlapping region of the lower chip with the upper chip in the opposing direction can be described as a functional region. Thus, the aforementioned first quantum component best is placed within the functional region, whereas outside the non-functional/functional region, pads of the line may be configured for connection, such as wire bonding.

Further, as an identification target of alignment, the first marker member 1011 is disposed in the functional region of the first chip 101, and may be fabricated by, for example, evaporation coating (for example, electron beam evaporation coating), chemical vapor deposition, molecular beam epitaxy, sputtering, or the like. The material of the first marker member 1011 may be various metal materials; or other materials as desired such as oxides and the like. The first marker member 1011 can be used as an important reference for aligning the upper and lower chips when manufacturing the flip chip.

As a structure for fitting the first marker member 1011, the second chip 102 is provided with a window for viewing the first marker member 1011 in a direction in which the upper and lower chips face each other. In an example, the second chip 102 is selected from a transparent substrate, and then a film layer 1021, which may be an aluminum film or an aluminum film, is disposed on the surface of the transparent substrate, and may be used to construct a structure such as a read bus, a read resonant cavity, a coupling structure, and the like in the superconducting quantum chip.

For convenience of description and clarity of illustration, the transparent substrate has a front side (facing the first chip 101) and a back side (facing away from the first chip 101) distributed in opposite directions (which may be described as thickness direction of the flip chip in some examples). Based on this, the front surface of the transparent substrate faces the functional region of the first chip 101 in a face-to-face manner; correspondingly, the film 1021 is formed on the front surface of the second chip 102, and the film 1021 also has a through opening 1022 facing the first mark section 1011 and extending in the opposite direction.

As a distinction, in the conventional flip chip, the upper and lower chips are generally non-transparent substrates, and the surfaces thereof are further provided with non-transparent films such as dielectric films or metal films — which can be used to form various functional devices or structures, such as transmission lines or as capacitor plates. In such a case, the visible region cannot be provided and the possibility of observation cannot be achieved. In the present application, while the transparent substrate is selected to be used to fabricate the second chip 102, the non-light-transmissive film 1021 on the surface of the transparent substrate is provided with an opening 1022, so as to allow observation to be performed on the first chip 101 through the transparent substrate and the opening 1022. The opening 1022 can be obtained by performing a selective photolithography operation on the film 1021 by using a mask, which is not described herein.

After the first chip 101 and the second chip 102 are constructed in the above-described manner, the first chip 101 and the second chip 102 may be flip-chip interconnected, and then the first marker member 1011 on the first chip 101 is viewed from the back side of the second chip 102. Therefore, the alignment of the two chips can be determined according to the preset alignment relationship between the first mark member 1011 and the opening 1022 and the alignment relationship between the two when actually observed.

Illustratively, the opening 1022 may be configured in a cross-shaped configuration, and accordingly, the first marker member 1011 may also be configured in a cross-shaped configuration. Both may also have the same structural dimensions and therefore the upper and lower chips may be considered to be precisely aligned when they are coincident, for example, see fig. 1 and 2. Alternatively, in other examples, where the opening 1022 has the same cross-like shape as the first marker component 1011, the opening 1022 also has a larger dimension than the first marker component 1011. Thus, when viewed, the first marker feature 1011 may be positioned within the confines of the opening 1022; as an example, only a schematic of the structure in a top view is shown and shown in fig. 3.

In other examples, the opening 1022 and the first marker member 1011 may be configured in a linear, circular, or polygonal manner. For example, if both are circular with equal diameter, the precise alignment of the upper and lower chips can be the coincidence of the two; or the two are circles with different diameters, and the accurate alignment of the two can be the centers of the circles to be coincident. It can be understood that, in an example where the openings 1022 and the first mark member 1011 are overlapped, the projection area of the opening 1022 of the second chip 102 on the functional region of the first chip 101 is completely covered and overlapped with the first mark member 1011 in the direction in which the upper and lower chips are opposed, as shown in fig. 2. In other non-coincident examples, the projection area of the opening 1022 of the second chip 102 on the functional region of the first chip 101 is completely covering the first marker member 1011, and also extends beyond the first marker member 1011; as shown in fig. 3.

It should be understood that the alignment form and structure of the opening 1022 and the first mark member 1011 under the viewing angle may correspond to the alignment result of the first chip 101 and the second chip 102 according to a pre-designed mode, and is not limited in the above-mentioned manner.

Although a plurality of examples are given above in which the opening 1022 and the first marker part 1011 have the same shape, in other examples, the opening 1022 and the first marker part 1011 may have different shapes. For example, opening 1022 is rectangular, while the first label is circular; the precise alignment of the upper and lower chips may be such that the circle is within the rectangle and the four sides of the rectangle are tangent to the circle.

Furthermore, the first marker member 1011 of the above example may optionally be configured in a planar configuration (having dimensions within the surface of the first chip 101; e.g., length and width, etc.), such that the first marker member 1011 located on the first chip 101 is generally remote from the second chip 102. In other examples, the first marker feature 1011 may also be selected to be a columnar structure, and thus it may also have another dimension, i.e., a height, than the dimension within the surface of the first chip 101. Accordingly, the first marker member 1011 may be configured as a cylinder, a prism, or the like. Thus, in some examples, the opening 1022 may be configured as a rectangle, while the first marker feature 1011 is configured as a cylinder/circular in cross-section. Thus, the upper and lower chip alignments may be orthographic projections of cylinders within the openings 1022.

The number of the first marker members 1011 may be one or more in number. As shown in fig. 4, there are three first marker members 1011. The three first marks are respectively arranged on the first chip 101, and the three first marks are cylindrical with different diameters; other examples may have the same diameter. In other words, when there are a plurality of first marker members 1011, and each of the first marker members 1011 is cylindrical, the diameter of each of the first marker members 1011 may be different. For example, all the first marker members 1011 have different cylindrical diameters, or are partially the same, while the others are different.

In the above example, the alignment member (i.e., the first mark member 1011) is mainly disposed on the first chip 101, but in some examples, the first mark member 1011 disposed on the first chip 101 may be alternatively disposed to be formed of a first cylinder and a second cylinder, and the two cylinders may be disposed on the first chip 101 and the second chip 102, respectively. Alternatively, a part of the first mark member 1011 is configured as a cylinder and is located on the first chip 101; while the other first marker members 1011 are replaced with first and second cylinders arranged at the first chip 101 and the second chip 102, respectively (the cylinders may be contacted at the ends to form the cylindrical marker members 103); please refer to fig. 5.

Similarly, an example in which the first chip 101 and the second chip 102 are respectively provided with the alignment members, the first mark member 1011 and the second mark member 1033, will be described later, and therefore, the first mark member 1011 and the second mark member 1033 may be provided in pairs to form an alignment structural component. The number of alignment features may be one or more pairs, and features of the same pair may be of the same size, e.g., diameter, and features of different pairs may be of different sizes, e.g., diameters. Illustratively, the first marker feature 1011 and the second marker feature 1033 in the same pair of assemblies are cylinders of the same diameter. It will be appreciated that the first and second marking members 1033 in the form of a cylindrical body in such an example can be considered as the aforementioned first and second cylinders. Thus, the two chips are aligned up and down in the flip chip (for example, the two chips are both cylinders, and the two chips are aligned up and down in a coaxial manner through the axes of the two chips), so that whether the chips of the upper layer and the lower layer are accurately aligned is judged through the alignment conditions of the two chips.

In an example in which the marking member is disposed corresponding to the first chip 101 and the second chip 102, respectively, the second marking member 1033 is formed on the front surface of the substrate of the second chip 102 and is also located in an area defined by the opening 1022 opened in the film layer 1021 on the surface of the substrate. As for the shapes of the two marking members, the two marking members are generally selected to be arranged in the same shape (different sizes; of course, the two marking members may have the same size) similarly to the first marking member 1011, so as to reduce the difficulty in positioning the two marking members. The foregoing gives examples of cylinders, in other examples, both may also be configured as stripe structures, narrow band structures, and so on. For example, various line structures, illustratively coplanar waveguide transmission lines, are possible.

As a specific and alternative explanation, a specific and non-limiting explanation is made below with respect to the first marker member 1011 and the second marker member 1033.

In the example, the first marker member 1011 and the second marker member 1033 are linear type respectively; for example, a belt-like structure having a rectangular cross section with the same width. In these examples, as described previously, the first marker part 1011 and the second marker part 1033 are present in pairs and are appropriately configured; it follows that the number of first marker elements 1011 and second marker elements 1033 is, for example, equal.

As previously mentioned, pairs of marking elements may be one, two, three, or even more pairs. The scheme of multiple pairs of marking parts can ensure higher precision in alignment operation, and avoid the inconsistency of alignment results and expected results caused by deviation generated when the marking parts are manufactured when one pair of the marks are configured.

The arrangement of the marking elements present in pairs can be arbitrarily chosen manually, depending on the alignment actually required. For example, the marking member is linear, it may be arranged horizontally, or vertically, or obliquely with respect to the vertical direction or the horizontal direction.

The first marker unit 1011 and the second marker unit 1033 are arranged in at least three pairs. Illustratively, the first marker members 1011 located on the first chip 101 may be selected to be equally spaced along the first path; accordingly, the respective second marking parts 1033 located at the second chip 102 are arranged at equal or varying intervals along the second path; wherein the first path is flat with the second path.

As shown in fig. 6 and 7, the first marker members 1011 of the respective straight lines are arranged to extend in the vertical direction, and all the first marker members 1011 are arranged at equal intervals in the horizontal direction; meanwhile, the respective linear second mark members 1033 are arranged extending in the vertical direction, and all the second mark members 1033 are arranged at equal intervals in the horizontal direction.

Specifically, as shown in fig. 7, 9 first marker members 1011 are arranged at equal intervals in the horizontal direction; while 9 second marking members 1033 are arranged at equal intervals in the horizontal direction. And wherein two types of marking elements are arranged in such a way that:

the first marker component 1011 and the second marker component 1033 located at the intermediate positions are expected to be aligned in the aligned condition.

Further, according to the orientation shown in fig. 7, from the middle position to the right side, the first mark member 1011 and the second mark member 1033 distributed up and down are expected to be shifted in the horizontal direction in the case of chip alignment; in FIG. 7, there are offsets such as 2-, 4-, 6-, 8-, respectively, in turn. Similarly, according to the orientation shown in fig. 7, from the middle position to the left side, the first mark member 1011 and the second mark member 1033 distributed up and down are expected to have a horizontal direction shift in the case of chip alignment; in fig. 7, there are offsets such as 2+, 4+, 6+, 8+ in sequence, respectively.

Therefore, with the structural design shown in fig. 7, it is possible to determine whether the chips are aligned, and the direction of the shift and the distance of the shift. For example, if the middle first and

second marker members

1011, 1033 are aligned above and below, this indicates that alignment has been achieved. If the 2-indicated marking elements are aligned above and below, this may indicate that the upper chip is shifted to the right by 2 units, and so on.

Further, based on the need to examine whether there is a relative angular deviation between the upper and lower chips, a marking element may be disposed on each of the first chip 101 and the second chip 102. For example, the first chip 101 is provided with a first marking member 1011 of a linear type, and the second chip 102 is provided with a second marking member 1033 of a linear type; the two marker features may be of the same shape and size. Therefore, the upper and lower chips may be misaligned either horizontally or angularly.

For example, as shown in FIG. 8, where B represents alignment, A represents horizontal offset, and C represents angular offset. Fig. 8 illustrates three alignment cases in which the first mark member 1011 and the second mark member 1033 are not aligned with each other; in other examples, when the first mark 1011 and the second mark 1033 are designed to be aligned in a manner of overlapping, the alignment may be horizontal offset, angular offset, vertical offset, or the like.

As an example of adjustment of the scheme shown in fig. 6, the respective second marking members 1033 may be arranged at varying intervals along the second path. To illustrate the manner of the variable pitch arrangement, the flip chip is defined to have a first direction and a second direction along a second path and opposite to each other, e.g., horizontal left and horizontal right. And, all the second marking parts 1033 positioned at the second chip 102 are grouped into a main part, and a first sub part and a second sub part positioned at both sides of the main part. Then the process is repeated. On the basis of the above, the distance between two adjacent first sub-members arranged along the first direction may be gradually increased, and the distance between two adjacent second sub-members arranged along the second direction may be gradually decreased.

Based on the application example of the flip chip in the above example, an alignment method of the flip chip to the chips of the adjacent layers in the manufacturing process can be implemented as follows:

step S101, providing a first chip 101 and a second chip 102.

The two chips can be used for manufacturing films, circuits, elements and the like in various shapes and structures on a substrate by adopting various processes in a semiconductor integrated circuit.

Wherein a first marker element 1011 is arranged on a substrate (which may be sapphire or silicon) of the first chip 101 or a thin film on a surface of the substrate. The substrate of the second chip 102 is made of a transparent material, and sapphire is generally selected in the field of superconducting quantum chips. The second chip 102 surface is also configured with a film layer 1021 that can be used to form elements (e.g., coplanar waveguide transmission lines in superconducting quantum chips, resonators, etc.). Further, the film layer 1021 is provided with an opening 1022 in the thickness direction in a selected region. The opening 1022 allows the first marker member 1011 located in the first chip 101 to be viewed through the transparent substrate of the second chip 102 and then through the opening 1022 when the first chip 101 and the second chip 102 are opposed.

Step S102 is to distribute the first chip 101 and the second chip 102 in a layer shape along a predetermined direction, and align the first mark 1011 along a predetermined manner.

In this step, the first chip 101 may be placed on various bases, platforms, or supports, and may be horizontally placed to maintain a stable posture. Electrical connection, signal conduction, etc. can then be achieved by overlaying the second chip 102 onto the first chip 101 surface and by adaptively displacing the second chip 102 (horizontally and/or vertically; where the horizontal direction can be either a left, right, front, or back translational movement, or a rotational movement about a selected vertical direction) so that the two chips are close to each other by a distance sufficient to effect flip chip bonding, while also being aligned so that the components, etc. between the two are in precise contact.

In the above example, the first chip 101 is used as a fixing target, the second chip 102 is used as a moving target, and the first chip 101 is fixed and then the second chip 102 is displaced to align the two. In other examples, the first chip 101 and the second chip 102 may also be moved synchronously.

In addition, the alignment of the first marking unit 1011 along the predetermined direction described above may be: the first marker member 1011 is positioned facing at least a part of the opening 1022, or the projection of the first marker member 1011 in the opposing direction of the two chips is positioned within the opening 1022.

When the flip chip further includes the second mark member 1033, the alignment manner may be: the second marker component 1033 is located on the substrate surface of the second chip 102 and within the opening 1022. If the two mark members have the same shape, the alignment may be performed such that the first mark member 1011 and the second mark member 1033 are overlapped (when both are the same size), or such that one of the first mark member 1011 and the second mark member 1033 is completely covered by the other in a predetermined direction (when both are different size).

It should be understood that the alignment of the first chip 101 and the second chip 102 may also be other ways and criteria; specifically, it may be determined according to the relative position design relationship of the first marker member 1011 and the opening 1022 to be expected when designing the flip chip or further selectively configuring the second marker member 1033. For example, when the first mark member 1011 and the opening 1022 are designed to be aligned when they are expected to coincide, the judgment criterion for the alignment when the alignment operation is performed may be that the first mark member 1011 and the opening 1022 coincide.

In addition, in the alignment operation, in order to confirm whether or not alignment is performed and to adjust the alignment operation, observation using an electron microscope is possible. The observation may be performed in real time, or the photograph may be taken by an electron microscope and then recognized, measured, or the like, as necessary. For example, the region directly opposite to the film layer opening is observed perpendicularly in the thickness direction of the flip chip from above the transparent substrate using an electron microscope.

The construction, features and functions of the present application are described in detail in the embodiments illustrated in the drawings, which are only preferred embodiments of the present application, but the present application is not limited by the drawings, and all equivalent embodiments that can be modified or changed according to the idea of the present application are within the scope of the present application without departing from the spirit of the present application.

Claims

1. A flip chip, comprising: a first chip and a second chip which are opposite;

the first chip is defined with a functional region at least used for configuring the first quantum component, and the functional region is also configured with a first mark component;

the second chip is provided with a transparent substrate and a film layer at least used for configuring a second quantum component;

wherein the substrate has a front surface and a back surface which are distributed in opposing directions, the front surface facing the functional region in a face-to-face manner, the film layer being formed on the front surface, the film layer having a through opening which faces the first marker member and extends in the opposing directions.

2. The flip chip of claim 1, wherein the opening has the same shape as the first flag feature;

and/or the first marking part is columnar;

and/or the first marking parts are a plurality of cylinders, and the diameters of the first marking parts are different.

3. The flip chip of claim 1, wherein the first marking member and the opening are each cross-shaped.

4. The flip chip according to claim 1, 2 or 3, wherein the opening covers at least the first marking member in a projection area of the functional region in the opposing direction.

5. The flip chip of claim 1, further comprising: a second marking member configured to be aligned with the first marking member;

the second marking element is formed on the front surface of the substrate and is located within an area defined by the opening.

6. The flip-chip of claim 5, wherein the first marking member and the second marking member are each linear.

7. The flip chip of claim 6, wherein the number of the first marking parts is equal to the number of the second marking parts, and is at least three, respectively;

the first marking parts are arranged at equal intervals along the first path;

the first path is parallel to the second path.

8. The flip chip of claim 7, wherein the respective second indicia members are variably spaced along the second path;

the flip chip defines a first direction and a second direction along a second path and opposite to each other;

9. The flip chip of claim 5 or 6, wherein the number of the first marking parts is equal to the number of the second marking parts, and is at least two respectively.

10. The flip-chip of claim 5, wherein the first and second marking features are arranged in pairs to form an alignment structure assembly, and wherein the first and second marking features in the same pair of assemblies are cylinders of the same diameter;

the flip chip is provided with at least two groups of contraposition structure components, and the diameters of cylinders in different groups are different.

11. An alignment method for fabricating a flip chip, the alignment method comprising:

providing a first chip having a first marking element;

providing a second chip, wherein the second chip is provided with a substrate and a film layer, the substrate is transparent, the film layer is formed on the surface of the substrate and has a preset thickness, and the film layer is provided with an opening which penetrates through the film layer along the thickness direction;

the first chip and the second chip are distributed in a layered mode along a preset direction, and the first marking part is opposite to at least part of the opening along the preset direction.

12. The alignment method of claim 11, further comprising: and adjusting the first chip and/or the second chip so that the projection of the first marking part along the preset direction is positioned in the opening.

13. The alignment method as claimed in claim 12, wherein the second chip further comprises a second marking feature formed on the surface of the substrate, the second marking feature having the same shape as the first marking feature, the second marking feature being located within the opening;

the alignment method further comprises a first operation or a second operation;