CN115295534A - A Flip Chip and Alignment Method - Google Patents

Abstract

The application discloses a flip chip and an alignment method, and belongs to the field of quantum chip manufacturing. The flip chip includes opposing first and second chips. Wherein the first chip is provided with a first marking means and the second chip has a transparent substrate and a film layer formed on the substrate. The film layer has a through opening facing the first marker feature. The flip chip can conveniently execute the alignment operation in the manufacturing process, thereby obtaining higher alignment quality and further being beneficial to improving the yield of the flip chip.

Description

A Flip Chip and Alignment Method

technical field

The application belongs to the field of quantum chip preparation, and specifically relates to a flip chip and an alignment method.

Background technique

As the number of qubits in the designed quantum chip continues to increase, more and more content (various circuits, components, etc.) are etched on the quantum chip. Therefore, the design scheme of a single chip has been difficult to meet the requirements. Faced with such a situation, the use of flip-chip welding technology is becoming more and more urgent. In flip-chip-based superconducting quantum chips, the top-layer chip is flip-chip-bonded on the bottom chip, and the two are connected for signal and common ground through indium pillars.

There will be a problem in the use of the flip-chip welding process: the distance between the double-layer chips is too close (for example, on the micron scale), and the overlapping part of the front of the two-layer chips cannot be observed (the reason is that the chip substrate is opaque and the chip surface is opaque. Light-transmitting metal or dielectric layer used to make various circuits and devices), so it is impossible to judge the relevant manufacturing process level of this part of the area, including the alignment situation.

In cases where it is not possible to observe the chip with an electron microscope, electrical performance testing is usually the best solution. That is to judge the quality of the chip by testing the continuity of the circuit, or design the test structure in the chip in advance, and judge the process level through the test structure.

However, there are certain limitations in this testing method, such as the limited testing scope and the inability to accurately locate the location and link of the problem. And for the flip chip, the indium column is an important link, it plays the role of transmitting signals, sharing the ground of the chip, stabilizing the chip, etc., but currently there is no good way to observe the production of the indium column, and there is no There is a way to test the manufacturing process level of the indium column.

Therefore, there is a need for a more convenient detection method, which can quickly and effectively detect the production status of the chip, and can use this method to test the process level of the indium column.

Contents of the invention

In view of this, the present application discloses a flip-chip and alignment method, which is characterized by convenient alignment during the manufacturing process, and thus has higher quality achieved in a more efficient and simple manner. Further, the design scheme of the flip chip allows the inspection of the indium pillars used in the flip chip, and the judgment of the manufacturing quality of the indium pillars or the alignment of the indium pillars.

The solutions illustrated in this application are implemented through the following contents.

In the first aspect, the present application example proposes a flip chip.

The flip chip includes: a first chip and a second chip opposite to each other;

The first chip is defined with at least a functional area for configuring the first quantum component, and the functional area is also configured with a first marking component;

The second chip has a transparent substrate and at least a film layer for configuring the second quantum component;

Wherein, the substrate has a front side and a back side distributed along opposite directions, the front side faces the functional area in a face-to-face manner, a film layer is formed on the front side, and the film layer has a through opening facing the first marking component.

In the above-mentioned flip chip, the first marking member is arranged on the first chip, and at the same time, the transparent substrate and the film layer formed on the substrate and having openings are arranged on the second chip. Thus during the fabrication of the flip-chip, the first chip and the second chip can be manipulated, allowing the first marking feature located on the first chip to be observed sequentially through the transparent substrate and the opening of the second chip.

Then, the alignment of the first chip and the second chip can be evaluated according to the observed relative positional relationship between the first marking component and the opening, so that the quality of the flip chip can also be estimated.

Correspondingly, when indium pillars are applied to flip-chips designed in, for example, superconducting quantum computing devices, this solution can also be used to evaluate the fabrication quality and alignment of the indium pillars.

In short, the above-mentioned flip-chip solution of the present application provides an important basis for alignment by the chip itself (rather than based on electrical measurement results), so that the alignment operation and verification of alignment can be performed conveniently and quickly.

According to some examples of the present application, the opening has the same shape as the first marking component; and/or, the first marking component is columnar; and/or, the first marking component has multiple cylinders, and each first marking Parts have different diameters.

According to some examples of the present application, the first marking part and the opening are respectively cross-shaped.

According to some examples of the present application, along the opposite direction, the projected area of the opening on the functional area at least covers the first marking component.

According to some examples of the present application, the flip chip further includes: a second marking part configured to be aligned with the first marking part; the second marking part is formed on the front side of the substrate and is located in an area defined by the opening.

According to some examples of the present application, the first marking part and the second marking part are respectively linear.

According to some examples of the present application, the number of the first marking components is equal to the number of the second marking components, and are respectively at least three;

Each first marking component is arranged at equal intervals along the first path;

The respective second marking components are arranged at equal intervals or at variable intervals along the second path;

The first path is parallel to the second path.

According to some examples of the present application, each second marking component is arranged at variable intervals along the second path;

The flip chip defines a first direction and a second direction along the second path and opposite to each other;

All the second marking parts are composed of a main part, and first and second sub-parts located on both sides of the main part;

The distance between two adjacent first subcomponents along the first direction gradually increases, and the distance between two adjacent second subcomponents along the second direction gradually decreases.

According to some examples of the present application, the number of the first marking components is equal to the number of the second marking components, and they are at least two respectively.

According to some examples of the present application, the first marking component and the second marking component are configured in pairs to form an alignment structural component, and the first marking component and the second marking component in the same pair are cylinders with the same diameter;

The flip chip has at least two sets of alignment structural components, and the cylinders of different sets have different diameters.

In a second aspect, the present application exemplarily proposes an alignment method for manufacturing a flip chip. Alignment methods include:

providing a first chip having a first marking feature;

A second chip is provided, having a substrate and a film layer, the substrate is transparent, the film layer is formed on the surface of the substrate and has a preset thickness, and the film layer has an opening configured through the thickness direction;

The first chip and the second chip are distributed in layers along a preset direction, and the first marking component faces at least part of the opening along the preset direction.

According to some examples of the present application, the alignment method further includes: adjusting the first chip and/or the second chip so that the projection of the first marking component along a preset direction is located within the opening.

According to some examples of the present application, the second chip further includes a second marking part formed on the surface of the substrate, the second marking part has the same shape as the first marking part, and the second marking part is located in the opening;

The alignment method further includes a first operation or a second operation;

The first operation includes: making the first marking part coincide with the second marking part along a preset direction;

The second operation includes: making one of the first marking part and the second marking part completely covered by the other along a preset direction.

Beneficial effect:

Compared with the prior art, the flip chip example in this application configures marking components in one layer of chips, and at the same time selects a transparent substrate in another layer of chips adjacent to it and configures a transparent substrate with openings in the substrate. film layer. The marking means also correspond to the openings of the film layer. Therefore, the marking member can be observed through the opening from the transparent substrate side during flip chip fabrication. According to the observed distribution of the marking components and the openings, the alignment of the flip chip can be inferred, and accordingly the quality of the flip chip can also be reflected.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application or in the prior art, the following briefly introduces the drawings that are required in the description of the embodiments or the prior art.

FIG. 1 is a schematic structural view of the first flip chip provided by the embodiment of the present application under a viewing angle;

Fig. 2 is a structural schematic diagram of the flip chip of Fig. 1 under another viewing angle;

FIG. 3 is a schematic structural view of the second flip chip provided by the embodiment of the present application under a viewing angle;

FIG. 4 is a schematic structural view of a third flip chip provided by the embodiment of the present application under a viewing angle;

Figure 5 is a schematic structural view of the fourth flip-chip provided in the embodiment of the present application (Figure 2 is a schematic cross-sectional structural view of Figure 1 along the A-A plane);

FIG. 6 is a schematic structural diagram of a fifth flip chip provided in the embodiment of the present application;

FIG. 7 discloses a schematic diagram of the layout structure of the first marking component and the second marking component in the flip chip of FIG. 6;

FIG. 8 discloses a schematic diagram of three alignment situations of a single first marking component and a single second marking component in another flip chip provided by an embodiment of the present application.

Icons: 101-first chip; 1011-first marking component; 102-second chip; 1021-film layer; 1022-opening; 103-cylindrical marking component; 1033-second marking component.

Detailed ways

Flip-chip bonding technology is an important means to expand the number of qubits integrated in quantum chips. But due to the fragility of qubits—very susceptible to adverse effects from noise—flip-chip applications require a high degree of maturity and consistency. However, as far as the inventors of the present application know, the current flip-chip technology cannot well meet the aforementioned requirements. Therefore, quantum chips made using flip-chip bonding technology need to undergo complex and numerous tests to ensure that they meet the design requirements and are consistent with the design goals.

Specific to superconducting quantum chips, in current practice, flip-chip bonding technology needs to use indium pillars as the interconnection structure between adjacent layers of chips. And the indium column can also be selectively configured to support the upper and lower chips, or to distribute some lines (such as various transmission lines; read bus) or components to the upper and lower chips in different planes.

Therefore, when the indium column is tilted, or the upper and lower structures that it needs to connect are not connected accurately, it will lead to potential failure of various circuits and components. In other words, when applying the flip chip technology, it is necessary to pay special attention to the alignment of the indium pillars. However, as mentioned above, in a chip, especially in a quantum chip, the distance between the flip-chip upper and lower chips is short, so it is difficult to directly observe the posture and structure of the indium column in the flip-chip, and the standard situation.

Based on this situation, one possible solution is to configure the corresponding test circuit structure when designing the chip, and obtain the corresponding measurement response data through electrical measurement, and then analyze the potential problems of the indium column based on the response data.

However, it is foreseeable that since the measurement circuit structure needs to be configured in the chip, how to design the measurement circuit structure and how to minimize the adverse impact of the measurement circuit on the chip is an important issue. In addition, due to the additional configuration of the measurement circuit structure, it will inevitably occupy a limited space on the chip, which may lead to limited scalability of the chip to a certain extent.

In view of this, after practical research, the inventor proposed a scheme for confirming the alignment of the indium pillars in this application; it will be described in detail later. It should be pointed out that although the above description is mainly based on the flip-chip structure using indium pillars in the superconducting quantum chip. However, this is not intended to limit the solution exemplified in the present application to the investigation of the alignment of indium pillars (or other components, such as TSV structures, etc.) in superconducting quantum chips.

In fact, the solutions exemplified in this application can also be applied to the flip-chip interconnection operations of other types of quantum chips, so as to confirm the components that need to consider the alignment. And further, for the confirmation of the alignment of the non-quantum chip conventional chip/classical chip during the application process of the flip-chip technology solution, the example solution of the present application is also used.

In general, the scheme of the example in this application is proposed based on the following considerations:

In the flip-chip structure, choose to confirm the alignment of the upper and lower chips by direct observation (considering the size of the chip, usually with an electron microscope). And correspondingly, a mark for identifying alignment and a visible area for observation are configured.

As a difference, in the existing flip-chip structure, since the substrates of each layer of chips and the components and circuits on them are non-transparent (that is, non-observable/non-visible), we choose to use the measurement circuit structure as mentioned above to perform the test. confirmation of the status. However, this application chooses to use a transparent substrate that can provide a visible area, and then configures the area to be observed so that no lines or components are provided, so as to avoid occlusion and allow observation.

Therefore, a flip chip applying the above-mentioned alignment scheme is proposed in an example. The flip chip of this alignment scheme includes a first chip 101 and a second chip 102 . In addition, the first chip 101 and the second chip 102 are distributed in a layered structure and arranged facing each other, that is, facing each other. In the example of the present application, the first chip 101 is described as a lower chip, and the second chip 102 is described as an upper chip.

For a quantum chip, such as a superconducting quantum chip, the first chip 101 has a substrate (such as a silicon substrate or a sapphire substrate; transparent or non-transparent), and on the surface of the substrate (facing the second chip 102) Configure structures such as quantum circuits and devices. Similarly, the second chip 102 also has a substrate (transparent material, so as to provide a visible area for observation; in the example of this application, it is sapphire), and the surface of the substrate (facing the first chip 101) can also be configured in various ways as required. Quantum circuits and devices.

As a distinction description, quantum circuits and devices configured in the first chip 101 may be described as first quantum components, while quantum circuits and devices configured in the second chip 102 may be described as second quantum components. These quantum components are, for example, signal lines, such as coplanar waveguide transmission lines, or coplanar waveguide resonators, which can be used as readout chambers, or readout buses, or various control lines, etc., or various capacitive elements, etc.

Based on the consideration of facilitating the connection between the chip and various external measurement and control systems, the above-mentioned bottom chip usually has a larger plane size than the upper chip, that is, along the opposite direction of the two, the projection of the upper chip only occupies a certain area on the lower chip. And usually not all of the surface area of the underlying chip. Therefore, the overlapping area of the projection of the lower chip and the upper chip in the opposite direction can be described as a functional area. Thus, all the aforementioned first quantum components are arranged in the functional area, and pads of circuits can be arranged outside the non-functional area/functional area for connection such as wire bonding.

Further, as an identification object for alignment, a first marking component 1011 is also arranged in the functional area of the first chip 101, for example, it can be formed by evaporation coating (eg electron beam evaporation coating for example), chemical vapor deposition, molecular beam epitaxy , sputtering and other methods for production. The material of the first marking component 1011 may be various metal materials; or other materials as required, such as oxides and the like. The first marking part 1011 can be used as an important basis for aligning upper and lower chips when making flip chips.

Furthermore, as a structure cooperating with the first marking member 1011 , a window is arranged on the second chip 102 for observing the first marking member 1011 in a direction in which the upper and lower chips face each other. In an example, the second chip 102 chooses to use a transparent substrate, and then configures a film layer 1021 on its surface, such as an aluminum film or an aluminum film layer, which can be used to construct such things as a read bus and read resonance in a superconducting quantum chip. cavities, coupling structures, etc.

For the convenience of description and clarity, the transparent substrate has a front side (facing the first chip 101 ) and a back side (facing away from the first chip 101 ) distributed along the opposite direction (in some examples, it can be described as the thickness direction of a flip chip). . Based on this, the front side of the transparent substrate faces the functional area of the first chip 101 in a face-to-face manner; correspondingly, the film layer 1021 is formed on the front side of the second chip 102. Through openings 1022 extending in opposing directions.

As a distinction, in the existing flip chips, the upper and lower chips are generally non-transparent substrates, and their surfaces also have non-transparent films such as dielectric films or metal films—which can be used to form various functions. Sexual devices or structures, such as transmission lines or as capacitive plates, etc. In such a case, no viewing area is provided and no viewing possibilities are possible. In this application, while choosing to use a transparent substrate to make the second chip 102, an opening 1022 is also provided on the non-transparent film layer 1021 on the surface of the transparent substrate, thereby allowing the transparent substrate and the opening 1022 to pass through the transparent substrate. The first chip 101 performs observation. The opening 1022 can be obtained by using a mask to perform selective photolithography on the film layer 1021 , which will not be repeated here.

After constructing the first chip 101 and the second chip 102 in the above-mentioned manner, the first chip 101 and the second chip 102 can be flip-chip interconnected, and then the second chip on the first chip 101 can be observed from the back of the second chip 102. A marking part 1011. Thus, the alignment of the two-layer chip can be determined according to the preset alignment relationship between the first marking component 1011 and the opening 1022 and the alignment relationship between the two in actual observation.

Exemplarily, the opening 1022 may be configured in a cross-shaped structure, and accordingly, the first marking component 1011 may also be configured in a cross-shaped structure. Both may also have the same structural dimensions, and therefore, the upper and lower chips may be considered to be precisely aligned when the two are superimposed, see eg FIGS. 1 and 2 . Or, in some other examples, when the opening 1022 and the first marking part 1011 have the same cross-shaped shape, the opening 1022 also has a larger size than the first marking part 1011 . Therefore, when viewed, the first marking component 1011 may be located within the range defined by the opening 1022; as an example, only a schematic view of the structure at a top view angle is shown as shown in FIG. 3 .

In other examples, the opening 1022 and the first marking part 1011 may also be configured in a linear, circular, or polygonal manner. For example, if both are selected as circles with equal diameters, the precise alignment of the upper and lower chips can be that the two coincide; or if the two are circles with different diameters, the precise alignment of the two can be that the centers of the two coincide. It can be known that, in the example where the openings 1022 overlap with the first marking part 1011, along the direction in which the upper and lower chips face each other, the projection area of the opening 1022 of the second chip 102 on the functional area of the first chip 101 is completely covered and overlapped. For the first marking part 1011, as shown in FIG. 2 . In other non-overlapping examples, the projected area of the opening 1022 of the second chip 102 in the functional area of the first chip 101 completely covers the first marking part 1011, and also extends beyond the first marking part 1011; as shown in Figure 3 .

It should be understood that the alignment form and structure of the opening 1022 and the first marking part 1011 at the viewing angle of view, and the alignment results of the first chip 101 and the second chip 102 may correspond to a pre-designed pattern, not in the above described manner. for the limit.

Although a number of examples have been given above in which the opening 1022 and the first marking part 1011 have the same shape, in other examples, the opening 1022 and the first marking part 1011 may also have different shapes. For example, the opening 1022 is a rectangle, and the first mark is a circle; then the precise alignment of the upper and lower chips can be that the circle is inside the rectangle, and the four sides of the rectangle are tangent to the circle.

In addition, the first marking part 1011 of the above example can be selected to be constructed in a planar structure (with dimensions within the surface of the first chip 101; such as length and width, etc.), therefore, the first marking part 1011 located on the first chip 101, Usually away from the second chip 102 . In some other examples, the first marking component 1011 can also be selected as a columnar structure, so it also has another dimension besides the dimension on the surface of the first chip 101 , that is, a height. Correspondingly, the first marking component 1011 can be configured as a cylinder or a prism or the like. Therefore, in some examples, the opening 1022 may be configured as a rectangle, while the first marking member 1011 is configured as a cylinder/circular in cross section. Therefore, the alignment of the upper and lower chip can be that the orthographic projection of the cylinder is located in the opening 1022 .

In terms of quantity, the number of cylindrical or other first marking components 1011 may be one or more. As shown in FIG. 4 , there are three first marking components 1011 . The three first marks are respectively arranged on the first chip 101, and the three are cylindrical shapes with different diameters; in other examples, they may also have the same diameter. In other words, when there are a plurality of first marking parts 1011 and each of the first marking parts 1011 is cylindrical, the diameters of the respective first marking parts 1011 may be different. For example, the cylinder diameters of all the first marking components 1011 are different, or some of them are the same while the rest are different.

In the above example, the first chip 101 is mainly configured with an alignment component (that is, the first marking component 1011) as an example for illustration, however, in some examples, the first marking component that will be configured on the first chip 101 can also be selected The component 1011 is alternatively configured to be composed of a first cylinder and a second cylinder, and the two cylinders are respectively configured to the first chip 101 and the second chip 102 . Alternatively, some of the first marking components 1011 are configured as cylinders and located on the first chip 101; while other first marking components 1011 are replaced with first cylinders and second cylinders respectively configured on the first chip 101 and the second chip 102 ( The two cylinders may touch at the ends, thereby forming a cylinder marking part 103 ); see FIG. 5 .

Similarly, an example in which the first chip 101 and the second chip 102 are respectively configured with alignment components—the first marking component 1011 and the second marking component 1033—will be described later, therefore, the first marking component 1011 and the second marking component 1033 Can be configured in pairs to form parasite structural components. The number of alignment structural components can be one or more pairs, and the dimensions, such as diameter, of components in the same pair can be the same, and the dimensions, such as diameter, of components of different pairs can be different. Exemplarily, the first marking part 1011 and the second marking part 1033 in the same pair of components are cylinders with the same diameter. It can be known that the first and second marking members 1033 in the form of cylinders in this example can be regarded as the aforementioned first cylinder and second cylinder. In this way, the two are aligned up and down in the flip chip (for example, both are cylinders, and the two are used to pass the axis of the two, and the upper and lower alignment is performed in a coaxial manner), and are used for the alignment of the two The situation judges whether the chips on the upper and lower layers are aligned accurately.

Corresponding to the above-mentioned example where the first chip 101 and the second chip 102 are respectively equipped with marking components, the second marking component 1033 is formed on the front side of the substrate of the second chip 102, and is also located on the surface of the substrate formed by the film layer 1021. In the area defined by the opening 1022. As for the shape of the two marking parts, similar to the aforementioned configuration of the first marking part 1011, the two are usually selected to be configured in the same shape (can have different sizes; of course, they can also have the same size), so that the two parts can be reduced. The implementation difficulty of alignment. The foregoing content gives an example of a cylinder, and in other examples, the two can also be configured as a strip structure, a narrow strip structure, and the like. For example, it can be various line structures, exemplarily a coplanar waveguide transmission line.

As a specific and alternative description, the first marking part 1011 and the second marking part 1033 will be specifically and non-limitingly described below.

In an example, the first marking part 1011 and the second marking part 1033 are respectively linear; for example, a strip-like structure with a rectangular cross section having the same width. In these examples, as mentioned above, the first marking part 1011 and the second marking part 1033 appear in pairs and are properly configured; then it can be seen that the number of the first marking part 1011 and the second marking part 1033 is, for example, are equal.

As mentioned above, the paired marking components can be one pair, two pairs, three pairs, or even more pairs. With the multi-pair marking parts scheme, the accuracy of the alignment operation can be higher, and the alignment result is inconsistent with the expected result caused by the deviation in the production of the marking parts when configuring a pair.

In terms of arrangement, for these marking components that appear in pairs, the arrangement can be selected arbitrarily, based on the matching of the actual required alignment. For example, if the marking component is linear, it can be arranged horizontally, vertically, or inclined relative to the vertical or horizontal direction.

Take the configuration of at least three pairs of the first marking part 1011 and the second marking part 1033 as an example. Exemplarily, each first marking component 1011 located on the first chip 101 can be selected to be arranged at equal intervals along the first path; correspondingly, each second marking component 1033 located on the second chip 102 is equally spaced or variable pitched along the second path permutation; where the first path is level with the second path.

As shown in Figure 6 and Figure 7, each linear first marking part 1011 is extended in the vertical direction, and all the first marking parts 1011 are arranged at equal intervals along the horizontal direction; at the same time, each linear second marking part 1033 extend in the vertical direction, and all the second marking components 1033 are arranged at equal intervals in the horizontal direction.

In particular, as shown in FIG. 7 , nine first marking components 1011 are arranged at equal intervals in the horizontal direction; at the same time, nine second marking components 1033 are arranged at equal intervals in the horizontal direction. And, two of the marked components are arranged in this way:

The first marking member 1011 and the second marking member 1033 in the middle position are expected to be aligned under alignment conditions.

Further, according to the orientation shown in FIG. 7 , from the middle position to the right side, the first marking part 1011 and the second marking part 1033 distributed up and down are expected to be offset in the horizontal direction in the case of chip alignment; in FIG. 7 , There are offsets such as 2-, 4-, 6-, 8-in turn respectively. Similarly, according to the orientation shown in FIG. 7 , from the middle position to the left, the first marking part 1011 and the second marking part 1033 distributed up and down are expected to be shifted in the horizontal direction in the case of chip alignment; Each has offsets such as 2+, 4+, 6+, 8+.

Therefore, using the structural design shown in FIG. 7 , it is possible to judge whether the chips are aligned, as well as the offset direction and offset distance. For example, if the first marking part 1011 and the second marking part 1033 in the middle are aligned up and down, it means that they have been aligned. If the marked parts represented by 2- are aligned up and down, it can indicate that the upper chip is shifted to the right by 2 units, and so on.

Further, based on the need to investigate whether there is a relative angle deviation between the upper and lower chips, a marking component can be respectively arranged on the first chip 101 and the second chip 102 . For example, the first chip 101 is configured with a linear first marking component 1011 , and the second chip 102 is configured with a linear second marking component 1033 ; the two marking components may be of the same shape and size. Therefore, the upper and lower chips may be misaligned either horizontally or angularly.

For example, as shown in Fig. 8, where B diagram represents alignment, A diagram represents horizontal offset, and C diagram represents angular offset. In Fig. 8, three alignment situations are described in the non-overlapping alignment mode of the first marking part 1011 and the second marking part 1033; in other examples, when the first marking part 1011 and the second marking part 1033 are aligned according to If the alignment method is designed, then the alignment situation may also include the above-mentioned horizontal offset, angular offset, and vertical offset.

As an adjustment example of the scheme shown in FIG. 6 , each second marking component 1033 may also be arranged at variable intervals along the second path. To illustrate the variable-pitch arrangement, it is defined that the flip chip has a first direction and a second direction opposite to each other along the second path, such as horizontally left and horizontally right. And, all the second marking parts 1033 located on the second chip 102 are grouped into a main part, and first sub parts and second sub parts located on both sides of the main part. So. On this basis, the distance between two adjacent first sub-components arranged along the first direction may gradually increase, while the distance between two adjacent second sub-components arranged along the second direction may gradually decrease.

Based on the application example of the flip chip in the above example, a method for aligning chips on adjacent layers during the manufacturing process of the flip chip can be implemented in the following manner:

Step S101 , providing a first chip 101 and a second chip 102 .

The two chips can be manufactured with various shapes and structures of thin films, circuits, components, etc. on the substrate by using various processes in semiconductor integrated circuits.

Wherein the first marking component 1011 is disposed on the substrate (which may be sapphire or silicon) of the first chip 101 or a thin film on the surface of the substrate. The substrate of the second chip 102 is made of a transparent material, usually sapphire can be selected in the field of superconducting quantum chips. The surface of the second chip 102 is also provided with a film layer 1021 that can be used to form components (such as coplanar waveguide transmission lines in superconducting quantum chips, resonators, etc.). Furthermore, the film layer 1021 is also provided with openings 1022 along the thickness direction in selected regions. The opening 1022 allows the first marking component 1011 located in the first chip 101 to be observed through the opening 1022 through the transparent substrate of the second chip 102 when the first chip 101 and the second chip 102 face each other.

Step S102 , distributing the first chips 101 and the second chips 102 in layers along a preset direction, and aligning the first marking component 1011 in a preset manner.

In this step, generally, the first chip 101 may be selected to be placed horizontally on various bases, platforms or supports, so as to maintain a stable posture. Then by making the second chip 102 cover the surface of the first chip 101, and by carrying out adaptive displacement (horizontal and/or vertical direction; wherein the horizontal direction can be left, right, front and rear directions) to the second chip 102 Translational movement, or rotational movement with the selected vertical axis as the axis), so that the two chips are close enough to each other to perform flip-chip bonding, and the two are also aligned so that the components between the two are accurately aligned. Contact can realize electrical connection, signal conduction, etc.

In the above example, the first chip 101 is used as a fixed target, and the second chip 102 is used as a moving target. After the first chip 101 is fixed, the second chip 102 is displaced to align them. In other examples, the first chip 101 and the second chip 102 may also be moved synchronously.

In addition, the above-described alignment of the first marking component 1011 in a preset manner may be: aligning the first marking component 1011 to at least part of the opening 1022, or making the projection of the first marking component 1011 in the direction where the two chips face each other Located within the opening 1022.

When there is a second marking component 1033 in the flip chip, the alignment method may also be: the second marking component 1033 is located on the substrate surface of the second chip 102 and is inside the opening 1022 . When the two marking parts have the same shape, the alignment can also be to make the first marking part 1011 coincide with the second marking part 1033 (when the two are the same size), or make the first marking part 1011 and the second marking part One of 1033 is completely covered by the other (when the two sizes are different) along a predetermined direction.

It should be understood that the alignment of the first chip 101 and the second chip 102 can also be other methods and criteria; specifically, it can be based on the expected first marking component 1011 or the second marking component further selected when designing the flip chip 1033 and the relative position of the opening 1022 depends on the design relationship. For example, when it is expected that the first marking part 1011 and the opening 1022 are aligned to achieve alignment during design, then the criterion for alignment during the alignment operation may be that the first marking part 1011 coincides with the opening 1022 .

In addition, it should be noted that in the alignment operation, in order to confirm alignment and adjust the alignment operation, an electron microscope can be used for observation. The observation can be done in real time according to the needs, or the pictures can be identified and measured after being photographed through an electron microscope. For example, from above the transparent substrate, along the thickness direction of the flip-chip, the region directly opposite to the opening of the film layer is observed using an electron microscope.

The structure, features and effects of the application have been described in detail above based on the embodiments shown in the drawings. The above descriptions are only preferred embodiments of the application, but the application does not limit the scope of implementation as shown in the drawings. Changes made to the idea of the application, or modifications to equivalent embodiments that are equivalent to changes, and still within the spirit covered by the description and illustrations, shall be within the scope of protection of the application.

Claims (13)

1. A flip-chip, characterized in that it comprises: an opposing first chip and a second chip; The first chip is defined with at least a functional area for configuring a first quantum component, and the functional area is also configured with a first marking component; The second chip has a transparent substrate and at least a film layer for configuring the second quantum component; Wherein, the substrate has a front side and a back side distributed along opposite directions, the front side faces the functional area in a face-to-face manner, the film layer is formed on the front side, and the film layer has a surface facing the first Through openings that mark the component and extend in opposing directions. 2. The flip chip according to claim 1, wherein the opening has the same shape as the first marking part; And/or, the first marking component is columnar; And/or, there are multiple first marking components, each of which is a cylinder, and each first marking component has a different diameter. 3. The flip chip according to claim 1, wherein the first marking part and the opening are respectively cross-shaped. 4. The flip chip according to claim 1, 2 or 3, characterized in that, along the opposing direction, the projected area of the opening on the functional area at least covers the first marking component. 5. The flip chip according to claim 1, further comprising: a second marking feature configured to be aligned with the first marking feature; A second marking feature is formed on the front side of the substrate within the area defined by the opening. 6 . The flip chip according to claim 5 , wherein the first marking part and the second marking part are respectively linear. 7. The flip chip according to claim 6, wherein the number of the first marking components is equal to the number of the second marking components, and they are at least three respectively; Each first marking component is arranged at equal intervals along the first path; The respective second marking components are arranged at equal intervals or at variable intervals along the second path; The first path is parallel to the second path. 8. The flip chip according to claim 7, characterized in that, each second marking component is arranged with variable pitch along the second path; The flip chip defines a first direction and a second direction along a second path and opposite to each other; All the second marking parts are composed of a main part, and first and second sub-parts located on both sides of the main part; The distance between two adjacent first subcomponents along the first direction gradually increases, and the distance between two adjacent second subcomponents along the second direction gradually decreases. 9. The flip chip according to claim 5 or 6, wherein the number of the first marking components is equal to the number of the second marking components, and there are at least two of them. 10. The flip chip according to claim 5, wherein the first marking part and the second marking part are configured in pairs to form an alignment structure component, and the first marking part and the second marking part in the same pair of components The second marking member is a cylinder of the same diameter; The flip chip has at least two groups of alignment structural components, and the cylinders of different groups have different diameters. 11. An alignment method for making a flip chip, characterized in that the alignment method comprises: providing a first chip having a first marking feature; A second chip is provided, having a substrate and a film layer, the substrate is transparent, the film layer is formed on the surface of the substrate and has a predetermined thickness, and the film layer has an opening configured through the thickness direction; The first chip and the second chip are distributed in layers along a preset direction, and the first marking component faces at least part of the opening along the preset direction. 12. The alignment method according to claim 11, further comprising: adjusting the first chip and/or the second chip so that the first marking component is aligned in the preset direction The projection of is located within the opening. 13. The alignment method according to claim 12, wherein the second chip further comprises a second marking part formed on the surface of the substrate, and the second marking part has the same shape as the first marking part , the second marking component is located in the opening; The alignment method further includes a first operation or a second operation; The first operation includes: making the first marking part coincide with the second marking part along a preset direction; The second operation includes: making one of the first marking part and the second marking part completely covered by the other along a preset direction.

Images