CN115295534A - A Flip Chip and Alignment Method - Google Patents
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Abstract
Description
技术领域technical field
本申请属于量子芯片制备领域,具体涉及一种倒装芯片和对准方法。The application belongs to the field of quantum chip preparation, and specifically relates to a flip chip and an alignment method.
背景技术Background technique
随着所设计的量子芯片中的量子比特数目的不断增加,刻蚀在量子芯片上的内容(各种线路、元件等)也越来越多。因此,单个芯片的设计方案已经很难满足要求。面对这样的现状,倒装焊工艺的使用越来越迫切。在基于倒装焊的超导量子芯片中,顶层芯片倒装压合在底层芯片上,并且二者通过铟柱进行信号连接以及共地。As the number of qubits in the designed quantum chip continues to increase, more and more content (various circuits, components, etc.) are etched on the quantum chip. Therefore, the design scheme of a single chip has been difficult to meet the requirements. Faced with such a situation, the use of flip-chip welding technology is becoming more and more urgent. In flip-chip-based superconducting quantum chips, the top-layer chip is flip-chip-bonded on the bottom chip, and the two are connected for signal and common ground through indium pillars.
倒装焊工艺的使用会存在一个问题:双层芯片距离太近(例如在微米尺度),两层芯片正面重合的部分没有办法进行观察(原因在于:芯片衬底不透光、芯片表面具有不透光的用于制作各种线路、器件的金属或电介质层),因此就无法判断这部分区域的相关制作工艺水平,包括对准情况。There will be a problem in the use of the flip-chip welding process: the distance between the double-layer chips is too close (for example, on the micron scale), and the overlapping part of the front of the two-layer chips cannot be observed (the reason is that the chip substrate is opaque and the chip surface is opaque. Light-transmitting metal or dielectric layer used to make various circuits and devices), so it is impossible to judge the relevant manufacturing process level of this part of the area, including the alignment situation.
在这种无法用电子显微镜观察芯片的情况下,通常最好的办法便是电学性能测试。即通过测试线路的通断来判断芯片的好坏,或者提前在芯片中设计测试结构,通过测试结构来判断工艺水平。In cases where it is not possible to observe the chip with an electron microscope, electrical performance testing is usually the best solution. That is to judge the quality of the chip by testing the continuity of the circuit, or design the test structure in the chip in advance, and judge the process level through the test structure.
但是这种测试方式存在一定的局限性,例如测试范围有限、并不能精确定位到出问题的位置和环节。并且对于倒装焊芯片来说,铟柱是重要的一个环节,它起着传输信号、芯片共地、稳固芯片等作用,但是目前却没有很好地办法观察到铟柱的制作情况,也没有办法去测试铟柱的制作工艺水平。However, there are certain limitations in this testing method, such as the limited testing scope and the inability to accurately locate the location and link of the problem. And for the flip chip, the indium column is an important link, it plays the role of transmitting signals, sharing the ground of the chip, stabilizing the chip, etc., but currently there is no good way to observe the production of the indium column, and there is no There is a way to test the manufacturing process level of the indium column.
因此,需要一种更加方便的检测方法,能够快速且有效地检测到芯片的制作情况,并能够利用这种方法进行铟柱的工艺水平测试。Therefore, there is a need for a more convenient detection method, which can quickly and effectively detect the production status of the chip, and can use this method to test the process level of the indium column.
发明内容Contents of the invention
有鉴于此,本申请公开了一种倒装芯片和对准方法,其具有在制作过程中方便地实现对准的特点,并且也因此具有以更高效和简便的手段实现的更高质量。进一步地,此倒装芯片的设计方案,允许对倒转芯片中所使用的铟柱的情况进行考察,并判断铟柱的制作质量或者铟柱对准情况。In view of this, the present application discloses a flip-chip and alignment method, which is characterized by convenient alignment during the manufacturing process, and thus has higher quality achieved in a more efficient and simple manner. Further, the design scheme of the flip chip allows the inspection of the indium pillars used in the flip chip, and the judgment of the manufacturing quality of the indium pillars or the alignment of the indium pillars.
本申请示例的方案,通过如下内容实施。The solutions illustrated in this application are implemented through the following contents.
在第一方面,本申请示例提出了一种倒装芯片。In the first aspect, the present application example proposes a flip chip.
该倒装芯片包括:对置的第一芯片和第二芯片;The flip chip includes: a first chip and a second chip opposite to each other;
第一芯片定义有至少用于配置第一量子部件的功能区,功能区还配置有第一标记部件;The first chip is defined with at least a functional area for configuring the first quantum component, and the functional area is also configured with a first marking component;
第二芯片具有透明衬底和至少用于配置第二量子部件的膜层;The second chip has a transparent substrate and at least a film layer for configuring the second quantum component;
其中,衬底具有沿对置方向分布的正面和背面,正面按照面对面的方式朝向功能区,膜层形成于正面,膜层具有面向第一标记部件的贯穿开口。Wherein, the substrate has a front side and a back side distributed along opposite directions, the front side faces the functional area in a face-to-face manner, a film layer is formed on the front side, and the film layer has a through opening facing the first marking component.
上述倒装芯片中,在第一芯片配置第一标记部件,同时在第二芯片配置透明衬底以及形成于该衬底并且具有开口的膜层。因此在制作倒装芯片的过程中,可以操作第一芯片和第二芯片,从而允许依次经由第二芯片的透明衬底和开口观察位于第一芯片的第一标记部件。In the above-mentioned flip chip, the first marking member is arranged on the first chip, and at the same time, the transparent substrate and the film layer formed on the substrate and having openings are arranged on the second chip. Thus during the fabrication of the flip-chip, the first chip and the second chip can be manipulated, allowing the first marking feature located on the first chip to be observed sequentially through the transparent substrate and the opening of the second chip.
那么,根据观察到的第一标记部件与开口的相对位置关系即可以对第一芯片和第二芯片的对准情况进行评估,从而也能在推测该倒装芯片的质量。Then, the alignment of the first chip and the second chip can be evaluated according to the observed relative positional relationship between the first marking component and the opening, so that the quality of the flip chip can also be estimated.
相应地,当在例如超导量子计算设备中所设计的倒装芯片应用铟柱时,也可以利用该方案对铟柱的制作质量以及对准情况进行评估。Correspondingly, when indium pillars are applied to flip-chips designed in, for example, superconducting quantum computing devices, this solution can also be used to evaluate the fabrication quality and alignment of the indium pillars.
简言之,本申请的上述倒装芯片方案将对准的重要依据由芯片自身提供(而非以电学测量结果为依据),从而能够方便、快捷地进行对准操作以及验证是否对准。In short, the above-mentioned flip-chip solution of the present application provides an important basis for alignment by the chip itself (rather than based on electrical measurement results), so that the alignment operation and verification of alignment can be performed conveniently and quickly.
根据本申请的一些示例,开口与第一标记部件具有相同的形状;和/或,第一标记部件为柱状;和/或,第一标记部件有多个且分别为圆柱体,各个第一标记部件的直径不同。According to some examples of the present application, the opening has the same shape as the first marking component; and/or, the first marking component is columnar; and/or, the first marking component has multiple cylinders, and each first marking Parts have different diameters.
根据本申请的一些示例,第一标记部件和开口分别为十字型。According to some examples of the present application, the first marking part and the opening are respectively cross-shaped.
根据本申请的一些示例,沿对置的方向,开口在功能区的投影区域至少覆盖第一标记部件。According to some examples of the present application, along the opposite direction, the projected area of the opening on the functional area at least covers the first marking component.
根据本申请的一些示例,倒装芯片还包括:被配置为与第一标记部件对准的第二标记部件;第二标记部件形成于衬底的正面、并且位于开口限定的区域内。According to some examples of the present application, the flip chip further includes: a second marking part configured to be aligned with the first marking part; the second marking part is formed on the front side of the substrate and is located in an area defined by the opening.
根据本申请的一些示例,第一标记部件和第二标记部件分别为直线型。According to some examples of the present application, the first marking part and the second marking part are respectively linear.
根据本申请的一些示例,第一标记部件的数量与第二标记部件的数量相等,且分别为至少三个;According to some examples of the present application, the number of the first marking components is equal to the number of the second marking components, and are respectively at least three;
各个第一标记部件沿第一路径等间距排列;Each first marking component is arranged at equal intervals along the first path;
各个第二标记部件沿第二路径等间距或变间距排列;The respective second marking components are arranged at equal intervals or at variable intervals along the second path;
第一路径与第二路径平行。The first path is parallel to the second path.
根据本申请的一些示例,各个第二标记部件沿第二路径变间距排列;According to some examples of the present application, each second marking component is arranged at variable intervals along the second path;
倒装芯片定义有沿第二路径且彼此相反的第一方向和第二方向;The flip chip defines a first direction and a second direction along the second path and opposite to each other;
全部的第二标记部件由主部件、以及位于主部件两侧的第一副部件和第二副部件构成;All the second marking parts are composed of a main part, and first and second sub-parts located on both sides of the main part;
沿第一方向的相邻两第一副部件的间距逐渐增加,沿第二方向的相邻两第二副部件的间距逐渐减小。The distance between two adjacent first subcomponents along the first direction gradually increases, and the distance between two adjacent second subcomponents along the second direction gradually decreases.
根据本申请的一些示例,第一标记部件的数量与第二标记部件的数量相等,且分别为至少两个。According to some examples of the present application, the number of the first marking components is equal to the number of the second marking components, and they are at least two respectively.
根据本申请的一些示例,第一标记部件和第二标记部件成对配置形成对位结构组件,且同一对中的第一标记部件和第二标记部件是直径相同的圆柱体;According to some examples of the present application, the first marking component and the second marking component are configured in pairs to form an alignment structural component, and the first marking component and the second marking component in the same pair are cylinders with the same diameter;
倒装芯片具有至少两组对位结构组件,且不同组的圆柱体的直径不同。The flip chip has at least two sets of alignment structural components, and the cylinders of different sets have different diameters.
在第二方面,本申请示例提出了一种用于制作倒装芯片的对准方法。对准方法包括:In a second aspect, the present application exemplarily proposes an alignment method for manufacturing a flip chip. Alignment methods include:
提供第一芯片,具有第一标记部件;providing a first chip having a first marking feature;
提供第二芯片,具有衬底和膜层,衬底是透明的,膜层形成于衬底表面且具有预设厚度,膜层具有沿厚度方向贯穿配置的开口;A second chip is provided, having a substrate and a film layer, the substrate is transparent, the film layer is formed on the surface of the substrate and has a preset thickness, and the film layer has an opening configured through the thickness direction;
使第一芯片和第二芯片沿预设方向层状分布、且第一标记部件沿预设方向正对开口的至少部分。The first chip and the second chip are distributed in layers along a preset direction, and the first marking component faces at least part of the opening along the preset direction.
根据本申请的一些示例,对准方法还包括:调整第一芯片和/或第二芯片,以使第一标记部件沿预设方向的投影位于开口之内。According to some examples of the present application, the alignment method further includes: adjusting the first chip and/or the second chip so that the projection of the first marking component along a preset direction is located within the opening.
根据本申请的一些示例,第二芯片还包括形成于衬底表面的第二标记部件,第二标记部件具有与第一标记部件相同的形状,第二标记部件位于开口内;According to some examples of the present application, the second chip further includes a second marking part formed on the surface of the substrate, the second marking part has the same shape as the first marking part, and the second marking part is located in the opening;
对准方法还包括第一操作或第二操作;The alignment method further includes a first operation or a second operation;
第一操作包括:使第一标记部件沿预设方向与第二标记部件重合;The first operation includes: making the first marking part coincide with the second marking part along a preset direction;
第二操作包括:使第一标记部件和第二标记部件中的一者沿预设方向被另一者完全覆盖。The second operation includes: making one of the first marking part and the second marking part completely covered by the other along a preset direction.
有益效果:Beneficial effect:
与现有技术相比,本申请示例的倒装芯片通过在其中的一层芯片中配置标记部件,同时在与之相邻的另一层芯片中选择透明衬底并且在衬底配置具有开口的膜层。标记部件还对应于膜层的开口。因此,在制作倒装芯片时可以从透明衬底侧,通过开口对标记部件进行观察。根据观察到的标记部件与开口的分布情况,进而可以推断获得倒装芯片的对位情况,相应地也能反映倒装芯片的质量。Compared with the prior art, the flip chip example in this application configures marking components in one layer of chips, and at the same time selects a transparent substrate in another layer of chips adjacent to it and configures a transparent substrate with openings in the substrate. film layer. The marking means also correspond to the openings of the film layer. Therefore, the marking member can be observed through the opening from the transparent substrate side during flip chip fabrication. According to the observed distribution of the marking components and the openings, the alignment of the flip chip can be inferred, and accordingly the quality of the flip chip can also be reflected.
附图说明Description of drawings
为了更清楚地说明本申请实施例或现有技术中的技术方案,以下将对实施例或现有技术描述中所需要使用的附图作简单地介绍。In order to more clearly illustrate the technical solutions in the embodiments of the present application or in the prior art, the following briefly introduces the drawings that are required in the description of the embodiments or the prior art.
图1为本申请实施例提供的第一种倒装芯片在一个视角下的结构示意图;FIG. 1 is a schematic structural view of the first flip chip provided by the embodiment of the present application under a viewing angle;
图2为图1的倒装芯片在另一个视角下的结构示意图;Fig. 2 is a structural schematic diagram of the flip chip of Fig. 1 under another viewing angle;
图3为本申请实施例提供的第二种倒装芯片在一个视角下的结构示意图;FIG. 3 is a schematic structural view of the second flip chip provided by the embodiment of the present application under a viewing angle;
图4为本申请实施例提供的第三种倒装芯片在一个视角下的结构示意图;FIG. 4 is a schematic structural view of a third flip chip provided by the embodiment of the present application under a viewing angle;
图5为本申请实施例提供的第四种倒装芯片的结构示意图(其中图二是图一沿A-A面的剖视结构示意图);Figure 5 is a schematic structural view of the fourth flip-chip provided in the embodiment of the present application (Figure 2 is a schematic cross-sectional structural view of Figure 1 along the A-A plane);
图6为本申请实施例提供的第五种倒装芯片的结构示意图;FIG. 6 is a schematic structural diagram of a fifth flip chip provided in the embodiment of the present application;
图7公开了图6的倒装芯片中的第一标记部件和第二标记部件的布局结构示意图;FIG. 7 discloses a schematic diagram of the layout structure of the first marking component and the second marking component in the flip chip of FIG. 6;
图8公开了本申请实施例提供的另一种倒装芯片中单个第一标记部件和单个第二标记部件的三种对准情况的示意图。FIG. 8 discloses a schematic diagram of three alignment situations of a single first marking component and a single second marking component in another flip chip provided by an embodiment of the present application.
图标:101-第一芯片;1011-第一标记部件;102-第二芯片;1021-膜层;1022-开口;103-圆柱标记部件;1033-第二标记部件。Icons: 101-first chip; 1011-first marking component; 102-second chip; 1021-film layer; 1022-opening; 103-cylindrical marking component; 1033-second marking component.
具体实施方式Detailed ways
倒装焊技术是实现扩展量子芯片中所集成的量子比特的数量的一个重要手段。但是由于量子比特的脆弱性—非常容易受到噪声的不利影响—倒装焊技术的应用对其成熟性和一致性要求非常高。然而,就本申请发明人所知,目前的倒装焊技术还无法很好地符合前述之要求。因此,利用倒装焊技术制作的量子芯片需要进行复杂和繁多的测试,以确保其满足设计要求、与设计目标一致。Flip-chip bonding technology is an important means to expand the number of qubits integrated in quantum chips. But due to the fragility of qubits—very susceptible to adverse effects from noise—flip-chip applications require a high degree of maturity and consistency. However, as far as the inventors of the present application know, the current flip-chip technology cannot well meet the aforementioned requirements. Therefore, quantum chips made using flip-chip bonding technology need to undergo complex and numerous tests to ensure that they meet the design requirements and are consistent with the design goals.
具体到超导量子芯片,在当前的实践中,倒装焊技术需要使用到铟柱作为相邻层芯片之间的互连结构。并且铟柱还可以选择性地被配置为支撑上下层芯片,或者用以将一些线路(例如各种传输线;读取总线)或元器件异面地分布到上下层芯片。Specific to superconducting quantum chips, in current practice, flip-chip bonding technology needs to use indium pillars as the interconnection structure between adjacent layers of chips. And the indium column can also be selectively configured to support the upper and lower chips, or to distribute some lines (such as various transmission lines; read bus) or components to the upper and lower chips in different planes.
因此,当铟柱发生倾斜情况,或者其需要连接的上下层结构未准确地连接时,都将导致各种线路和元器件的潜在失效。换言之,在应用倒装焊技术时,需要特别考察铟柱的对准情况。但是正如在前文所提及的那样,在芯片中,尤其是量子芯片中倒装的上下层芯片之间的距离短,难以直接地观察到在倒装芯片中的铟柱的姿态和结构、对准情况。Therefore, when the indium column is tilted, or the upper and lower structures that it needs to connect are not connected accurately, it will lead to potential failure of various circuits and components. In other words, when applying the flip chip technology, it is necessary to pay special attention to the alignment of the indium pillars. However, as mentioned above, in a chip, especially in a quantum chip, the distance between the flip-chip upper and lower chips is short, so it is difficult to directly observe the posture and structure of the indium column in the flip-chip, and the standard situation.
基于这样的现状,一种可以尝试的方案是在设计芯片时,配置对应的测试电路结构,通过进行电学测量,获得相应的测量响应数据,进而由此响应数据分析铟柱的潜在问题。Based on this situation, one possible solution is to configure the corresponding test circuit structure when designing the chip, and obtain the corresponding measurement response data through electrical measurement, and then analyze the potential problems of the indium column based on the response data.
然而,可以预见地,由于需要在芯片中配置测量电路结构,因此,如何设计该测量电路结构以及如何将测量电路对芯片的不利影响降到更小是一个重要的问题。此外,由于额外地配置了测量电路结构,其必然会占用芯片的有限空间,从而可能导致芯片的可扩展性在一定程度上受限。However, it is foreseeable that since the measurement circuit structure needs to be configured in the chip, how to design the measurement circuit structure and how to minimize the adverse impact of the measurement circuit on the chip is an important issue. In addition, due to the additional configuration of the measurement circuit structure, it will inevitably occupy a limited space on the chip, which may lead to limited scalability of the chip to a certain extent.
有鉴于此,经过实践研究,发明人于本申请中提出了一种对铟柱的对准情况进行确认的方案;其将在后文被详述。需要指出的是,虽然前文主要以超导量子芯片中使用铟柱的倒装结构进行说明。但是这并非意在限制本申请示例的方案只能适用于超导量子芯片中的铟柱(或其他部件,例如硅通孔结构等)的对准情况的考察。In view of this, after practical research, the inventor proposed a scheme for confirming the alignment of the indium pillars in this application; it will be described in detail later. It should be pointed out that although the above description is mainly based on the flip-chip structure using indium pillars in the superconducting quantum chip. However, this is not intended to limit the solution exemplified in the present application to the investigation of the alignment of indium pillars (or other components, such as TSV structures, etc.) in superconducting quantum chips.
实际上,本申请示例的方案还可以适用于其他类型的量子芯片的倒装互连操作,以便对需要考虑对准情况的部件的确认。并且更进一步而言,对于非量子芯片的常规芯片/经典芯片中倒装技术方案应用过程中的对准情况的确认,本申请示例方案同样使用。In fact, the solutions exemplified in this application can also be applied to the flip-chip interconnection operations of other types of quantum chips, so as to confirm the components that need to consider the alignment. And further, for the confirmation of the alignment of the non-quantum chip conventional chip/classical chip during the application process of the flip-chip technology solution, the example solution of the present application is also used.
大体上,本申请示例的方案基于这样的考虑被提出:In general, the scheme of the example in this application is proposed based on the following considerations:
在倒装结构中,选择通过直接观察(考虑到芯片的尺寸,通常选择以电子显微镜进行观察)的方式确认上下层芯片是否对准。并且相应地,配置用于识别是否对准的标记,以及用于实施观察的可视区域。In the flip-chip structure, choose to confirm the alignment of the upper and lower chips by direct observation (considering the size of the chip, usually with an electron microscope). And correspondingly, a mark for identifying alignment and a visible area for observation are configured.
作为区别,在既有的倒装结构中,由于各层芯片的衬底以及其上的元器件和线路是非透光(即不可观察/非可视),因此选择如前述使用测量电路结构进行对准情况的确认。而本申请则选择使用能够提供可视区域的透明衬底,再将待观察区域配置为不设置线路或者元件器,从而避免遮挡,以允许进行观察。As a difference, in the existing flip-chip structure, since the substrates of each layer of chips and the components and circuits on them are non-transparent (that is, non-observable/non-visible), we choose to use the measurement circuit structure as mentioned above to perform the test. confirmation of the status. However, this application chooses to use a transparent substrate that can provide a visible area, and then configures the area to be observed so that no lines or components are provided, so as to avoid occlusion and allow observation.
因此,在示例中提出了应用上述对准方案的倒装芯片。该对准方案的倒装芯片包括第一芯片101和第二芯片102。并且第一芯片101和第二芯片102按照层状结构分布而相互面对面配置,即对置。在本申请示例中,第一芯片101被描述为下层芯片,第二芯片102被描述为上层芯片。Therefore, a flip chip applying the above-mentioned alignment scheme is proposed in an example. The flip chip of this alignment scheme includes a
对于量子芯片,例如超导量子芯片,其中的第一芯片101具有衬底(例如硅衬底或蓝宝石衬底;透明或非透明皆可),并且在衬底的表面(面向第二芯片102)配置各种结构,例如是量子线路和器件。类似地,第二芯片102也具有衬底(透明材质,以便提供可视区域进行观察;本申请示例中为蓝宝石),且衬底的表面(面向第一芯片101)也可以按需要配置各种量子线路和器件。For a quantum chip, such as a superconducting quantum chip, the
作为区别描述,在第一芯片101中配置的量子线路和器件可以被描述为第一量子部件,而在第二芯片102中配置的量子线路和器件可以被描述为第二量子部件。这些量子部件例如是信号线,例如共面波导传输线,或者共面波导谐振腔,可以作为读取腔,或者读取总线,或者各种控制线等等,或者各种电容元件等。As a distinction description, quantum circuits and devices configured in the
基于方便芯片与外界各种测控系统连接考虑,上述的底层芯片通常具有比上层芯片更大的平面尺寸,即沿着二者的对置方向,上层芯片的投影在下层芯片仅占一定的区域,而通常并非全部的下层芯片的表面区域。因此,下层芯片的与上层芯片在对置方向的投影重合区域可以被描述为功能区。由此,前述第一量子部件尽数被设置到该功能区内,而在非功能区/功能区之外则可以配置线路的焊盘,以便进行诸如引线键合的连接。Based on the consideration of facilitating the connection between the chip and various external measurement and control systems, the above-mentioned bottom chip usually has a larger plane size than the upper chip, that is, along the opposite direction of the two, the projection of the upper chip only occupies a certain area on the lower chip. And usually not all of the surface area of the underlying chip. Therefore, the overlapping area of the projection of the lower chip and the upper chip in the opposite direction can be described as a functional area. Thus, all the aforementioned first quantum components are arranged in the functional area, and pads of circuits can be arranged outside the non-functional area/functional area for connection such as wire bonding.
进一步地,作为对准的识别对象,在第一芯片101的功能区还配置了第一标记部件1011,例如可以通过蒸发镀膜(示例性地如电子束蒸发镀膜)、化学气相沉积、分子束外延、溅射等方式进行制作。第一标记部件1011的材质可以是各种金属材料;或者其他根据需要的材料,例如氧化物等。该第一标记部件1011可以作为制作倒装芯片时,上下层芯片对准的一个重要依据。Further, as an identification object for alignment, a
并且,作为与该第一标记部件1011配合的结构,在第二芯片102配置一个窗口,其用于在上下层芯片对置的方向观察第一标记部件1011。示例中,第二芯片102选择使用透明衬底,然后在其表面配置膜层1021,例如可以是铝膜或者铝膜层,可以用于在超导量子芯片中构建诸如读取总线、读取谐振腔、耦合结构等等。Furthermore, as a structure cooperating with the
为了方便描述和清楚地阐明,该透明衬底具有沿对置方向(一些示例中可以描述为倒装芯片的厚度方向)分布的正面(面向第一芯片101)和背面(背离第一芯片101)。基于此,透明衬底的正面按照面对面的方式朝向第一芯片101的功能区;对应地,膜层1021形成于第二芯片102的正面,同时,膜层1021还具有面向第一标记部件1011且沿对置方向延伸的贯穿开口1022。For the convenience of description and clarity, the transparent substrate has a front side (facing the first chip 101 ) and a back side (facing away from the first chip 101 ) distributed along the opposite direction (in some examples, it can be described as the thickness direction of a flip chip). . Based on this, the front side of the transparent substrate faces the functional area of the
作为一种区分,现有的倒装芯片中,上下层芯片一般都是采用的非透明衬底,并且其表面还具有诸如介质膜或者金属膜层非透明膜层—可以用于形成各种功能性的器件或结构,如传输线或作为电容板等。在这样的情况下,无法提供可视区域以及也不能够实现观察的可能。而本申请中在选择使用透明衬底制作第二芯片102的同时,还将该透明衬底的表面的非透光的膜层1021设置一个开口1022,从而允许通过透明衬底以及该开口1022向第一芯片101实施观察。其中的开口1022可以通过使用掩膜对膜层1021进行选择性的光刻操作而获得,在此不予赘述。As a distinction, in the existing flip chips, the upper and lower chips are generally non-transparent substrates, and their surfaces also have non-transparent films such as dielectric films or metal films—which can be used to form various functions. Sexual devices or structures, such as transmission lines or as capacitive plates, etc. In such a case, no viewing area is provided and no viewing possibilities are possible. In this application, while choosing to use a transparent substrate to make the
在以上述方式构建第一芯片101和第二芯片102之后,即可将第一芯片101和第二芯片102进行倒装互连,然后从第二芯片102的背面观察第一芯片101上的第一标记部件1011。由此可以根据第一标记部件1011和开口1022的预设的对准关系,以及实际观察时二者的对位关系对两层芯片的对准情况进行确定。After constructing the
示例性地,开口1022可以配置为十字型结构,相应地,第一标记部件1011也可以配置为十字型结构。二者还可以具有相同的结构尺寸,并且因此,当二者重合时可以认为上下层芯片精确地对准,例如参阅图1和图2。或者,在另一些示例中,在开口1022与第一标记部件1011具有相同的十字型的形状的情况下,开口1022还具有大于第一标记部件1011的尺寸。因此,当进行观察时,第一标记部件1011可以是位于开口1022所限定的范围之内的;作为示例,仅展示在俯视角度的结构示意图且如图3所示。Exemplarily, the
其他示例中,开口1022和第一标记部件1011还可以选择为直线型、或者圆形、或者多边形等方式进行构造。例如,二者都选择为等直径的圆形,则上下层芯片精确对位可以为二者重合;或者二者是直径不同的圆形,则二者精确对位可以为圆心重合。可以知晓,在这些开口1022和第一标记部件1011重合的示例中,沿上下层芯片对置的方向,第二芯片102的开口1022在第一芯片101的功能区的投影区域是完全覆盖并重合于第一标记部件1011,如图2。在其他非重合的示例中,第二芯片102的开口1022在第一芯片101的功能区的投影区域是完全覆盖第一标记部件1011,并且还扩展到第一标记部件1011之外;如图3。In other examples, the
应当理解,开口1022和第一标记部件1011在观察视角下的对位形式和结构,与第一芯片101和第二芯片102对准结果可以根据预先设计的模式进行对应,并不以上述记载方式为限制。It should be understood that the alignment form and structure of the
虽然上文中给出了多个实例,且这些实例中开口1022和第一标记部件1011具有相同的形状,但是在其他示例中,开口1022和第一标记部件1011也可以具有不同的形状。例如,开口1022为矩形,而第一标记为圆形;则上下层芯片精确对准可以是圆形位于矩形内,且矩形四边与圆形相切。Although a number of examples have been given above in which the
此外,上述示例的第一标记部件1011可以选择以平面结构(具有在第一芯片101表面内的尺寸;例如长度和宽度等)进行构造,因此,位于第一芯片101的第一标记部件1011,通常地远离第二芯片102。在另一些示例中,第一标记部件1011还可以选择为柱状结构,因此其还具有在第一芯片101表面内的尺寸之外的另一尺寸,即高度。相应地,第一标记部件1011可以配置为圆柱体或棱柱体等。因此,部分示例中,开口1022可以配置为矩形,而第一标记部件1011配置为圆柱体/横截面为圆形。因此,上下层芯片对准可以是圆柱体的正投影位于开口1022内。In addition, the
从数量上而言,圆柱形或其他形状的第一标记部件1011的数量可以是一个,也可以是多个。以图4所示,第一标记部件1011有三个。该三个第一标记分别配置到第一芯片101,并且三者为直径各自均不同的圆柱形;其他示例中也可以具有相同的直径。换言之,当存在多个第一标记部件1011,且各个第一标记部件1011是圆柱形时,各个第一标记部件1011的直径可以是不同的。例如全部的第一标记部件1011的圆柱直径均不同,或者部分相同,而剩余的不同。In terms of quantity, the number of cylindrical or other
上述示例中,主要以在第一芯片101配置对准用部件(即第一标记部件1011)为例进行说明,但是,在部分示例中,还可以选择将配置于第一芯片101的第一标记部件1011替换配置为由第一圆柱和第二圆柱构成,并且该两圆柱分别配置到第一芯片101和第二芯片102。或者,部分第一标记部件1011配置为圆柱且位于第一芯片101;同时另一些第一标记部件1011被替换为分别配置在第一芯片101和第二芯片102的第一圆柱和第二圆柱(两圆柱可以在端部接触,从而形成圆柱标记部件103);请参阅图5。In the above example, the
类似地,后文将描述第一芯片101和第二芯片102分别配置对准部件—第一标记部件1011和第二标记部件1033—的示例,因此,第一标记部件1011和第二标记部件1033可以成对配置形成对位结构组件。对位结构组件的数量可以为一对或多对,同一对中的部件尺寸如直径可以相同,不同对的部件的尺寸如直径可以相异。示例性地,同一对的组件中的第一标记部件1011和第二标记部件1033是直径相同的圆柱体。可以知晓,这样示例中的圆柱体构造形式的第一、第二标记部件1033可以认为是前述第一圆柱和第二圆柱。如此,二者在倒装芯片中上下对位(例如二者同为圆柱体,两者用于通过二者的轴线,以共轴的方式进行上下对位),用于通过二者的对位情况判断上下层的芯片是否精确地对准了。Similarly, an example in which the
对应于上述第一芯片101和第二芯片102分别配置标记部件的实例,第二标记部件1033形成于第二芯片102的衬底的正面,并且还位于衬底的表面的膜层1021所开设的开口1022而限定的区域内。对于两个标记部件的形状,如同前述配置第一标记部件1011类似,二者通常选择以相同的形状(可以具有不同的尺寸;当然也可以具有相同的尺寸)的方式进行配置,从而可以降低二者对位的实施难度。前述内容给出了圆柱体的示例,在另一些示例中,二者还可以被配置为条状结构、窄带状结构等等。例如可以是各种线路结构,示例性地为共面波导传输线。Corresponding to the above-mentioned example where the
作为具体且可替代的说明,下面就第一标记部件1011和第二标记部件1033做具体且非限制性的说明。As a specific and alternative description, the
示例中,第一标记部件1011和第二标记部件1033分别为直线型;例如,具有相同的宽度的横截面为矩形的带状结构。在这些示例中,如前述,第一标记部件1011和第二标记部件1033是成对地出现并被合适地配置的;那么由此可知,第一标记部件1011和第二标记部件1033的数量例如是相等的。In an example, the
如前述,成对的标记部件可以是一对、两对,三对,甚至更多对。具有多对标记部件方案,可以使对位操作时的精度更高,避免配置一对时因为制作标记部件时出现的偏差所导致对位结果与预期结果不一致。As mentioned above, the paired marking components can be one pair, two pairs, three pairs, or even more pairs. With the multi-pair marking parts scheme, the accuracy of the alignment operation can be higher, and the alignment result is inconsistent with the expected result caused by the deviation in the production of the marking parts when configuring a pair.
从排列方式而言,对于这些成对出现的标记部件,其排列方式可以是任意地被人为选择的,以实际所需的对准方式匹配为选择依据。例如标记部件为直线型,则其可以水平布置,或者竖直布置,或者相对于竖直方向或水平方向倾斜地布置。In terms of arrangement, for these marking components that appear in pairs, the arrangement can be selected arbitrarily, based on the matching of the actual required alignment. For example, if the marking component is linear, it can be arranged horizontally, vertically, or inclined relative to the vertical or horizontal direction.
以第一标记部件1011和第二标记部件1033按照至少三对的方式配置为例。示例性地,位于第一芯片101的各个第一标记部件1011可以选择沿第一路径等间距排列;相应地,位于第二芯片102的各个第二标记部件1033沿第二路径等间距或变间距排列;其中,第一路径与第二路径平。Take the configuration of at least three pairs of the
以图6和图7所示,各个直线型的第一标记部件1011在竖直方向延伸布局,且全部的第一标记部件1011沿水平方向等间距排列;同时,各个直线型的第二标记部件1033在竖直方向延伸布局,并且全部的第二标记部件1033沿水平方向等间距排列。As shown in Figure 6 and Figure 7, each linear
特别地,如图7所示,9个第一标记部件1011在水平方向等间距排列;同时9个第二标记部件1033在水平方向等间距排列。并且,其中两类标记部件按照这样的方式布置:In particular, as shown in FIG. 7 , nine
位于中间位置的第一标记部件1011和第二标记部件1033预期是在对准情况下对齐的。The
进一步地,按照图7所示方位,由位于中间位置至右侧,上下分布的第一标记部件1011和第二标记部件1033预期是在芯片对准情况下水平方向存在偏移;图7中,依次各个存在诸如2-、4-、6-、8-的偏移。类似地,按照图7所示方位,由位于中间位置至左侧,上下分布的第一标记部件1011和第二标记部件1033预期是在芯片对准情况下水平方向存在偏移;图7中依次各个存在诸如2+、4+、6+、8+的偏移。Further, according to the orientation shown in FIG. 7 , from the middle position to the right side, the
因此,利用图7所示的结构设计,可以判断芯片是否对准,以及偏移方向和偏移的距离。例如,如果中间的第一标记部件1011和第二标记部件1033上下对齐,则表示已经对准。如果2-所表示的标记部件上下对齐,则可以表示上层芯片向右侧偏移了2个单位,等等。Therefore, using the structural design shown in FIG. 7 , it is possible to judge whether the chips are aligned, as well as the offset direction and offset distance. For example, if the
进一步地,基于考察上下层芯片是否存在相对的角度偏差需要,可以在分别在第一芯片101和第二芯片102上各配置一个标记部件。例如,第一芯片101配置直线型的一个第一标记部件1011,第二芯片102配置直线型的一个第二标记部件1033;该两个标记部件可以是相同形状和尺寸。因此,上下两个芯片可以存在水平偏移或者角度偏移两种未对准的情况。Further, based on the need to investigate whether there is a relative angle deviation between the upper and lower chips, a marking component can be respectively arranged on the
例如,如图8所示,其中B图表示对准,A图表示水平偏移,C图表示角度偏移。图8中以第一标记部件1011和第二标记部件1033非重合的对位方式描述了三种对准情况;在其他的示例中,当第一标记部件1011和第二标记部件1033是按照重合的对位方式进行设计,那么对准情况也可以存在如上述的水平偏移、角度偏移以及竖直偏移等情况。For example, as shown in Fig. 8, where B diagram represents alignment, A diagram represents horizontal offset, and C diagram represents angular offset. In Fig. 8, three alignment situations are described in the non-overlapping alignment mode of the
作为图6所示方案的调整示例,各个第二标记部件1033也可以沿第二路径变间距排列。为了说明变间距排列的方式,定义倒装芯片具有沿第二路径且彼此相反的第一方向和第二方向,例如水平向左和水平向右。并且,位于第二芯片102的全部第二标记部件1033被分组为主部件、以及位于主部件两侧的第一副部件和第二副部件。那么。在此基础上,沿第一方向排列的相邻两第一副部件的间距可以是逐渐增加的,且同时沿第二方向排列的相邻两第二副部件的间距时逐渐减小的。As an adjustment example of the scheme shown in FIG. 6 , each
基于上述示例的倒装芯片的应用实例,一种倒装芯片在制作过程中对相邻层的芯片的对准方法可以通过如下方式实施:Based on the application example of the flip chip in the above example, a method for aligning chips on adjacent layers during the manufacturing process of the flip chip can be implemented in the following manner:
步骤S101、提供第一芯片101和第二芯片102。Step S101 , providing a
该两芯片可以分别通过在衬底上采用半导体集成电路中的各种工艺制作各种形状、结构的薄膜、线路、元件等。The two chips can be manufactured with various shapes and structures of thin films, circuits, components, etc. on the substrate by using various processes in semiconductor integrated circuits.
其中第一芯片101的衬底(可以是蓝宝石或硅)或衬底表面的薄膜之上配置了第一标记部件1011。第二芯片102的衬底采用透明材料,在超导量子芯片领域中通常可以选择为蓝宝石。第二芯片102表面还配置有可以用于形成元件(例如超导量子芯片中的共面波导传输线、谐振器等)的膜层1021。并且,进一步地,该膜层1021还在被选择的区域沿厚度方向配置了开口1022。该开口1022允许在第一芯片101和第二芯片102对置时,透过第二芯片102的透明衬底,再经由开口1022观察到位于第一芯片101中的第一标记部件1011。Wherein the
步骤S102、使第一芯片101和第二芯片102沿预设方向层状分布、且第一标记部件1011沿预设方式进行对位。Step S102 , distributing the
本步骤中,通常可以选择将第一芯片101配置到各种基座、平台或者支架等结构上水平地放置,以便使其保持稳定的姿态。然后通过使第二芯片102覆盖到第一芯片101表面,并且通过对第二芯片102进行适应性的位移(水平和/或竖直方向;其中在水平方向可以是左、右、前、后方向进行平移运动,或者以选择的竖直方向为轴进行旋转运动),使得两个芯片彼此接近到足以实施倒装焊的距离,同时二者还对准以便两者之间的元器件等准确地接触而能够实现电连接、信号导通等。In this step, generally, the
上述示例中,以第一芯片101作为固定目标,第二芯片102为移动目标,通过将第一芯片101固定后,再位移第二芯片102使其二者对准。在其他的示例中,也可以同步地移动第一芯片101和第二芯片102。In the above example, the
此外,上述描述的第一标记部件1011沿预设方式进行对位可以是:将第一标记部件1011正对开口1022的至少部分,或者,使第一标记部件1011在两芯片对置方向的投影位于开口1022之内。In addition, the above-described alignment of the
当在倒装芯片中还具有第二标记部件1033时,对位方式还可以是:该第二标记部件1033位于第二芯片102的衬底表面且在开口1022内。如两标记部件具有相同的形状时,则对位还可以是使第一标记部件1011与第二标记部件1033重合(当二者尺寸相同时),或者使第一标记部件1011和第二标记部件1033中的一者沿预设方向被另一者完全覆盖(当二者尺寸不同时)。When there is a
应当理解,第一芯片101和第二芯片102的对位还可以是其他方式和判断标准;具体地可以根据设计倒装芯片时所预期的第一标记部件1011或者进一步选择配置的第二标记部件1033以及开口1022的相对位置设计关系而定。例如,当设计时预期第一标记部件1011和开口1022重合即达到对准,那么进行对位操作时对准的判断标准可以是第一标记部件1011与开口1022重合。It should be understood that the alignment of the
此外,需要说明的是,对于在对位操作中,为了确认是否对准以及调整对位操作,可以使用电子显微镜进行观察。根据需要其中的观察可以是实时地进行观察,或者通过电子显微镜拍照后对照片进行识别、测量等。例如,从透明衬底之上,沿着倒装芯片的厚度方向垂直地对膜层开口所正对的区域使用电子显微镜进行观察。In addition, it should be noted that in the alignment operation, in order to confirm alignment and adjust the alignment operation, an electron microscope can be used for observation. The observation can be done in real time according to the needs, or the pictures can be identified and measured after being photographed through an electron microscope. For example, from above the transparent substrate, along the thickness direction of the flip-chip, the region directly opposite to the opening of the film layer is observed using an electron microscope.
以上依据图式所示的实施例详细说明了本申请的构造、特征及作用效果,以上所述仅为本申请的较佳实施例,但本申请不以图面所示限定实施范围,凡是依照本申请的构想所作的改变,或修改为等同变化的等效实施例,仍未超出说明书与图示所涵盖的精神时,均应在本申请的保护范围内。The structure, features and effects of the application have been described in detail above based on the embodiments shown in the drawings. The above descriptions are only preferred embodiments of the application, but the application does not limit the scope of implementation as shown in the drawings. Changes made to the idea of the application, or modifications to equivalent embodiments that are equivalent to changes, and still within the spirit covered by the description and illustrations, shall be within the scope of protection of the application.
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