CN115295524B

CN115295524B - Through-silicon-via interconnection structure and quantum computer

Info

Publication number: CN115295524B
Application number: CN202211220570.2A
Authority: CN
Inventors: 请求不公布姓名
Original assignee: Origin Quantum Computing Technology Co Ltd
Current assignee: Benyuan Quantum Computing Technology Hefei Co ltd
Priority date: 2022-10-08
Filing date: 2022-10-08
Publication date: 2023-02-03
Anticipated expiration: 2042-10-08
Also published as: CN115295524A

Abstract

The application discloses through-silicon-via interconnection structure and quantum computer belongs to quantum chip manufacturing field. The through silicon via interconnection structure comprises a transparent substrate, a functional layer and a through silicon via interconnection. Wherein the functional layer and the through-silicon via interconnect are both attached to the transparent substrate. The functional layer is bonded to the front and/or rear surface of the substrate, and the interconnection is arranged through a through-hole of the substrate in the viewing window region. The transparent window and the through hole have certain gaps, so that the structure that the through hole is positioned in the through hole of the chip can be observed from the transparent window area from the surface, and the quality of the through silicon via interconnection can be conveniently evaluated through inspection.

Description

Through-silicon-via interconnection structure and quantum computer

Technical Field

The application belongs to the field of quantum chip preparation, and particularly relates to a through silicon via interconnection structure and a quantum computer.

Background

In the preparation process of the quantum chip, due to the increase of the number of quantum bits in the chip, the flip-chip bonding process is often selected to convert the planar structure of the chip into a three-dimensional structure, so that the utilization rate of unit area is improved, and the area of the chip is further reduced.

The flip chip bonding process requires that bonding metal layers are respectively formed on the upper chip and the base chip, and then the upper chip and the base chip are bonded together by pressure to form a flip chip.

However, with the further increase of the number of quantum bits, it is gradually difficult for the conventional flip-chip bonding process to meet the requirements of more and more bit contents (more and more bit capacitors, resonant cavities, buses, control lines, and other devices). However, when the TSV technology is applied to chip fabrication, considering the maturity of the technology, it is necessary to investigate whether the TSV is successfully fabricated and the fabrication quality after the TSV is fabricated.

Currently, testing by measuring the electrical characteristics of through-silicon vias is mostly used, but such a solution requires the fabrication of various measurement lines and the like, which in turn potentially increases the quality requirements of these lines. Therefore, a solution capable of conveniently evaluating the quality of the through silicon via is needed.

Disclosure of Invention

In view of the above, the present application discloses a through silicon via interconnection structure and a quantum computer. The scheme identifies whether the through silicon via interconnection has physical defects such as breakage or not by observing the through silicon via interconnection, so that the problem that an additional configuration line is needed when the quality of the through silicon via is evaluated by an electrical measurement mode at present can be replaced.

The scheme exemplified in the present application is implemented as follows.

In a first aspect, examples of the present application propose a through silicon via interconnect structure comprising:

a transparent substrate having a front surface and a back surface which are oppositely arranged in a thickness direction, and a through hole which passes through the substrate from the front surface to the back surface, the substrate defining an observation window region which surrounds the through hole;

the functional layer is formed on the front surface and/or the back surface, and avoids and exposes the observation window area; and

a through silicon via interconnect formed in the via.

In the through silicon via interconnection structure, a transparent substrate is used and a viewing window region is defined. A through hole is further penetratingly provided in this region. Accordingly, a through silicon via interconnect is configured based on such a via. Further, as a functional layer in which various lines or elements are arranged, it avoids the aforementioned region. Then, based on the through-silicon-via interconnection structure, the part of the through-silicon-via, which is located inside the substrate, can be observed from the front side or the back side of the substrate, so that the quality of the interconnection can be evaluated and determined according to the observed result.

According to some examples of the application, the transparent substrate is a sapphire substrate.

According to some examples of the present application, the functional layer is one or more layers; and/or the functional layer is a metal layer; and/or the functional layer is made of a superconducting material.

According to some examples of the present application, the through-silicon via interconnect is a super-pillar; and/or the through silicon via interconnect is a hollow post.

According to some examples of the present application, the through silicon via interconnect extends to the front side at one end and to the back side at another end.

In a second aspect, examples of the present application propose a through silicon via interconnect structure. It comprises the following steps:

the first chip is provided with a first transparent window, the first transparent window provides an observation path from the front surface to the back surface of the first chip, and the first transparent window is also provided with a through hole extending along the direction from the front surface to the back surface in a penetrating way;

a second chip opposed to the first chip in a front-facing manner, the second chip being flip-chip interconnected with the first chip by flip-chip interconnections; and

the through silicon via interconnection is filled in the through hole;

there is a gap between the through silicon via interconnect and an edge profile of the first transparent window at the back side of the first chip.

According to some examples of the present application, the through silicon via interconnect is hollow; and/or the through silicon via interconnect is cylindrical.

According to some examples of the present application, the through silicon via interconnect is columnar and has a first end and a second end; the first end extends to the front face and/or the second end extends to the back face.

According to some examples of the application, the first end and/or the second end are each annular.

According to some examples of the present application, the through silicon via interconnect comprises a superconducting material.

According to some examples of the present application, the second chip has a second transparent window, the second transparent window being directly opposite the first transparent window.

According to some examples of the application, the edge profile of the first transparent window at the back side is rectangular or circular.

According to some examples of the present application, the orthographic projection of the first transparent window on the second chip is located within the second transparent window; and/or the edge outline of the second transparent window is rectangular or circular.

According to some examples of the application, in the area of the first transparent window, a grid is defined on the front side; the grids are formed by criss-cross of warps and wefts, and the intersections of the warps and the wefts are grid points; the through holes are multiple, all the through holes are positioned by the grid points of the grid, and the through holes correspond to the grid points one to one.

According to some examples of the present application, the distance between two adjacent wefts is gradually changed in all wefts; and/or the distance between two adjacent wefts is gradually changed in all warps.

According to some examples of the application, the diameter of each through hole of the same weft is gradual; and/or the diameters of the through holes of the same longitude line are the same.

According to some examples of the present application, a portion of the flip-chip interconnect is positioned within a region of the first transparent window.

In a third aspect, examples of the present application propose a quantum computer comprising a quantum processor implemented based on the through silicon via interconnect structure of the above examples.

Has the advantages that:

in contrast to the prior art, the through-silicon via interconnect structure in the examples of the present application uses a transparent substrate to provide a window area for viewing, and to configure the vias within that area and the interconnects within the holes. While taking into account the various lines and components of the desired configuration, the interconnect structure defines a functional layer that is made up of the source of these lines and components and keeps the functional layer away from the aforementioned window area. Therefore, in the interconnect structure, both ends of the interconnect are naturally exposed, so that it can be observed. Also, due to the design of the transparent substrate and the window region, the portion of the interconnect within the substrate can also be viewed from the surface of the substrate, enabling viewing of the entire interconnect. Through the observation, potential physical defects of the interconnection piece, such as breakage, gaps, surface burrs and the like, can be visually discovered, and further, the corresponding modification and optimization of the manufacturing process are facilitated.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments or the prior art of the present application, the drawings used in the description of the embodiments or the prior art will be briefly described below.

Fig. 1 is a schematic top view structural diagram of a first through silicon via interconnection structure provided in an embodiment of the present application;

FIG. 2 disclosesbase:Sub>A schematic cross-sectional view along the A-A plane in the interconnect structure of FIG. 1;

fig. 3 discloses a schematic view of the viewing pattern at different viewing angles, shown in cross-section in fig. 2;

fig. 4 is a schematic top view of a second through silicon via interconnection structure provided in an embodiment of the present application;

fig. 5 is a schematic structural diagram of a third through silicon via interconnection structure according to an embodiment of the present application;

fig. 6 is a schematic structural diagram of a fourth through silicon via interconnection structure according to an embodiment of the present application;

fig. 7 is a schematic structural diagram of a fifth through silicon via interconnection structure according to an embodiment of the present application.

Icon: 101-a substrate; 102-a film layer; 103-through silicon via interconnect; 104-a viewing window area; 201-a first chip; 202-a second chip; 203-flip chip interconnects; 204-gap.

Detailed Description

In order to conveniently examine the possible problems in the application process of the through silicon via technology, in the example of the application, the inventor proposes a through silicon via interconnection structure. The through silicon via interconnection structure includes a substrate 101, a functional layer (hereinafter, referred to again as an example with a film layer 102) and a through silicon via interconnection 103; and the functional layer and the through-silicon via interconnect 103 are attached to the substrate 101, respectively, see also fig. 1 and 2.

Wherein the substrate 101 is transparent and thus capable of providing a viewing path extending inwardly from a forward or lateral surface thereof. In terms of material, the transparent substrate 101 may be selected as a sapphire substrate, a silicon dioxide substrate, a gallium nitride substrate, or the like. In different usage scenarios, the material of the transparent substrate 101 is selected accordingly, and is not limited to the above examples. For example, when the through-silicon via interconnect structure in the example is applied in a superconducting quantum computer, then the substrate may be a sapphire substrate.

For convenience of description, the substrate 101 is defined to have a front surface and a back surface (or may be described as an upper surface/top surface, a lower surface/bottom surface) distributed along a thickness direction thereof. On this basis, the substrate 101 is provided with through holes along the thickness direction (by means of forms such as plasma etching, laser ablation, etc.); both ends of the through-hole penetrate the front and back surfaces of the substrate 101.

Typically, the through-holes extend in a direction perpendicular to the thickness direction of the substrate 101. Constructing the vias in this manner may reduce the difficulty of fabricating the vias and also facilitate subsequent fabrication of the through-silicon-via interconnects 103 therein. However, this is not intended to limit the through-holes to have to be arranged in a direction perpendicular to the thickness direction of the substrate 101, and in other examples, the through-holes may be arranged obliquely.

In addition, from the structural discussion, the through hole can be a through hole or a hole with a variable inner diameter. For example, the through hole may be a cylindrical hole, or a prismatic hole such as a quadrangular prismatic hole, or the through hole may also be a tapered hole, or the like. Alternatively, the through hole may be formed by two upper and lower trapezoidal holes which are oppositely communicated. In short, the through-holes may be configured in various appropriate structures as needed, and are not particularly limited.

Upon the provision of the through-holes, the substrate 101 also defines a viewing window region 104 surrounding the through-holes, as shown in fig. 1 and 2. It will be appreciated that the viewing window area 104 comprises a first portion located on the front side of the substrate 101, a second portion located within the substrate 101, and a third portion located on the back side of the substrate 101.

The area where the through-holes are located is surrounded by the viewing window area 104. At the same time, there is a suitable distance between the edge profile of the window area and the edge profile of the via, and no other line or component configuration is provided within this distance, allowing observation in this area. In fig. 1, the viewing window area 104 is circular in outline at the edge of the surface of the substrate 101, but it is contemplated that it may be rectangular in other examples, such as square, or other shapes. The edge profile may be limited by, but is not necessarily limited to, the particular form of circuitry and components fabricated on the surface of the substrate 101.

As an example, fig. 3 illustrates a manner of viewing the interconnects disposed at the through-holes from three different angles. Since the physical size of the interconnects is small, for example, on the micrometer or nanometer scale, although the observation is visually represented in fig. 3, the observation may be actually performed by selecting an electron microscope for observation. Further, in addition to the observation from the direction shown in fig. 3, the interconnector may be selectively observed from other viewing angles such as a side surface of the substrate 101, if necessary.

In order to distribute various elements or circuits on the upper and lower surfaces of the substrate 101 in a non-planar manner, a functional layer is optionally provided on one or both of the front and rear surfaces in the interconnect structure. The functional layer may be a superconducting layer (e.g., an aluminum film, a titanium nitride film, etc.) exhibiting superconducting characteristics (zero resistance) at a target operating temperature threshold. Alternatively, the functional layer may be another metal film layer, a dielectric film layer, or an insulating film layer.

In still other examples, the functional layer may be one or more of the above-described film layers, or a combination of two or more of the above-described film layers. Illustratively, the front and back surfaces of the substrate are each provided with a functional layer, based on the need to distribute signal lines to the front and back surfaces of the substrate 101, and the signal lines-for example, coplanar waveguides-are formed by suitable means, such as etching.

It is to be noted that the functional layer needs to be built up so as to avoid the aforementioned surrounding area of the through hole. I.e. the functional layer, avoids the viewing window region 104, thereby leaving the viewing window region 104 exposed. Furthermore, there is a certain clearance 204 between the functional layer and the through hole, as for example indicated in fig. 5 and 6, and depicted and not indicated in fig. 1 to 3.

Further, the through-silicon via interconnection 103 in the interconnection structure may be selectively formed in the through-hole by means of, for example, electroplating, on the basis of the above-described through-hole and functional layer. From its spatial position, the interconnect may be entirely located within the via. Or the interconnection also extends out of the via-hole-both ends of which extend to the surface of the substrate 101; such as one end of the interconnect extending to the front surface, or the other end extending to the back surface, or both. In some examples, when the interconnects extend to the surface of the substrate 101, the portions of the interconnects at the surface may be configured as annular structures.

In general, considering the potential effects of interconnects with the substrate 101 or other components, in some examples, interconnects are mated with through-holes of the substrate through intermediate structures.

For example, the interconnection may be formed by sequentially disposing a combination structure of an insulating layer, a barrier layer, and a seed layer on the inner wall of the via hole by plasma enhanced chemical vapor deposition, or sputtering, or physical vapor deposition, metal organic chemical vapor deposition, and then filling copper in the combination structure by electrochemical plating, etc. Of course, the material of the interconnection member may be selected from various materials corresponding to the actual situation in different examples, besides copper.

Structurally, the profile of the through silicon via interconnect 103 is generally adapted to the shape of the via. In general, the through silicon via interconnect 103 is a cylindrical structure and has a height defined by the thickness of the substrate 101. Additionally, the interconnects may alternatively be solid posts or hollow posts.

The applicant has thus described in detail the interconnection architecture scheme of the example, which a person skilled in the art will be able to implement in light of this disclosure. Based on the scheme, when the TSV technology is applied in the process of manufacturing equipment such as chips, the manufacturing quality of the interconnection piece can be evaluated conveniently, and scheme screening and verification can be further performed on the manufacturing process, the material, the size, the arrangement mode and the like of the interconnection piece.

For example, in fig. 3, one surface of the substrate 101, such as the front surface, is provided with a functional layer, and thus, observation can be performed from an oblique angle with respect to the front surface, thereby recognizing the manufacturing quality of the region where the interconnect is located inside the substrate 101. Alternatively, since the functional layer is not provided on the back surface of the substrate 101, the back surface thereof is completely exposed. Then, observation can also be made from a viewing angle direction with respect to which the back surface of the substrate 101 is inclined. Meanwhile, the upper and lower ends of the interconnection can be observed from a vertical or oblique view angle with respect to the surface of the substrate 101.

Furthermore, fig. 1 to 3 show an observation of a through-silicon-via, in order to visually identify the quality of the region of the interconnection within the substrate 101. In other examples, other observations may be made to further examine the through-silicon-via fabrication process.

Illustratively, fig. 4 discloses that three columns of interconnects (each having a hollow cylindrical configuration) are configured in the viewing window region 104. From left to right, in the orientation shown in fig. 4, there are a first column of interconnects (six), a second column of interconnects (five), and a third column of interconnects (five). Each interconnect in the same column has the same diameter. The diameter of the interconnects of different columns is different. The spacing between two interconnects of two adjacent rows in the same column is different and is graded overall.

Alternatively, the following can be set forth: in the area of the viewing window region 104, or first transparent window, of the substrate 101, a grid for positioning the individual vias and the through-silicon-via interconnects 103 therein is defined on the front side of the substrate 101. And, the mesh is formed by warps and wefts in a criss-cross manner. Wherein, the intersection of the longitude and the latitude is a lattice point. Thus, each via is positioned by a grid point of the grid, and each via corresponds one-to-one to each grid point.

For the example of the plurality of through-silicon via interconnects 103, it may be configured in different arrangements, and accordingly, the above-described mesh is designed in advance and configured based on the substrate 101 so as to be conveniently used as a reference for positioning.

Illustratively, the distance between two adjacent wefts is gradually changed in all wefts. Thus, when multiple through-silicon via interconnects 103 of the same size are positioned in the same warp and different wefts, these interconnects have longitudinally different adjacent pitches.

Similarly, the distance between two adjacent wefts is gradually changed in all warps. Thus, when multiple through-silicon via interconnects 103 of the same size are positioned in the same weft and different warps, then these interconnects have different adjacent pitches, measured in the lateral direction.

Furthermore, through hole schemes and interconnection schemes with various sizes and arrangement modes can be realized by matching with different through hole sizes (for example, the diameters of all through holes of the same weft are gradually changed; and/or the diameters of all through holes of the same warp are the same), and the advantages and the disadvantages of the schemes can be judged according to the observation result.

In other words, the shape and size (e.g., diameter in the case of a cylindrical shape) of a single through-silicon-via, and the arrangement of multiple through-silicon-vias (e.g., the pitch between adjacent through-silicon-vias) may cause fabrication failures or defects in the corresponding fabricated interconnects, and may also adversely affect the substrate 101.

For example, small through-silicon-via sizes make it difficult to fabricate vias and interconnects; too large a through-silicon-via may overly occupy the area of the substrate 101. Too small a via pitch may damage the substrate 101, which may also lead to cracks, chips, etc. in the interconnects. Due to these potential effects, the size and arrangement of the through holes can be selected for identification and evaluation, and the quality of the interconnection can be evaluated accordingly.

On the basis of the above-mentioned through-silicon-via interconnection structure, a new through-silicon-via interconnection structure can be implemented by further applying to a flip chip, please refer to fig. 5.

The interconnect structure includes a first chip 201, a second chip 202, and a through silicon via interconnect 103. The tsv interconnection 103 is disposed on the first chip 201, the second chip 202 is disposed opposite to the first chip 201, and the two chips are connected/flip-chip interconnected by a flip-chip interconnection 203 (a flip-chip interconnection, which may be a superconducting material, such as indium columns).

And has a first transparent window in view of the first chip 201. In particular, in some examples, some or all of the aforementioned flip-chip interconnects 203 may be selectively positioned in corresponding regions of the first transparent window. Thus, the flip-chip interconnect 203 can be viewed while selecting the view of the through-silicon via interconnect 103.

It is understood that the first transparent window can provide a viewing path from the front side to the back side of the first chip 201, and the first transparent window is further configured with a through hole extending along the front side to the back side; accordingly, the exemplary superconducting material of the through-silicon-via interconnect 103 fills the via.

As an example, the first chip 201 may adopt the interconnection structure in fig. 1 described above. Thus, at the backside of the first chip 201 (i.e. the surface facing away from the second chip 202), there is a gap 204 between the through silicon via interconnect 103 and the edge profile of the first transparent window.

In the through-silicon via interconnection structure of the flip chip type shown in fig. 5, a substrate of a transparent material is used for the first chip 201, and a substrate of a non-transparent material is used for the second chip 202 without limitation. It can thus be appreciated that in order to view the quality of the fabricated through-silicon via interconnect 103, the viewing direction may be a region located inside the transparent substrate 101 viewed obliquely from above the first chip 201 from the orientation shown in fig. 5.

Furthermore, when the substrate 101 made of a transparent material is also used for the second chip 202, the through-silicon via interconnection 103 may be optionally observed from a surface of the second chip 202 facing away from the first chip 201 at an oblique viewing angle; as shown in fig. 6.

Further, when the substrate of the second chip 202 is also provided with various appropriate signal lines or transmission lines or elements (and these lines and elements are usually opaque), in order to be able to view from the side of the second chip 202, it can be known that these elements also need to avoid the area of the through-silicon via interconnection 103 above; see fig. 7.

Referring again to the structure shown in fig. 7, along the direction in which the first chip 201 and the second chip 202 are opposite to each other, when the second chip 202 is also provided with a functional layer, i.e. a circuit or a device, it can be seen that the second chip 202 has a transparent window for allowing the substrate 101 of the second chip 202 to pass through and be limited by the functional layer; for example, the transparent window of the second chip 202 may be named as a second transparent window as distinguished from the first transparent window formed at the first chip 201. The shape of which may be defined by the contour of the top view angle at the surface of the second chip 202, for example, circular or rectangular.

In fig. 7, the first transparent window and the second transparent window may be selected to be opposite to each other along the opposite direction of the two chips; and, the first transparent window is located within the second transparent window in the orthographic projection area of the second chip 202. Alternatively, in another example different from fig. 7, the upper and lower transparent windows may be staggered by a suitable distance from each other, which is not shown.

Further, although the functional layers are disposed on one surface of each chip or substrate 101 in the above-mentioned drawings, the functional layers may be disposed on both surfaces of the chip or substrate in other examples not shown, and the view of the interconnects in the through holes is not limited.

In addition, based on the above-described flip chip structure, a quantum processor can be constructed, and thus a quantum computer having the foregoing through-silicon-via interconnection structure can be fabricated. The quantum computer may be further configured such as a control system, a reading system, and the like. The control system and the reading system are respectively matched with a flip chip serving as a quantum processor, so that quantum information such as state control, state and the like of quantum bits is read.

Further, a superconducting quantum computer, which is an example of a quantum computer, is also configured with a refrigeration system, and is generally selected as a dilution refrigerator. The dilution refrigerator has a closed vessel capable of providing milli-scale cryogenic temperatures. The quantum processor is disposed on a bottom layer of the container. The corresponding lines of the control and reading system are connected in the container with corresponding pads, pins, etc. of the quantum processor and are in a low temperature environment.

The embodiments described above with reference to the drawings are exemplary only for the purpose of illustrating the present application and are not to be construed as limiting the present application. In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the foregoing description explains the embodiments of the present application in detail with reference to the drawings. However, it will be appreciated by those of ordinary skill in the art that in the various embodiments of the present application, numerous technical details are set forth in order to provide a better understanding of the present application. However, the technical solution claimed in the present application can be implemented without these technical details and various changes and modifications based on the following embodiments. The division of the examples is for convenience of description, and should not constitute any limitation to the specific implementation manner of the present application, and the embodiments may be mutually incorporated and referred to each other without contradiction.

It should be noted that the terms "first," "second," and the like in the description and claims of this application and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application described herein are capable of operation in sequences other than those illustrated or described herein.

Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

In addition, it will be understood that when a layer (or film), region, pattern, or structure is referred to as being "on" a substrate, layer (or film), region, and/or pattern, it can be directly on the other layer or substrate, and/or intervening layers may also be present. In addition, it will be understood that when a layer is referred to as being "under" another layer, it can be directly under the other layer, and/or one or more intervening layers may also be present. In addition, references to "on" and "under" layers may be made based on the drawings.

The construction, features and functions of the present application are described in detail in the embodiments illustrated in the drawings, which are only preferred embodiments of the present application, but the present application is not limited by the drawings, and all equivalent embodiments that can be modified or changed according to the idea of the present application are within the scope of the present application without departing from the spirit of the present application.

Claims

1. A through-silicon-via interconnect structure, comprising:

the transparent substrate is provided with a front surface and a back surface which are oppositely arranged along the thickness direction, the substrate is also provided with a through hole from the front surface to the back surface in a penetrating way, the substrate is defined with an observation window area which surrounds the through hole, and the front surface defines a grid in the observation window area; the grid is formed by criss-cross warps and wefts, and the intersections of the warps and the wefts are grid points; the number of the through holes is multiple, all the through holes are positioned by the lattice points of the grids, and the through holes correspond to the lattice points one by one;

a functional layer formed on the front surface and/or the back surface, the functional layer avoiding and exposing the observation window region;

a through silicon via interconnect formed in the via.

2. The through silicon via interconnect structure of claim 1, wherein the interconnect structure is defined by one or more of:

a first definition, the transparent substrate being a sapphire substrate;

a second definition, the functional layer is one or more layers;

a third definition, the functional layer is a metal layer;

fourthly, the functional layer is made of superconducting materials;

a fifth defining the through-silicon via interconnect as a super-pillar;

sixthly, the through silicon via interconnect is a hollow post;

a seventh definition, the through silicon via interconnect extending to the front side at one end and the back side at another end.

3. A through silicon via interconnect structure, comprising:

the chip comprises a first chip and a second chip, wherein the first chip is provided with a first transparent window, the first transparent window provides an observation path from the front surface to the back surface of the first chip, the first transparent window is also provided with a through hole extending along the direction from the front surface to the back surface in a penetrating way, and in the area of the first transparent window, a grid is defined on the front surface; the grid is formed by criss-cross warps and wefts, and the intersections of the warps and the wefts are grid points; the number of the through holes is multiple, all the through holes are positioned by the lattice points of the grids, and the through holes correspond to the lattice points one by one;

a second chip opposed to the first chip in a manner facing the front surface, the second chip being flip-chip interconnected with the first chip by flip-chip interconnection; and

a through silicon via interconnection filled in the through hole;

at the back side, there is a gap between the through silicon via interconnect and an edge profile of the first transparent window.

4. The through silicon via interconnect structure of claim 3, wherein the through silicon via interconnect is hollow; and/or the through silicon via interconnection is cylindrical; and/or the through silicon via interconnection comprises a superconducting material; and/or, a portion of the flip-chip interconnect is positioned within a region of the first transparent window.

5. The through silicon via interconnect structure of claim 3, wherein the through silicon via interconnect is columnar and has a first end and a second end;

the first end extends to the front face and/or the second end extends to the back face.

6. The through silicon via interconnect structure of claim 5, wherein the first end and/or the second end are each circular.

7. The through silicon via interconnect structure of claim 3, wherein the second chip has a second transparent window, the second transparent window being directly opposite the first transparent window.

8. The through silicon via interconnect structure of claim 7, wherein an orthographic projection of the first transparent window on the second chip is located within the second transparent window; and/or the edge outline of the second transparent window is rectangular or circular.

9. The TSV interconnect structure of claim 3, 7 or 8, wherein the first transparent window has a rectangular or circular edge profile at the back side.

10. The through silicon via interconnect structure of claim 3, wherein the distance between two adjacent wefts is gradually varied among all wefts;

and/or the distance between two adjacent warps is gradually changed in all warps.

11. The through-silicon-via interconnect structure of claim 3 or 10, wherein the diameter of each through-hole of the same weft is gradually varied; and/or the diameter of each through hole of the same longitude line is the same.

12. A quantum computer comprising a quantum processor having the through-silicon-via interconnect structure of claims 3 to 11.