CN115295502A - Three-dimensional packaging structure and manufacturing method thereof - Google Patents

Three-dimensional packaging structure and manufacturing method thereof Download PDF

Info

Publication number
CN115295502A
CN115295502A CN202210859669.0A CN202210859669A CN115295502A CN 115295502 A CN115295502 A CN 115295502A CN 202210859669 A CN202210859669 A CN 202210859669A CN 115295502 A CN115295502 A CN 115295502A
Authority
CN
China
Prior art keywords
conductive circuit
chip
substrate
layer
circuit layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202210859669.0A
Other languages
Chinese (zh)
Inventor
朱凯
黄立湘
缪桦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shennan Circuit Co Ltd
Original Assignee
Shennan Circuit Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shennan Circuit Co Ltd filed Critical Shennan Circuit Co Ltd
Priority to CN202210859669.0A priority Critical patent/CN115295502A/en
Priority to PCT/CN2022/129806 priority patent/WO2024016517A1/en
Publication of CN115295502A publication Critical patent/CN115295502A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/145—Organic substrates, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02381—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/03001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

Abstract

The invention discloses a three-dimensional packaging structure and a manufacturing method thereof, wherein the manufacturing method comprises the following steps: providing a substrate made of an organic resin material, processing a through hole on the substrate, and electroplating in the through hole to form an interconnection metal column; processing a through groove at a set position of the substrate, embedding a preset chip in the through groove and carrying out plastic package; respectively carrying out circuit manufacturing on a bonding pad side and a non-bonding pad side on a substrate embedded with a preset chip to form conductive circuit layers, mounting a flip bare chip on one conductive circuit layer and carrying out plastic package, and planting balls on the other conductive circuit layer; the conductive circuit layer is connected with the interconnection metal column and comprises a first conductive circuit layer and a second conductive circuit layer. The three-dimensional packaging structure has the advantages of small packaging thickness, high packaging density, high density of the three-dimensional interconnection structure, low manufacturing cost and high fineness of circuits on the surface of the chip.

Description

Three-dimensional packaging structure and manufacturing method thereof
Technical Field
The invention relates to the field of semiconductor packaging, in particular to a three-dimensional packaging structure and a manufacturing method thereof.
Background
In modern chip packaging technology, a widely used chip packaging technology is Package on Package (PoP), and the main idea is to Package (or flip) a memory chip on top of a logic chip, and certainly, a passive component may be further mounted on top of the logic chip.
One of the biggest technical challenges of chip-on-package is the interconnection of the bottom package with the top package. Currently, the interconnection of the bottom package and the top package mainly adopts three types of methods:
the first method is based on the conventional packaging technology, i.e., after a chip is plastically packaged on a packaging substrate, the chip is used as a bottom packaging body, then a hole is drilled in a plastic packaging layer of the bottom packaging body, the hole is filled with a conductive paste to realize interconnection, and then the top packaging body which is already packaged is inversely installed on the top of the bottom packaging body.
The second method is based on advanced packaging technology, firstly, a seed layer is manufactured on a temporary carrier, then a dry film is pasted to electroplate a copper column, the seed layer is etched, a three-dimensional interconnection structure is obtained, a chip is further pasted, finally the chip is plastically packaged, the copper column is exposed through grinding, the three-dimensional interconnection structure is obtained, a bottom packaging body is manufactured, then the bottom packaging body is welded on a printed circuit board, and a top packaging body is welded on the bottom packaging body.
The third method is also based on advanced packaging technology, firstly, a through hole is processed on an organic resin core board for a printed circuit board, then, electroplating is carried out to realize the interconnection of two sides of the organic resin core board, then, a through groove is processed at a designated position, then, adhesive tapes are sequentially pasted on the through groove, a chip is pasted on the adhesive tapes in the through groove, and finally, the chip is plastically packaged, thus obtaining a three-dimensional interconnection structure. And manufacturing to obtain a bottom packaging body, then welding the bottom packaging body on the printed circuit board, and welding a top packaging body on the bottom packaging body.
However, in all the above methods, since the top package is generally a packaged chip, and since the thickness of the top package is thick, there are problems of low packaging density, low density of the three-dimensional interconnection structure, high manufacturing cost, and low fineness of the circuit on the surface of the chip.
Disclosure of Invention
Therefore, the three-dimensional packaging structure and the manufacturing method thereof are provided to solve the problems of low packaging density, low density of a three-dimensional interconnection structure, high manufacturing cost and low fineness of circuit on the surface of a chip in the prior art.
The embodiment of the invention provides a manufacturing method of a three-dimensional packaging structure, which comprises the following steps:
providing a substrate made of organic resin materials, processing a through hole in the substrate, and electroplating in the through hole to form an interconnection metal column;
processing a through groove at a set position of the substrate, embedding a preset chip in the through groove and carrying out plastic package;
respectively carrying out circuit manufacturing on a bonding pad side and a non-bonding pad side on the substrate embedded with the preset chip to form conductive circuit layers, mounting a flip bare chip on one conductive circuit layer and carrying out plastic package, and planting balls on the other conductive circuit layer; the conductive circuit layer is connected with the interconnection metal column and comprises a first conductive circuit layer and a second conductive circuit layer.
Optionally, the step of providing a substrate made of an organic resin material, processing a through hole in the substrate, and electroplating in the through hole to form an interconnection metal pillar includes:
providing a substrate made of an organic resin material, and processing through holes at positions on the substrate where the interconnection metal posts need to be manufactured;
and manufacturing a seed layer, and electroplating the through hole to obtain the interconnection metal column, wherein the copper layer is completely covered on the surface of the substrate.
Optionally, "bury the chip in advance in the logical groove and the plastic envelope" specifically includes:
bonding one side of the substrate on a first temporary carrier by using bonding glue; attaching the preset chip to the through groove on the first temporary carrier by using an attaching film, wherein a bonding pad of the preset chip is far away from the first temporary carrier;
and plastically packaging the preset chip in the through groove.
Optionally, "respectively performing circuit manufacturing on a pad side and a non-pad side of a substrate in which the preset chip is embedded to form conductive circuit layers, mounting a flip bare chip on one of the conductive circuit layers and performing plastic package, and planting balls on the other conductive circuit layer" specifically includes:
grinding the bonding pad side of the substrate until the bonding pad of the preset chip is exposed; performing line manufacturing on the ground bonding pad side on the substrate to form a first conductive line layer;
mounting a flip bare chip on the first conductive circuit layer, filling filler at the bottom of the flip bare chip, and plastically packaging the flip bare chip;
attaching a second temporary carrier to one side of the plastic package material of the flip bare chip;
removing the first temporary carrier, grinding and removing the non-pad side of the substrate after the first temporary carrier is removed, and carrying out circuit manufacturing on the non-pad side of the substrate to form a second conductive circuit layer;
and removing the second temporary carrier, and planting balls on the second conductive circuit layer.
Optionally, "respectively performing circuit manufacturing on a pad side and a non-pad side of a substrate in which the preset chip is embedded to form conductive circuit layers, mounting a flip bare chip on one of the conductive circuit layers and performing plastic package, and planting balls on the other conductive circuit layer" includes:
grinding the bonding pad side of the substrate until the bonding pad of the preset chip is exposed; conducting line manufacturing on the ground bonding pad side on the substrate to form a first conducting line layer;
attaching a second temporary carrier on the first conductive circuit layer, and removing the first temporary carrier; grinding and removing the non-pad side of the substrate after the first temporary carrier, and carrying out circuit manufacturing on the non-pad side of the substrate to form a second conductive circuit layer;
mounting the flip bare chip on the second conductive circuit layer, filling filler at the bottom of the flip bare chip, and plastically packaging the flip bare chip;
and removing the second temporary carrier, and planting balls on the first conductive circuit layer.
Optionally, the "forming a conductive circuit layer by performing circuit fabrication" specifically includes:
a target layer number of conductive circuit layers are obtained through multiple circulation manufacturing by adopting a lamination method, wherein the conductive circuit layers comprise conductive circuits and insulating media;
the conductive circuit is made by adopting a semi-additive method, and the insulating medium is one of photosensitive polyimide, thin composite material or epoxy resin.
Optionally, before mounting the flip bare chip on one of the conductive trace layers and performing plastic molding, the method further includes:
and manufacturing a surface treatment layer on the conducting circuit layer for mounting the flip bare chip.
Optionally, the ball mounting on the other conductive circuit layer specifically includes:
and manufacturing a surface treatment layer on the conductive circuit layer needing to be subjected to ball planting, and then planting balls on the conductive circuit layer on which the surface treatment layer is manufactured.
The manufacturing method of the three-dimensional packaging structure provided by the invention has the advantages that the bare chips are packaged together in a three-dimensional mode, and compared with stacked packaging, the thickness of a packaging body can be further reduced, and the packaging density is improved. The organic resin substrate is adopted to assist the chip in plastic package, so that the interconnected metal posts can be manufactured with high density, low cost and high yield, the mechanical strength of the chip plastic package layer can be improved, and the organic resin substrate is particularly suitable for large-size advanced package. In addition, the consumption of plastic package materials can be reduced, and the material cost of plastic package is reduced. The organic resin substrate is adopted to assist the chip in plastic package, so that the warping resistance of the package body can be improved, the package body with larger size can be realized, and the integration level of the package product can be improved. The chip is plastically packaged by the aid of the temporary carrier, specifically, the temporary carrier with small thermal expansion and isotropy is selected, so that the predictability of the position deviation of the chip during the plastic packaging of the chip, the position precision of the chip after the plastic packaging and the alignment precision of a chip pad side conducting circuit and the chip can be obviously improved. The temporary carrier auxiliary circuit is adopted for manufacturing for many times, specifically, a high-flatness temporary carrier is selected, and a grinding technology is combined, so that a high-flatness surface can be obtained, a high-precision conductive circuit can be manufactured, and the chip packaging density is improved.
The embodiment of the invention provides a three-dimensional packaging structure, which comprises:
a substrate of organic resin material, said substrate having a via, said via being plated with an interconnecting metal post;
the substrate is provided with a through groove, and a preset chip is embedded and plastically packaged in the through groove;
conductive circuit layers are respectively arranged on two sides of the substrate and connected with the interconnection metal columns; a flip bare chip is mounted on one of the conductive circuit layers and is subjected to plastic package, and balls are planted on the other conductive circuit layer.
Compared with the conventional stack packaging technology, the three-dimensional packaging structure provided by the invention structurally uses the bare chip stack packaging, and the packaging density is higher. The three-dimensional packaging structure has the advantages of high density of conducting circuits, small chip drift and good predictability. In addition, the method also has the advantages of low manufacturing cost of the interconnection metal column, short glue flowing distance of the plastic packaging material, low processing and transferring difficulty and good anti-warping capability.
Optionally, a first conductive circuit layer is arranged on a bonding pad side of the substrate embedded with the preset chip; a second conductive circuit layer is arranged on the non-pad side of the substrate embedded with the preset chip;
the first conductive line layer and the second conductive line layer are connected with the interconnection metal pillar;
the flip bare chip is mounted on the first conductive circuit layer and is subjected to plastic package, and a filling agent is filled at the bottom of the flip bare chip; and planting balls on the second conductive circuit layer.
Optionally, a first conductive circuit layer is arranged on a bonding pad side of the substrate embedded with the preset chip; a second conductive circuit layer is arranged on the non-welding disc side of the substrate embedded with the preset chip;
the first conductive line layer and the second conductive line layer are connected with the interconnection metal pillar;
the flip bare chip is mounted on the second conductive circuit layer and is subjected to plastic package, and filling agent is filled at the bottom of the flip bare chip; and planting balls on the first conductive circuit layer.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments of the present invention will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without inventive labor.
Fig. 1 is a flowchart of a method for manufacturing a three-dimensional package structure according to an embodiment of the invention;
FIG. 2-1 is a schematic diagram of a through hole processing on a substrate according to an embodiment of the present invention;
FIG. 2-2 is a schematic diagram of via plating on a substrate according to one embodiment of the present invention;
fig. 2-3 are schematic views illustrating processing of a through groove on a substrate according to an embodiment of the present invention;
FIGS. 2-4 are schematic diagrams illustrating the application of an adhesive to a substrate according to an embodiment of the present invention;
fig. 2-5 are schematic diagrams illustrating a substrate with adhesive removed from through-grooves according to an embodiment of the present invention;
fig. 2-6 are schematic views illustrating a first temporary carrier attached to a substrate by an adhesive according to an embodiment of the present invention;
fig. 2-7 are schematic diagrams illustrating a preset chip being attached to a through groove of a first temporary carrier according to an embodiment of the present invention;
fig. 2 to 8 are schematic diagrams illustrating a predetermined chip is plastically packaged in a through groove according to an embodiment of the present invention;
FIGS. 2-9 are schematic views illustrating polishing of a predetermined chip molding layer according to an embodiment of the present invention;
fig. 2-10 are schematic diagrams illustrating the formation of a first conductive trace on a substrate according to an embodiment of the invention;
FIGS. 2-11 are schematic diagrams of flip-chip bare chips on first conductive lines according to an embodiment of the present invention;
fig. 2-12 are schematic diagrams of a flip-chip bare chip with a filler filled in the bottom of a first conductive trace and molded in a plastic package according to an embodiment of the invention;
fig. 2-13 are schematic diagrams illustrating a second temporary carrier being attached to a side of a flip chip and the first temporary carrier being removed according to an embodiment of the present invention;
FIGS. 2-14 are schematic diagrams of polishing on a substrate-removed first temporary carrier side according to one embodiment of the present invention;
FIGS. 2-15 are schematic diagrams illustrating the fabrication of a second conductive trace layer on the substrate with the first temporary carrier removed;
fig. 2-16 are schematic diagrams illustrating ball implantation on a second conductive trace layer on a substrate according to an embodiment of the invention;
FIG. 3-1 is a schematic diagram illustrating a first conductive trace layer being polished according to another embodiment of the present invention;
fig. 3-2 is a schematic diagram of attaching a second temporary carrier on a first conductive line layer and removing the first temporary carrier according to another embodiment of the invention;
fig. 3-3 are schematic diagrams illustrating a second temporary carrier being attached to the first conductive trace layer and the first temporary carrier being removed according to another embodiment of the present invention;
FIGS. 3-4 are schematic diagrams illustrating the polishing of a second conductive trace layer according to another embodiment of the present invention;
FIGS. 3-5 are schematic diagrams of a flip-chip bare chip on a second conductive trace layer according to another embodiment of the invention;
fig. 3-6 are schematic diagrams of a bare chip plastically molded on a second conductive trace layer according to another embodiment of the invention;
fig. 3-7 are schematic diagrams illustrating ball-mounting on a first conductive line according to another embodiment of the present invention.
The package structure comprises an organic resin substrate 1, a through hole 2, an interconnection metal column 3, a through groove 4, a bonding glue 5, a first temporary carrier 6, a chip 7, an adhesive film 8, a plastic package material 9, a first conductive circuit layer 10, a bare chip 11, a micro-bump 12, a filler 13, a second conductive circuit 14, a second temporary carrier 15 and a BGA solder ball 16, wherein the through hole 2 is a through hole, the through hole 3 is an interconnection metal column, the through groove 5 is a through hole, the micro-bump 11 is a bare chip, the filler 13 is a filler, the second conductive circuit 14 is a filler, the second temporary carrier 15 is a through hole, and the BGA solder ball 16 is a solder ball.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.
It should be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It should also be understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.
As used in this specification and the appended claims, the term "if" may be interpreted contextually as "when", "upon" or "in response to a determination" or "in response to a detection". Similarly, the phrase "if it is determined" or "if a [ described condition or event ] is detected" may be interpreted contextually to mean "upon determining" or "in response to determining" or "upon detecting [ described condition or event ]" or "in response to detecting [ described condition or event ]".
Furthermore, in the description of the present specification and the appended claims, the terms "first," "second," "third," and the like are used for distinguishing between descriptions and not necessarily for describing a relative importance or importance.
Reference throughout this specification to "one embodiment" or "some embodiments," or the like, means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the present invention. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," or the like, in various places throughout this specification are not necessarily all referring to the same embodiment, but rather "one or more but not all embodiments" unless specifically stated otherwise. The terms "comprising," "including," "having," and variations thereof mean "including, but not limited to," unless otherwise specifically stated.
It should be understood that, the sequence numbers of the steps in the following embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by the function and the internal logic thereof, and should not limit the implementation process of the embodiments of the present invention in any way.
In order to explain the technical means of the present invention, the following description will be given by way of specific examples.
Referring to fig. 1, a flowchart of a method for manufacturing a three-dimensional package structure according to an embodiment of the present invention is shown, where the method includes:
s101, providing a substrate made of an organic resin material, processing a through hole in the substrate, and electroplating in the through hole to form an interconnection metal pillar.
Referring to fig. 2-1 and 2-2, in one example, "providing a substrate 1 of an organic resin material, processing a through hole 2 in the substrate 1, and performing electroplating in the through hole 2 to form an interconnection metal pillar 3" specifically includes:
providing a substrate 1 made of organic resin material, and processing through holes 2 at positions on the substrate 1 where interconnection metal posts 3 need to be manufactured;
and manufacturing a seed layer, electroplating the through hole 2 to obtain the interconnection metal column 3, and completely covering the copper layer, namely the metal layer, on the surface of the substrate 1.
Specifically, one organic resin substrate 1 is selected, and preferably, the organic resin substrate 1 may be an organic resin substrate 1 whose surface is covered with a copper foil, and the through-holes 2 are formed at predetermined positions of the organic resin substrate 1 where the interconnection metal posts 3 are to be formed. The method for processing the through hole 2 on the organic resin substrate 1 may be to drill the through hole 2 on the organic resin substrate 1 by using a mechanical drill, or may be to irradiate the through hole 2 on the organic resin substrate 1 by using a laser.
The inner wall of the through hole needs to be manufactured with a seed layer, and several seed layer manufacturing methods commonly used in the industry at present are as follows:
(1) Sputtering (PVD) or evaporation (CVD), in which case a metal layer is deposited on both the surface and the walls of the holes, typically one or two of Cu, ti, ni, cr, au, most commonly Ti/Cu.
(2) Electroless copper plating, catalytic reduction using a reducing agent (catalyst is Pd), attaches a metallic copper layer to both the surface and the pore walls.
(3) Conductive substances such as graphite, carbon black, graphene oxide and high-molecular conductive polymers are adsorbed only on the hole wall (without copper).
In the present invention, the order of electroless copper plating > sputtering/evaporation > adsorption of the conductive substance is preferable.
The electroplating of the through hole 2 refers to electroplating the through hole 2 of the organic resin substrate 1, wherein the electroplating material can be metal copper, and the electroplating mode is as follows: the through-hole 2 of the organic resin substrate 1 is filled with metal by direct current plating or pulse plating to form the interconnection metal post 3.
And S102, processing a through groove at a set position of the substrate, embedding a preset chip in the through groove and carrying out plastic package.
Referring to fig. 2-3 to 2-8, through-grooves 4 are processed at positions where the organic resin substrate 1 needs to be embedded with the predetermined chips 7, and the size of the through-grooves 4 is larger than that of the predetermined chips. Alternatively, the space of the through-groove 4 may accommodate one chip or two or more chips. The method for processing the through groove 4 on the organic resin substrate 1 may be processing the organic resin substrate 1 by using laser, so that the through groove 4 is exposed from the organic resin substrate 1; the organic resin substrate 1 may be exposed from the through-grooves 4 by machining.
"bury the chip of predetermineeing in leading to the inslot and plastic envelope" specifically includes:
as shown in fig. 2-4, firstly, the bonding glue is adhered to one side of the substrate 1, and then, as shown in fig. 2-5, the bonding glue 5 below the through groove is removed; then as shown in fig. 2-6, the substrate 1 is bonded on one side to a first temporary carrier 6 by means of an adhesive 5; as shown in fig. 2 to 7, the pre-set chip 7 is attached in the through groove 4 on the first temporary carrier 6 by using the attachment film 8, and the pad of the pre-set chip 7 is far away from the first temporary carrier 6;
the attaching film 8 is adopted to replace the original adhesive tape on the non-pad side of the preset chip 7, the preset chip 7 is attached to the first temporary carrier 6 with good thermal expansion coefficient matching performance and good uniformity, the problem that the preset chip 7 is greatly drifted due to large difference of the thermal expansion coefficients of the adhesive tape in the prior art is solved, and the fixing effect of the chip attaching film adopting a resin curing fixing mode is better than that of the adhesive tape with large temperature influence on viscosity.
In one example, the adhesive 5 is a double-sided adhesive, one side of which is used for adhering to one side of the organic resin substrate 1 and the other side of which is used for adhering to the first temporary carrier 6. The adhesive 5 is preferably used to fix the organic resin substrate 1 to the first temporary support 6.
Then, as shown in fig. 2 to 8, the plastic package of the preset chip 7 in the through groove specifically includes:
and filling the plastic package material 9 in the gap between the groove wall of the through groove of the organic resin substrate 1 and the preset chip 7 and covering the upper surface of the organic resin substrate 1. When more than two preset chips are placed in one through groove, the plastic package material is required to fill gaps among the preset chips.
The plastic package material 9 is also called epoxy plastic package material, is a packaging material of electronic components, is prepared by processing epoxy resin and phenolic resin serving as matrix resin, silicon micropowder serving as filler and a plurality of auxiliaries, and belongs to the prior art.
The plastic package material 9 can be granular, liquid or film type, the plastic package mode can be compression molding or vacuum film pasting, and when the vacuum film pasting plastic package is adopted, only the film type epoxy plastic package material can be used.
In one example, a release layer is disposed on a side of the first temporary carrier 6 close to the organic resin substrate 1, and the adhesive film is attached on the release layer.
The release layer can be a photosensitive debonding release layer, a thermosensitive debonding release layer, and preferably a photosensitive debonding release layer.
The purpose of setting up from the type layer is for making things convenient for organic resin core 1 and attached membrane 8 to peel off with first temporary carrier, can guarantee from the type layer that double faced adhesive tape (bonding glue) and solidified attached membrane 8 peel off from first temporary carrier, can not lead to first temporary carrier to be cracked because of huge stress when peeling off, bonding glue remains, chip attached membrane is cracked etc..
S103, respectively carrying out circuit manufacturing on a bonding pad side and a non-bonding pad side of a substrate embedded with a preset chip to form conductive circuit layers, mounting a flip bare chip on one conductive circuit layer and carrying out plastic package, and planting balls on the other conductive circuit layer; the conductive circuit layer is connected with the interconnection metal column and comprises a first conductive circuit layer and a second conductive circuit layer.
In particular, the pad side refers to the pad side of the predetermined chip, and the non-pad side refers to the non-pad side of the predetermined chip.
Referring to fig. 2-9 to 2-16, in an example, "performing circuit fabrication on a pad side and a non-pad side of a substrate in which a predetermined chip is embedded to form conductive circuit layers, respectively, mounting a flip-chip bare chip on one of the conductive circuit layers and performing plastic encapsulation, and planting balls on the other conductive circuit layer" specifically includes:
as shown in fig. 2 to 9, the pad side of the substrate 1 is ground to expose the pad of the predetermined chip 7; performing line manufacturing on the pad side of the ground substrate 1 to form a first conductive line layer 10;
specifically, the pad side of the organic resin substrate 1 after molding is polished to expose the pads of the pre-chip. The plastic package material and the metal layer on the upper surface of the bonding pad side of the preset chip are ground off in a mechanical grinding mode, so that the metal layer on the bonding pad side surface of the organic resin substrate 1 is completely ground off and the bonding pad on the surface of the preset chip is exposed. Since the organic resin substrate 1 has a high surface flatness, the organic resin substrate 1 can be polished to obtain a highly flat surface, which is advantageous for the fabrication of fine wiring.
As shown in fig. 2 to 10, the forming of the first conductive traces 10 on the pad side of the organic resin substrate 1 after grinding specifically includes:
and (3) manufacturing a plurality of circulating conducting circuits on the side of the bonding pad of the preset chip by adopting a lamination method, wherein the manufacturing is carried out by adopting a semi-addition method every time, and thus the first connecting circuit with the preset layer number is obtained.
And performing a plurality of times of circulating manufacture on the bonding pad side of the preset chip by adopting a lamination method to obtain a target layer number of conductive circuit layers, wherein the conductive circuit layers comprise conductive circuits and insulating media. The manufacture of the conductive circuit is preferably carried out by a semi-additive method, a photoresist material is selected according to the fineness of the conductive circuit, liquid photosensitive glue is preferably selected for the circuit with the thickness of less than 8 microns, and a dry film is preferably selected for the circuit with the thickness of 8 microns or more. The insulating medium is selected according to the fineness of the conductive circuit, the circuit with the diameter less than 8 μm is preferably photosensitive polyimide, the circuit with the diameter less than 8 μm is preferably ABF (Ajinomoto build-up film), and the circuit with the diameter of 50 μm and more can be selected from glass fiber cloth reinforced epoxy resin.
The process of forming the first conductive trace layer 10 is conventional and will not be described herein.
Preferably, in order to ensure the reliability of the flip bare chip in the subsequent mounting, a surface treatment layer may be further formed on a surface of the first conductive circuit layer on the embedded chip pad side, which is far away from the embedded chip pad. The surface treatment layer is preferably made of chemical nickel gold, and nickel gold electroplating, silver immersion, an organic solder resist and tin spraying can be selected.
As shown in fig. 2-11, mounting a flip bare chip 11 on the first conductive trace layer 10, and as shown in fig. 2-12, filling a filler 13 at the bottom of the flip bare chip 11, and plastically molding the flip bare chip 11;
the method specifically comprises the following steps: the pads of the bare chip 11 are mounted on the first conductive trace layer 10. When the size of the salient points of the flip bare chip 11 is smaller and the size of the flip bare chip is larger, hot-pressing bonding mounting is preferred, and a non-conductive adhesive film material is preferred to realize bottom filling of the chip; when the flip bare chip bump size is large and the flip bare chip size is small, batch reflow mounting of the chips is preferred, and chip underfill by a non-conductive adhesive film or a capillary underfill is preferred. And (3) plastically packaging the flip bare chip 11 by adopting a plastic packaging material 9, wherein the plastic packaging material 9 is filled above the first conductive circuit layer 10 to form a plastic packaging layer, and the height of the plastic packaging layer is not lower than that of the flip bare chip. The plastic packaging mode is preferably compression molding, and the plastic packaging material can be epoxy plastic packaging material, preferably granular and liquid plastic packaging material, and also can be film type plastic packaging material. The plastic package mode can also be vacuum film pasting, wherein when the vacuum film pasting is used for plastic package, only thin film type epoxy plastic package materials can be used.
In one example, as shown in fig. 2-13, a second temporary carrier 15 may also be attached on the flip-chip side;
the method specifically comprises the following steps: and attaching a second temporary carrier 15 above the flip bare chip, wherein the first temporary carrier 6 and the second temporary carrier 15 are hard carriers, and the hard carriers are one of glass carriers, stainless steel carriers or silicon chip carriers.
When the second conductive circuit layer 14 is manufactured on the surface of the substrate on the non-pad side of the embedded chip, the second temporary carrier 15 is added on the pad side of the embedded chip, namely above the first conductive circuit layer 10, and the surface of the substrate on the non-pad side of the embedded chip is ground, so that a surface with high flatness is obtained, the density of the conductive circuits on the non-pad side of the embedded chip is improved, and the overall packaging density of the packaging body is improved. This, of course, is also in order to accommodate the relatively high demand for conductive traces in the actual chip (transistor) density in the package.
Removing the first temporary carrier 6, grinding and removing the non-pad side, namely the copper layer, of the substrate after the first temporary carrier 6 is removed, and carrying out circuit manufacturing on the non-pad side of the substrate to form a second conductive circuit layer 14;
the method specifically comprises the following steps: as shown in fig. 2-14, the first temporary carrier 6 is removed, the non-pad side of the substrate 1 after the first temporary carrier 6 is removed by grinding, the bonding layer and the metal layer, i.e. the copper layer, on the surface of the substrate are ground away, and at this time, the die pad side still has a predetermined thickness of the attaching film. When the non-pad side of the substrate is ground, no connecting pad with a diameter slightly larger than that of the copper column is arranged at the position of the copper column, so that the design density of the side conducting circuit is improved.
As shown in fig. 2-15, a target number of conductive circuit layers are obtained by multiple-cycle manufacturing on the non-pad side of the embedded chip by a lamination method, wherein the conductive circuit layers comprise conductive circuits and insulating media; the manufacturing of the conductive circuit is preferably performed by a semi-additive method, a photoresist material is selected according to the fineness degree of the conductive circuit, liquid photosensitive glue is preferably selected for circuits below 8 mu m, and dry films are preferably selected for circuits above 8 mu m; the insulating medium is selected according to the fineness of the conducting circuit, the circuit with the thickness of less than 8 microns is preferably photosensitive polyimide, the circuit with the thickness of 8 microns and more is preferably ABF, and the circuit with the thickness of 50 microns and more can be selected from glass fiber cloth reinforced epoxy resin.
The process of forming the second conductive trace layer 14 is well known in the art and will not be described herein.
Finally, as shown in fig. 2-16, the second temporary carrier 15 is removed, and the second conductive trace layer 14 is ball-planted to form BGA solder balls 16.
The method specifically comprises the following steps: the second temporary carrier 15 on the flip chip side is released, the bonding-releasing manner is determined according to the type of the release layer, and the remaining adhesive layer is removed. Then, the second conductive circuit layer on the non-pad side of the embedded chip is subjected to Ball planting on the surface far away from the embedded chip to form a BGA (Ball grid Array) solder Ball 16, and the Ball planting on the surface is used for forming the BGA solder Ball 16 so as to solder the three-dimensional packaging structure to the surface of a printed circuit board or other chips.
The bare chip is directly inverted and integrally plastically packaged on the side of the embedded chip bonding pad, instead of welding the packaged chip, so that the thickness of the packaging body is further reduced, and the density of the chip (the density of the transistor) in the whole packaging body can also be improved.
Referring to fig. 2-1 to 2-10 and 3-1 to 3-7 in the foregoing embodiment, in another example, the method includes performing circuit fabrication on a pad side and a non-pad side of a substrate on which the predetermined chip is embedded to form conductive circuit layers, respectively, mounting a flip-chip bare chip on one of the conductive circuit layers and performing plastic molding, and performing ball-mounting on the other conductive circuit layer, specifically including:
the steps of embedding a predetermined chip on the substrate and forming the first conductive trace layer on the substrate are the same as those before fig. 2-1 to 2-10 in the foregoing embodiments, and are the same as the above steps, and are not described again here.
Then, as shown in fig. 3-1, on the pad side of the polishing substrate 1 until the pad of the predetermined chip 7 is exposed; performing line manufacturing on the pad side of the ground substrate 1 to form a first conductive line layer 10;
then as shown in fig. 3-2, attaching a second temporary carrier 15 on the first conductive trace layer 10, and removing the first temporary carrier 6; then, as shown in fig. 3-4, the non-pad side of the substrate after the first temporary carrier is removed is ground, and as shown in fig. 3-5, a second conductive circuit layer is formed by conducting circuit manufacturing on the non-pad side of the substrate;
the method specifically comprises the steps of attaching a second temporary carrier 15 to the upper surface of a first conductive circuit layer 10, removing the first temporary carrier 6, grinding off adhesive glue and a metal layer on the surface of the organic resin substrate 1, and grinding off an attaching film embedded with a preset thickness on the non-pad side of the chip. And forming a second conductive circuit layer 14 by circuit manufacturing on the non-pad side of the substrate 1. The second conductive trace layer 14 is made by the prior art and will not be described herein.
As shown in fig. 3-5, mounting the flip-chip bare chip 11 on the second conductive trace layer 14, and as shown in fig. 3-6, filling a filler 13 at the bottom of the flip-chip bare chip 11, and molding the flip-chip bare chip 11;
the method specifically comprises the following steps: the bonding pad of the bare chip 11 is connected with the second conductive circuit layer 14 through the micro-bumps 12, the filler is filled between the bare chip 11 and the second conductive circuit layer 14, the flip bare chip is plastically packaged by the plastic package material 9, the plastic package material 9 is filled on the surface, away from the non-bonding pad side of the embedded chip, of the second conductive circuit layer 14 to form a plastic package layer, and the height of the plastic package layer is not lower than that of the flip bare chip.
As shown in fig. 3-7, the second temporary carrier 15 is removed, and the first conductive trace layer 10 is subjected to ball-planting to form BGA solder balls 16.
Specifically, the second temporary carrier 15 is removed, and the first conductive trace layer 10 is subjected to ball-planting to form BGA solder balls 16, which are used to solder the three-dimensional package structure to a printed circuit board or other chip surface.
The flip chip is located on the non-pad side of the embedded chip, and this example allows higher density circuitry and more solder balls to be routed on the pad side of the embedded chip (the number of solder balls on the non-pad side of the embedded chip is limited by the density of the interconnecting copper pillars), so that a higher overall chip (transistor) density package can be achieved, and in particular, a higher transistor density embedded chip can be used or more chips can be embedded.
The manufacturing method of the three-dimensional packaging structure provided by the invention has the advantages that the bare chips are packaged together in a three-dimensional manner, and compared with stacked packaging, the thickness of a packaging body can be further reduced, and the packaging density is improved. The organic resin substrate is adopted to assist the chip in plastic package, so that the interconnected metal columns can be manufactured with high density, low cost and high yield, the mechanical strength of the chip plastic package layer can be improved, and the organic resin substrate is particularly suitable for large-size advanced package. In addition, the using amount of plastic packaging materials can be reduced, and the material cost of plastic packaging is reduced. The organic resin substrate is adopted to assist the chip in plastic package, so that the warping resistance of the package body can be improved, the package body with larger size can be realized, and the integration level of the package product can be improved. The chip is plastically packaged by the aid of the temporary carrier, specifically, the temporary carrier with small thermal expansion and isotropy is selected, so that the predictability of the position deviation of the chip during the plastic packaging of the chip, the position precision of the chip after the plastic packaging and the alignment precision of the side conducting circuit of the chip bonding pad and the chip can be obviously improved. The temporary carrier auxiliary circuit is adopted for manufacturing for many times, specifically, a high-flatness temporary carrier is selected, and a grinding technology is combined, so that a high-flatness surface can be obtained, a high-precision conductive circuit can be manufactured, and the chip packaging density is improved.
An embodiment of the present invention provides a schematic diagram of a three-dimensional package structure, where the three-dimensional package structure includes:
a substrate of organic resin material, the substrate having a through hole, the through hole being plated with an interconnection metal post;
the substrate is provided with a through groove, and a preset chip is embedded and plastically packaged in the through groove;
conductive circuit layers are respectively arranged on two sides of the substrate and connected with the interconnection metal columns; a flip bare chip is mounted on one of the conductive circuit layers and is subjected to plastic package, and balls are planted on the other conductive circuit layer.
In one example, referring to fig. 2 to 16, a first conductive line layer 10 is provided on a pad side on a substrate 1 in which a predetermined chip is embedded; a second conductive circuit layer 14 is provided on the non-pad side of the substrate 1 in which the predetermined chip 7 is embedded;
the first conductive line layer 10 and the second conductive line layer 14 are connected to the interconnection metal posts 3;
a flip bare chip 11 is mounted on the first conductive circuit layer 10 and is subjected to plastic package, and a filling agent 13 is filled at the bottom of the flip bare chip 11; the second conductive trace layer 14 is plated with balls.
The substrate 1 is made of an organic resin material. And a plastic packaging material 9 is filled between the embedded preset chip 7 and the inner wall of the substrate, a plastic packaging material 9 is filled between the flip bare chip 11 and the first conductive circuit layer 10, and an attaching film 8 is also arranged between the non-pad side of the embedded preset chip 7 and the second conductive circuit layer 14.
In another example, referring to fig. 3 to 7, a first conductive line layer 10 is provided on the pad side on the substrate 1 in which the pre-set chip 7 is embedded; a second conductive circuit layer 14 is provided on the non-pad side of the substrate 1 in which the predetermined chip 7 is embedded;
the first conductive line layer 10 and the second conductive line layer 14 are connected to the interconnection metal posts 3;
the flip bare chip 11 is mounted on the second conductive circuit layer 14 and is subjected to plastic package, and the filler 13 is filled at the bottom of the flip bare chip 11; the first conductive circuit layer 10 is provided with balls.
In one example, the filler 13 at the bottom of the flip-chip bare chip is a non-conductive adhesive film or a capillary underfill.
The substrate 1 is made of organic resin materials, plastic packaging materials 9 are filled between the embedded preset chip 7 and the inner wall of the substrate, the plastic packaging materials 9 are filled between the flip bare chip 11 and the second conductive circuit layer 14, and an attaching film 8 is further arranged between the non-pad side of the embedded preset chip 7 and the second conductive circuit layer 14.
Compared with the conventional stack packaging technology, the three-dimensional packaging structure provided by the invention structurally uses bare chips for stack packaging, has higher packaging density, and has the advantages of high flatness of the temporary carrier, small chip drift and good predictability. In addition, the method also has the advantages of low manufacturing cost of the interconnection metal column, short glue flowing distance of the plastic packaging material, low processing and transferring difficulty and good anti-warping capability.
The above-mentioned embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the embodiments of the present invention, and they should be construed as being included therein.

Claims (10)

1. A manufacturing method of a three-dimensional packaging structure is characterized by comprising the following steps:
providing a substrate made of organic resin materials, processing a through hole in the substrate, and electroplating in the through hole to form an interconnection metal column;
processing a through groove at a set position of the substrate, embedding a preset chip in the through groove and carrying out plastic package;
respectively carrying out circuit manufacturing on a bonding pad side and a non-bonding pad side on the substrate embedded with the preset chip to form conductive circuit layers, mounting a flip bare chip on one conductive circuit layer and carrying out plastic package, and planting balls on the other conductive circuit layer; the conductive circuit layer is connected with the interconnection metal column, and comprises a first conductive circuit layer and a second conductive circuit layer.
2. The method for manufacturing the three-dimensional encapsulation structure according to claim 1, wherein the providing a substrate made of an organic resin material, processing a through hole in the substrate, and performing electroplating in the through hole to form the interconnection metal pillar specifically comprises:
providing a substrate made of an organic resin material, and processing through holes at positions on the substrate where the interconnection metal posts need to be manufactured;
and manufacturing a seed layer, electroplating a through hole to obtain an interconnection metal column, and completely covering the copper layer on the surface of the substrate.
3. The manufacturing method of the three-dimensional package structure according to claim 1, wherein the step of embedding a preset chip in the through groove and performing plastic molding specifically comprises the steps of:
bonding one side of the substrate on a first temporary carrier by using bonding glue; attaching the preset chip to the through groove on the first temporary carrier by using an attaching film, wherein a bonding pad of the preset chip is far away from the first temporary carrier;
and plastically packaging the preset chip in the through groove.
4. The method for manufacturing a three-dimensional package structure according to claim 3, wherein the steps of performing circuit manufacturing on a pad side and a non-pad side of a substrate in which the preset chip is embedded to form conductive circuit layers, mounting a flip bare chip on one of the conductive circuit layers and performing plastic package, and planting balls on the other conductive circuit layer specifically include:
grinding the bonding pad side of the substrate until the bonding pad of the preset chip is exposed; conducting line manufacturing on the side of the preset chip bonding pad to form a first conducting line layer;
mounting a flip bare chip on the first conductive circuit layer, filling filler at the bottom of the flip bare chip, and plastically packaging the flip bare chip;
attaching a second temporary carrier to one side of the plastic packaging material of the flip bare chip;
removing the first temporary carrier, grinding the non-pad side of the preset chip after removing the first temporary carrier, and carrying out circuit manufacturing on the non-pad side of the preset chip to form a second conductive circuit layer;
and removing the second temporary carrier, and planting balls on the second conductive circuit layer.
5. The method for manufacturing a three-dimensional package structure according to claim 3, wherein the step of performing circuit manufacturing on a pad side and a non-pad side of a substrate in which the predetermined chip is embedded to form conductive circuit layers, respectively, mounting a flip bare chip on one of the conductive circuit layers and performing plastic package, and planting balls on the other conductive circuit layer specifically comprises:
grinding the bonding pad side of the substrate until the bonding pad of the preset chip is exposed; conducting line manufacturing on the ground bonding pad side on the substrate to form a first conducting line layer;
attaching a second temporary carrier on the first conductive circuit layer, and removing the first temporary carrier; grinding and removing the non-pad side of the preset chip after the first temporary carrier is removed, and carrying out circuit manufacturing on the non-pad side of the preset chip to form a second conductive circuit layer;
mounting the flip bare chip on the second conductive circuit layer, filling filler at the bottom of the flip bare chip, and plastically packaging the flip bare chip;
and removing the second temporary carrier, and planting balls on the first conductive circuit layer.
6. The method for manufacturing a three-dimensional package structure according to any one of claims 1 to 5, wherein the step of performing circuit manufacturing to form a conductive circuit layer specifically comprises:
and circularly manufacturing the target layer of the conductive circuit layer by adopting a lamination method for multiple times, wherein the conductive circuit layer comprises a conductive circuit and an insulating medium, the conductive circuit is manufactured by adopting a semi-additive method, and the insulating medium is one of photosensitive polyimide, a thin composite material or epoxy resin.
7. The method for manufacturing a three-dimensional package structure according to claim 1, wherein before mounting the flip bare chip on one of the conductive trace layers and performing plastic encapsulation, the method further comprises:
manufacturing a surface treatment layer on the conducting circuit layer provided with the flip bare chip;
the ball planting on the other conductive circuit layer specifically comprises:
and manufacturing a surface treatment layer on the conductive circuit layer needing to be subjected to ball planting, and then planting balls on the conductive circuit layer on which the surface treatment layer is manufactured.
8. A three-dimensional package structure, comprising:
a substrate of organic resin material, said substrate having a via, said via being plated with an interconnecting metal post;
the substrate is provided with a through groove, and a preset chip is embedded and plastically packaged in the through groove;
conductive circuit layers are arranged on two sides of the substrate respectively and connected with the interconnection metal columns; a flip bare chip is mounted on one of the conductive circuit layers and is subjected to plastic package, and balls are planted on the other conductive circuit layer.
9. The solid package structure according to claim 8, wherein a first conductive trace layer is provided on a pad side of the substrate in which the predetermined chip is embedded; a second conductive circuit layer is arranged on the non-pad side of the substrate embedded with the preset chip;
the first conductive line layer and the second conductive line layer are connected with the interconnection metal pillar;
the flip bare chip is mounted on the first conductive circuit layer and is subjected to plastic package, and filling agent is filled at the bottom of the flip bare chip; and planting balls on the second conductive circuit layer.
10. The solid package structure according to claim 8, wherein a first conductive trace layer is provided on a pad side of the substrate in which the predetermined chip is embedded; a second conductive circuit layer is arranged on the non-welding disc side of the substrate embedded with the preset chip;
the first conductive line layer and the second conductive line layer are connected with the interconnection metal pillar;
the flip bare chip is mounted on the second conductive circuit layer and is subjected to plastic package, and a filling agent is filled at the bottom of the flip bare chip; and planting balls on the first conductive circuit layer.
CN202210859669.0A 2022-07-21 2022-07-21 Three-dimensional packaging structure and manufacturing method thereof Pending CN115295502A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN202210859669.0A CN115295502A (en) 2022-07-21 2022-07-21 Three-dimensional packaging structure and manufacturing method thereof
PCT/CN2022/129806 WO2024016517A1 (en) 2022-07-21 2022-11-04 Three-dimensional packaging structure and manufacturing method therefor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210859669.0A CN115295502A (en) 2022-07-21 2022-07-21 Three-dimensional packaging structure and manufacturing method thereof

Publications (1)

Publication Number Publication Date
CN115295502A true CN115295502A (en) 2022-11-04

Family

ID=83823387

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210859669.0A Pending CN115295502A (en) 2022-07-21 2022-07-21 Three-dimensional packaging structure and manufacturing method thereof

Country Status (2)

Country Link
CN (1) CN115295502A (en)
WO (1) WO2024016517A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024016525A1 (en) * 2022-07-21 2024-01-25 深南电路股份有限公司 Bottom package and fabrication method therefor, and package on package structure and fabrication method therefor

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8101868B2 (en) * 2005-10-14 2012-01-24 Ibiden Co., Ltd. Multilayered printed circuit board and method for manufacturing the same
US8159828B2 (en) * 2007-02-23 2012-04-17 Alpha & Omega Semiconductor, Inc. Low profile flip chip power module and method of making
US20140035935A1 (en) * 2012-08-03 2014-02-06 Qualcomm Mems Technologies, Inc. Passives via bar
CN103871996A (en) * 2012-12-11 2014-06-18 宏启胜精密电子(秦皇岛)有限公司 Package structure and manufacturing method thereof
CN109087909A (en) * 2018-08-10 2018-12-25 付伟 Multi-chamber encapsulating structure with metal column and preparation method thereof
CN109727969A (en) * 2018-12-29 2019-05-07 华进半导体封装先导技术研发中心有限公司 A kind of substrate flush type power device packaging structure and its manufacturing method
US11164818B2 (en) * 2019-03-25 2021-11-02 Intel Corporation Inorganic-based embedded-die layers for modular semiconductive devices
CN114050111A (en) * 2021-11-16 2022-02-15 江苏芯德半导体科技有限公司 Fan-out type packaging method and fan-out type packaging structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024016525A1 (en) * 2022-07-21 2024-01-25 深南电路股份有限公司 Bottom package and fabrication method therefor, and package on package structure and fabrication method therefor

Also Published As

Publication number Publication date
WO2024016517A1 (en) 2024-01-25

Similar Documents

Publication Publication Date Title
US6627998B1 (en) Wafer scale thin film package
US10177130B2 (en) Semiconductor assembly having anti-warping controller and vertical connecting element in stiffener
US6611055B1 (en) Leadless flip chip carrier design and structure
US8217509B2 (en) Semiconductor device
US10790234B2 (en) Embedding known-good component in known-good cavity of known-good component carrier material with pre-formed electric connection structure
EP3288077B1 (en) Microelectronic package having a bumpless laminated interconnection layer
EP2798675B1 (en) Method for a substrate core layer
CN100452342C (en) Method for manufacturing board with built-in device and board with built-in device, and method for manufacturing printed wiring board and printed wiring board
TW200931628A (en) Stacking die package structure for semiconductor devices and method of the same
EP3836209B1 (en) Component carrier and method of manufacturing the same
TW201208004A (en) Semiconductor device package structure and forming method of the same
CN102034768B (en) Embedded-dice-inside type substrate structure with redistribution layer covered on both side and method thereof
KR20140029268A (en) Method of manufacturing semiconductor device
JP2003347352A (en) Method for bonding ic chip by non-conductive adhesive to substrate and assembly formed by the method
CN115295502A (en) Three-dimensional packaging structure and manufacturing method thereof
WO2024016525A1 (en) Bottom package and fabrication method therefor, and package on package structure and fabrication method therefor
US6495771B2 (en) Compliant multi-layered circuit board for PBGA applications
CN210575899U (en) Embedded multi-chip and element SIP fan-out type packaging structure
CN113035830A (en) Semiconductor structure and manufacturing method thereof
JP5371834B2 (en) Wiring circuit structure and manufacturing method of semiconductor device using the same
CN108305864B (en) Terminal with a terminal body
US9673063B2 (en) Terminations
CN218887167U (en) Semiconductor packaging device
JP4770095B2 (en) Manufacturing method of multilayer wiring board
CN117133748A (en) Package and method for manufacturing the same

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination