CN115277520B

CN115277520B - Detection method and detection circuit

Info

Publication number: CN115277520B
Application number: CN202211196625.0A
Authority: CN
Inventors: 应子罡; 赵亚琼; 杨猛; 曹正; 张雄波; 刘银栋; 杨丽丽; 何斌
Original assignee: Beijing Tasson Science and Technology Co Ltd
Current assignee: Beijing Tasson Science and Technology Co Ltd
Priority date: 2022-09-29
Filing date: 2022-09-29
Publication date: 2022-12-27
Anticipated expiration: 2042-09-29
Also published as: CN115277520A

Abstract

The application relates to a detection method and a detection circuit, wherein the method comprises the following steps: starting a target switch in the first signal selection circuit, and closing other switches; acquiring a first signal through the first ADC sampling circuit, and acquiring a second signal through the first ADC sampling circuit after a standard signal is sent through a first sending circuit if the first signal meets a preset first level condition; if the second signal meets a preset second level condition, the standard signal sent by the first sending circuit is closed, and a third signal is collected through the first ADC sampling circuit; and determining the state of the first port corresponding to the third signal according to the corresponding relation between a preset signal and the port state. By adopting the method, the real-time state of the port can be comprehensively and accurately detected under the condition of not increasing additional detection signal sources, and the interference of the additional detection signal sources is avoided.

Description

Detection method and detection circuit

Technical Field

The present application relates to the field of communications technologies, and in particular, to a detection method and a detection circuit.

Background

With the development of science and technology, the vehicle-mounted ethernet is also continuously developed, and in the related art, an interface circuit of the vehicle-mounted ethernet is composed of a MAC (media access control), a PHY chip (physical interface transceiver) and a twisted pair socket, and bidirectional transmission of signals is realized through physical connection between the twisted pair socket and a twisted pair. In order to ensure stable transmission of signals, the working state of a vehicle port of a vehicle ethernet needs to be detected.

In the related art, a test signal source (such as a Time Domain Reflectometer (TDR)) is added in an ethernet physical layer interface chip to detect a working state of a vehicle-mounted port of a vehicle-mounted ethernet, and because an additional test signal needs to be generated by the test signal source in a detection mode in the related art, the detection mode is easily interfered by the additional test signal, and misjudgment is generated.

Disclosure of Invention

In view of the above, it is necessary to provide a detection method and a detection circuit capable of accurately determining the operating state of a port.

In a first aspect, the present application provides a detection method.

The method is applied to a detection circuit, which comprises: the device comprises a control device, a first transmitting chip and a second transmitting chip, wherein the first transmitting chip comprises a first transmitting circuit, a first port, a first received signal processing circuit, a first signal selection circuit and a first ADC sampling circuit; the first port is connected with a first end of the first received signal processing circuit, the first transmitting circuit is connected with a first end of the first received signal processing circuit, the first port is connected with a first end of the first signal selection circuit, the first transmitting circuit is connected with a first end of the first signal selection circuit, a second end of the first received signal processing circuit is connected with a second end of the first signal selection circuit, a third end of the first signal selection circuit is connected with the first ADC sampling circuit, the first transmitting chip is connected with the second transmitting chip through a common mode choke coil, and the first signal selection circuit comprises a plurality of switches;

starting a target switch in the first signal selection circuit, and closing other switches;

acquiring a first signal through the first ADC sampling circuit, and acquiring a second signal through the first ADC sampling circuit after sending a standard signal through a first sending circuit if the first signal does not meet a preset first level condition;

if the second signal meets a preset second level condition, the standard signal sent by the first sending circuit is closed, and a third signal is collected through the first ADC sampling circuit;

and determining the state of the first port corresponding to the third signal according to the corresponding relation between a preset signal and the port state.

In one embodiment, the determining the state of the first port corresponding to the third signal according to a corresponding relationship between a preset signal and a port state includes:

determining that the first port is in an open state if the third signal is a preset common mode signal;

determining that the first port is in a normal state if the third signal is not the predetermined common mode signal.

In one embodiment, the method further comprises:

if the first signal meets a preset first level condition, determining that the first port is in a normal state under the condition that the first signal is the standard signal;

or, in a case where the level of the first signal is a zero level, determining that the first port is in a short-circuited to ground state;

or, in case the level of the first signal is a preset power level, determining that the first port is in a short-circuited to power state.

In one embodiment, the first port comprises a first sub-port and a second sub-port; each circuit in the detection circuit is connected through two paths, the first sub-port is arranged on a first branch, and the second sub-port is arranged on a second branch;

the acquiring, by the first ADC sampling circuit, a first signal comprises:

acquiring a first sub-signal corresponding to the first sub-port and acquiring a second sub-signal corresponding to the second sub-port through the first ADC sampling circuit;

the method further comprises the following steps:

and determining that the first sub-port corresponding to the first sub-signal is in an open state when the level of the first sub-signal is the level of a preset common mode signal and the second sub-signal is the standard signal.

In one embodiment, the method further comprises:

if the second signal does not meet a preset second level condition, determining that the first port is in a normal state under the condition that the second signal is a standard signal;

or, when the level of the second signal is the level of the preset common mode signal, determining that the first sub-port and the second sub-port in the first port are in a short-circuit and floating state.

In one embodiment, the first signal selection circuit includes a first switch, a second switch, and a third switch;

a first end of the first signal selection circuit is connected with a first end of the first switch, a second end of the first signal selection circuit is connected with a first end of the second switch, a target control device is connected with a first end of the third switch, and a second end of the first switch, a second end of the second switch and a second end of the third switch are connected with a third end of the first signal selection circuit;

the starting of the target switch in the first signal selection circuit and the closing of other switches comprises:

and starting the second switch in the first signal selection circuit, and closing the first switch and the third switch.

In a second aspect, the present application further provides a detection circuit, including: the device comprises a control device, a first transmitting chip and a second transmitting chip, wherein the first transmitting chip comprises a first transmitting circuit, a first port, a first received signal processing circuit, a first signal selection circuit and a first ADC sampling circuit; the first port is connected with a first end of the first received signal processing circuit, the first transmitting circuit is connected with a first end of the first received signal processing circuit, the first port is connected with a first end of the first signal selection circuit, the first transmitting circuit is connected with a first end of the first signal selection circuit, a second end of the first received signal processing circuit is connected with a second end of the first signal selection circuit, a third end of the first signal selection circuit is connected with the first ADC sampling circuit, the first transmitting chip is connected with the second transmitting chip through a common mode choke coil, and the first signal selection circuit comprises a plurality of switches;

the control device is used for starting a target switch in the first signal selection circuit and closing other switches;

the control device is further configured to acquire a first signal through the first ADC sampling circuit, and if the first signal does not satisfy a preset first level condition, acquire a second signal through the first ADC sampling circuit after sending a standard signal through the first sending circuit;

and if the second signal meets a preset second level condition, closing the standard signal sent by the first sending circuit, acquiring a third signal through the first ADC sampling circuit, and determining the state of the first port corresponding to the third signal according to the corresponding relation between the preset signal and the port state.

In one embodiment, the detection circuit further comprises a first ADC driving circuit;

the first end of the first ADC driving circuit is connected with the third end of the first signal selection circuit, and the second end of the first ADC driving circuit is connected with the first ADC sampling circuit.

In one embodiment, the detection circuit further includes a capacitor, and the first transmitting chip is connected to the common mode choke through the capacitor, and the common mode choke is connected to the second transmitting chip.

In one embodiment, the first port comprises a first sub-port and a second sub-port, and the capacitor comprises a first sub-capacitor and a second sub-capacitor; each circuit in the detection circuit is connected through two paths, the first sub-switch and the first sub-port are arranged on one path, and the second sub-switch and the second sub-port are arranged on the other path; the first sub-port is connected with the common mode choke coil through the first sub-capacitor, and the second sub-port is connected with the common mode choke coil through the second sub-capacitor.

In a third aspect, the application also provides a computer device. The computer device comprises a memory and a processor, wherein the memory stores a computer program, and the processor realizes the steps when executing the computer program.

In a fourth aspect, the present application further provides a computer-readable storage medium. The computer-readable storage medium has stored thereon a computer program which, when executed by a processor, performs the above-described steps.

In a fifth aspect, the present application further provides a computer program product. The computer program product comprises a computer program which when executed by a processor performs the above steps.

According to the detection method, the detection circuit, the computer device, the storage medium and the computer program product, the target switch in the first signal selection circuit is started, and other switches are closed; acquiring a first signal through the first ADC sampling circuit, and acquiring a second signal through the first ADC sampling circuit after a standard signal is sent through a first sending circuit if the first signal meets a preset first level condition; if the second signal meets a preset second level condition, the standard signal sent by the first sending circuit is closed, and a third signal is collected through the first ADC sampling circuit; and determining the state of the first port corresponding to the third signal according to the corresponding relation between a preset signal and the port state. The detection method provided by the embodiment of the invention can comprehensively and accurately detect the real-time state of the port without adding an additional detection signal source and avoid the interference of the additional detection signal source.

Drawings

FIG. 1 is a schematic diagram of a detection circuit in one embodiment;

FIG. 2 is a schematic flow chart of a detection method in one embodiment;

FIG. 3 is a schematic diagram of a first signal selection circuit in one embodiment;

FIG. 4 is a flowchart illustrating a step of determining a port status according to a corresponding relationship between a predetermined signal and the port status in one embodiment;

FIG. 5 is a flow chart illustrating the step of determining a port status based on the first signal in one embodiment;

FIG. 6 is a schematic diagram of a detection circuit with two branches in one embodiment;

FIG. 7 is a flowchart illustrating the step of determining the port status based on the second signal according to one embodiment;

FIG. 8 is a schematic diagram of a first signal selection circuit in another embodiment;

FIG. 9 is a schematic diagram of a detection circuit including an ADC drive circuit in one embodiment;

FIG. 10 is a schematic diagram of a detection circuit including a capacitor in one embodiment;

FIG. 11A is a schematic diagram of a detection circuit for transmission through a single port in one embodiment;

FIG. 11B is a schematic diagram of a detection circuit for transmission through a differential port in one embodiment;

FIG. 12 is a schematic flow chart of a detection method in one embodiment;

FIG. 13 is a schematic flow chart of a detection method in another embodiment;

FIG. 14 is a diagram illustrating an internal structure of a computer device according to an embodiment.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

In an embodiment, a detection method is provided, and this embodiment is exemplified by applying the method to a control device, it may be understood that the method may also be applied to a server, and may also be applied to a system including the control device and the server, and is implemented through interaction between the control device and the server, where the control device may be, but is not limited to, various personal computers, notebook computers, smart phones, tablet computers, internet of things devices, and portable wearable devices, and the internet of things devices may be smart speakers, smart televisions, smart air conditioners, smart car-mounted devices, and the like. The portable wearable device can be a smart watch, a smart bracelet, a head-mounted device and the like, and the server can be realized by an independent server or a server cluster formed by a plurality of servers.

Specifically, the detection method provided in this embodiment may be applied to a control device in a detection circuit, where the detection circuit is an ethernet interface circuit to be detected, and the ethernet interface circuit to be detected includes a first transmitting chip and a second transmitting chip.

As shown in fig. 1, the first transmitting chip includes a first transmitting circuit 200, a first port 100, a first received signal processing circuit 300, a first signal selection circuit 400, and a first ADC sampling circuit 500; the first port 100 is connected to a first end of the first received signal processing circuit 300, the first transmitting circuit 200 is connected to a first end of the first received signal processing circuit 300, the first port 100 is connected to a first end of the first signal selecting circuit 400, the first transmitting circuit 200 is connected to a first end of the first signal selecting circuit 400, a second end of the first received signal processing circuit 300 is connected to a second end of the first signal selecting circuit 400, a third end of the first signal selecting circuit 400 is connected to the first ADC sampling circuit 500, the first transmitting chip is connected to the second transmitting chip 30 through the common mode choke coil 50, and the first signal selecting circuit 400 includes a plurality of switches.

The second transmitting chip 30 may transmit a TRX signal to the first transmitting chip 10 through the common mode choke 50, where a flow direction of the TRX signal inside the first transmitting chip 10 may be: the first port transmits the TRX signal to the first signal selection circuit 400 and the first received signal processing circuit 300, respectively, the first received signal processing circuit 300 processes the TRX signal to obtain an RX signal, and transmits the RX signal to the first signal selection circuit 400. The signal transmitted by the first signal selection circuit 400 to the first ADC sampling circuit 500 may be an R signal.

The detection method provided by the embodiment of the invention, as shown in fig. 2, comprises the following steps:

step 102, starting a target switch in the first signal selection circuit, and closing other switches.

Wherein the first signal selection circuit may be a mux circuit for selecting the input signal by the control signal. The circuit connection diagram inside the first signal selection circuit may be as shown in fig. 3, and the first signal selection circuit includes a first switch (SW _ TRX) and a second switch (SW _ RX). The first end of the first signal selection circuit is connected with the first end of the first switch, the second end of the first signal selection circuit is connected with the first end of the second switch, and the second end of the first switch and the second end of the second switch are connected with the third end of the first signal selection circuit. Thus, the switch SW _ TRX selects the signal TRX, and the switch SW _ RX selects the signal RX. The control device can select to make the TRX signal pass through by controlling the activation of the switch SW _ TRX; or the TRX signal is not passed by controlling the closing of the switch SW _ TRX. The signal output by the first signal selection circuit is an R signal.

Specifically, the target switch may be the second switch, and the other switches may be the first switch and the third switch. The control device activates the second switch (SW _ RX) and deactivates the first switch (SW _ TRX).

And 104, acquiring a first signal through the first ADC sampling circuit, and acquiring a second signal through the first ADC sampling circuit after the first signal is transmitted through the first transmitting circuit if the first signal does not meet a preset first level condition.

Wherein, the first ADC sampling circuit is used for collecting digital signals, the standard signal is PAM3 signal used in the Ethernet interface circuit,

specifically, the control device cannot determine whether the second transmitting chip is in a state of transmitting a signal or in a state of not transmitting a signal. Therefore, the control device needs to acquire the first signal through the first ADC sampling circuit, for example, a signal with a preset length is acquired. In this way, the control device determines whether the acquired first signal meets a preset first level condition, wherein the preset first level condition is that the first signal is a standard signal, or the level of the first signal is a zero level, or the level of the first signal is any one of power supply levels.

In one example, the specific process of the control device determining that the first signal does not satisfy the preset first level condition may be: in a case where the control means determines that the first signal is not the standard signal, and the level of the first signal is not the zero level, and the level of the first signal is not the power supply level, the control means may determine that the first signal does not satisfy a preset first level condition, so that the control means may cause the first transmitting chip to transmit the standard signal through the first transmitting circuit. After the first transmitting chip is enabled to transmit the standard signal, the control device acquires the signal again through the first ADC sampling circuit, namely the second signal.

The standard signal is a PAM3 signal used in the ethernet interface circuit, and the PAM3 signal is a three-level signal, which is a negative one code, a zero code, and a positive one code. The level of the zero code signal is the level of the predetermined common mode signal, the level of the negative code signal is the difference between the level of the predetermined common mode signal and the target level value, and the level of the positive code signal is the level of the predetermined common mode signal and the target level value (x) And, the target level value may be a first target multiple of the level value of the preset standard signal, for example, the target level value may be 3/2 times the level of the PAM signal. Thus, the level of the zero code signal (0 code) is the VCM level, and the level of the-1 code signal can be obtained from the level of the PAM signal and the VCM level, and can be, for example, the VCM-PAM3/2 level (VCM-x). The level of the 1-code signal can be obtained according to the level of the PAM signal and the VCM level, and can be VCM + PAM3/2 powerFlat (VCM +x）。

And 106, if the second signal meets a preset second level condition, closing the standard signal sent by the first sending circuit, and acquiring a third signal through the first ADC sampling circuit.

Specifically, the preset second level condition may be: the second signal is a standard signal of a second target multiple, for example, in the case where the standard signal is a PAM3 signal, the second target multiple may be 2. Thus, if the level of the negative-one code signal of the second signal is the difference (VCM-2) between the level of the predetermined common mode signal and the 2 times target level valuex) The level of the positive code signal is the sum (VCM + 2) of the level of the predetermined common mode signal and a 2-fold target level valuex) The control device may determine that the second signal is a 2 × pam3 signal, that is, may determine that the second signal satisfies a preset second level condition.

In this way, in the case where the control device determines that the second signal satisfies the preset second level condition, the control device needs to turn off the first transmitting chip to transmit the standard signal through the first transmitting circuit, even if the first transmitting chip stops transmitting the standard signal. After the first transmitting chip customizes the transmitting standard signal, the control device acquires the signal, namely the third signal, again through the first ADC sampling circuit.

And step 108, determining the state of the first port corresponding to the third signal according to the corresponding relation between the preset signal and the port state.

Specifically, the corresponding relationship between the preset signal and the port state may be that, if the level of the signal is the level of the preset common mode signal, the port state is determined to be an open circuit state; if the level of the signal is not the level of the preset common mode signal, it is determined that the port state is a normal state.

In one example, the first port is determined to be in an open state if the control means determines that the level of the collected third signal is the VCM level, and the first port is determined to be in a normal state if the control means determines that the level of the collected third signal is not the VCM level.

In this embodiment, the target switch in the first signal selection circuit is activated, and other switches are closed; acquiring a first signal through the first ADC sampling circuit, and acquiring a second signal through the first ADC sampling circuit after a standard signal is sent through a first sending circuit if the first signal meets a preset first level condition; if the second signal meets a preset second level condition, the standard signal sent by the first sending circuit is closed, and a third signal is collected through the first ADC sampling circuit; and determining the state of the first port corresponding to the third signal according to the corresponding relation between a preset signal and the port state. The detection method provided by the embodiment of the invention can comprehensively and accurately detect the real-time state of the port without adding an additional detection signal source, and avoids the interference of the additional detection signal source.

In one embodiment, as shown in fig. 4, the specific processing procedure of "determining the state of the first port corresponding to the third signal according to the corresponding relationship between the preset signal and the port state" in step 108 includes:

in step 202, if the third signal is a predetermined common mode signal, it is determined that the first port is in an open circuit state.

Specifically, the predetermined common mode signal may be determined according to physical properties of each device in the circuit to be detected, and may be a VCM signal, for example. If the control device determines that the third signal collected at this time is consistent with the preset common mode signal, it may be determined that the first port in the first transmitting chip is in an open state.

In one example, the third signal collected by the control device through the first ADC sampling circuit is changed from the second signal satisfying the preset second level condition to the preset common mode signal, and then the first port is determined to be in the open state.

In step 204, if the third signal is not the predetermined common mode signal, it is determined that the first port is in a normal state.

Specifically, if the control device determines that the third signal collected at this time is inconsistent with the preset common-mode signal, it may be determined that the first port in the first transmitting chip is in a normal state.

In one embodiment, as shown in fig. 5, the method further comprises:

in step 302, if the first signal satisfies a preset first level condition, it is determined that the first port is in a normal state if the first signal is a standard signal.

The preset first level condition may be that the first signal is a standard signal, or the level of the first signal is a zero level, or the level of the first signal is a power supply level.

Specifically, if the control device determines that the first signal collected at this time is consistent with the standard signal, the control device may determine that the first signal satisfies a preset first level condition, and determine that the first port is in a normal state.

In one example, if the first signal collected by the control device through the first ADC sampling circuit is a PAM signal, it may be determined that the first port is in a normal state.

Alternatively, step 304: in a case where the level of the first signal is a zero level, it is determined that the first port is in a short-circuit to ground state.

Specifically, in a case where the control device determines that the level of the first signal is a zero level, the control device may determine that the collected first signal satisfies a preset first level condition, and may determine that the vocabulary first port is in a normal state.

Alternatively, in step 306, in case the level of the first signal is a preset power level, it is determined that the first port is in a short-circuited to the power.

Specifically, in a case where it is determined that the level of the first signal coincides with the preset power supply level, the control device may determine that the first signal satisfies the preset first level condition, and may determine that the first port is in a short-circuited state to the power supply.

In one embodiment, as shown in fig. 6, the first port includes a first sub-port (port 1) and a second sub-port (port 2). Each circuit in the detection circuit is connected through two paths, the first sub-port is arranged on one path, and the second sub-port is arranged on the other path.

Specifically, the first transmitting chip 10 is connected to the second transmitting chip 30 through the common mode choke 20 (CMC), specifically: the first transmitting chip 10 is connected to the common mode choke 20 (CMC) through the cable TRXp, the cable TRXn, and accordingly, the second transmitting chip 30 may also be connected to the common mode choke 20 through a cable, which is not shown in fig. 6.

In the first transmitting chip 10, the first port includes a first sub-port (port 1) and a second sub-port (port 2). Port 1 is connected to the CMC by cable TRXp, and port 2 is connected to the CMC by cable TRXn. Port 1 is a P-port and port 2 is an N-port. The first subport (port 1) is in the first branch and the second subport (port 2) is in the second branch.

The first sub-port (port 1) is connected to the first end of the first received signal processing circuit 300 through a first branch, the first sub-port (port 1) is connected to the first end of the first signal selection circuit 400 through a first branch, and the first transmitting circuit 200 is connected to the first end of the first signal selection circuit 400 through a first branch, and transmits the TRXp signal to the first end of the first signal selection circuit 400; the first transmitting circuit 200 is further connected to a first end of the first received signal processing circuit 300 through a first branch; a second end of the first received signal processing circuit 300 is connected to a second end of the first signal selection circuit 400 through a first branch, and transmits the RXp1 signal to the first signal selection circuit 400; the third terminal of the first signal selection circuit 400 is connected to the first ADC sampling circuit 500 through the first branch, and transmits the Rp1 signal to the first ADC sampling circuit 500. The first signal selection circuit 400 may also be controlled by the Ctrl1 signal.

Similarly, the second sub-port (port 2) is connected to the first terminal of the first received signal processing circuit 300 through a second branch, the second sub-port (port 2) is connected to the first terminal of the first signal selection circuit 400 through a second branch, and the first transmitting circuit 200 is connected to the first terminal of the first signal selection circuit 400 through a second branch, and transmits the TRXn signal to the first terminal of the first signal selection circuit 400; the first transmitting circuit 200 is further connected to the first end of the first received signal processing circuit 300 through a second branch; a second end of the first received signal processing circuit 300 is connected to a second end of the first signal selection circuit 400 through a second branch, and transmits the RXn1 signal to the first signal selection circuit 400; the third terminal of the first signal selection circuit 400 is connected to the first ADC sampling circuit 500 through the second branch, and transmits the Rn1 signal to the first ADC sampling circuit 500.

Optionally, as shown in fig. 6, the first transmitting chip 10 further includes a capacitor. Thus, the first transmitting chip 10 is connected to the common mode choke 20 through a capacitor, and the common mode choke 20 is connected to the second transmitting chip 30; specifically, the first port in the first transmitting chip 10 may be connected to a cable set including the cables TRXp and TRXn through the capacitor. In case the first port comprises a first sub-port (port 1) and a second sub-port (port 2), the capacitor may comprise a first sub-capacitance C1 and a second sub-capacitance C2; port 1 is connected to cable TRXp through a first sub-capacitor C1, and port 2 is connected to cable TRXn through a second sub-capacitor C2.

Accordingly, the step 104 "acquiring the first signal by the first ADC sampling circuit" includes:

and acquiring a first sub-signal corresponding to the first sub-port and acquiring a second sub-signal corresponding to the second sub-port through the first ADC sampling circuit.

Specifically, the third end of the first signal selection circuit is connected with the first ADC sampling circuit through the first branch circuit, and transmits the Rp1 signal to the first ADC sampling circuit; and the third end of the first signal selection circuit is connected with the first ADC sampling circuit through a second branch circuit, and the Rn1 signal is transmitted to the first ADC sampling circuit. The first sub-port may be a P-port, the second sub-port may be an N-port, the control device may collect data on the first branch and the second branch respectively through the first ADC sampling circuit, and the specific process of collecting may be: a first sub-signal (Rp 1) corresponding to a first sub-port (pport) is collected on a first branch and a second sub-signal (Rn 1) corresponding to a second sub-port (nport) is collected on a second branch.

Correspondingly, the detection method further comprises the following steps:

and determining that the first sub-port corresponding to the first sub-signal is in an open circuit state under the condition that the level of the first sub-signal is the level of the preset common-mode signal and the second sub-signal is the standard signal.

Specifically, the control device collects a first sub-signal and a second sub-signal through a first ADC sampling circuit. The control means may determine that the first sub-port on the branch of the first sub-signal is in an open state if the level of the first sub-signal coincides with the level of the preset common mode signal and the second sub-signal coincides with the standard signal.

In one example, if the level of the second sub-signal coincides with the level of the preset common mode signal and the first sub-signal coincides with the standard signal, the control apparatus may determine that the second sub-port on the branch of the second sub-signal is in an open state.

For example, if the control means determines that the level of the collected Rp1 is the VCM level and Rn1 is the PAM3 signal, the control means may determine that the P port is in an open state. Accordingly, if the control means determines that the acquired level of Rn1 is the VCM level and Rp1 is the PAM3 signal, the control means may determine that the N port is the open state.

In this embodiment, the circuit connection state in the port can be comprehensively and accurately detected through different conditions corresponding to the collected second sub-signal and the multiple states of the second sub-signal.

In one embodiment, as shown in fig. 7, the method further comprises:

and 402, if the second signal does not meet the preset second level condition, determining that the first port is in a normal state under the condition that the second signal is the standard signal.

Specifically, if the second signal collected by the control device is not the standard signal of the second target multiple, it may be determined that the second signal does not satisfy the preset second level condition. In a case where it is determined that the second signal does not satisfy the preset second level condition, if the control means determines that the second signal coincides with the standard signal, it may be determined that the first port is in a normal state.

Alternatively, in step 404, in a case that the level of the second signal is the level of the predetermined common mode signal, it is determined that the first sub-port and the second sub-port in the first port are in a short-circuit and floating state.

In one example, the first port includes a first sub-port and a second sub-port. Each circuit in the detection circuit is connected through two paths, the first sub-port is arranged on the first branch, and the second sub-port is arranged on the second branch. Accordingly, if the second signal collected by the control device is not the standard signal of the second target multiple, it may be determined that the second signal does not satisfy the preset second level condition. Under the condition that the second signal is determined not to satisfy the preset second level condition, if the control device determines that the level of the collected second signal is consistent with the level of the preset common-mode signal, it may be determined that the first sub-port and the second sub-port included in the first port are in a short-circuit and floating state.

In one specific example, if Rp1 (Rn 1) receives the VCM level, it represents that P port and N port are shorted and floating.

In the embodiment, the circuit connection state of the port of the transmitting chip can be comprehensively and accurately detected under the conditions that no additional test signal source is added and no interference is caused by the other side signal.

In one embodiment, the first signal selection circuit includes a first switch, a second switch, and a third switch. The first end of the first signal selection circuit is connected with the first end of the first switch, the second end of the first signal selection circuit is connected with the first end of the second switch, the preset ground end is connected with the first end of the third switch, and the second end of the first switch, the second end of the second switch and the second end of the third switch are connected with the third end of the first signal selection circuit.

Step 102 "start the target switch in the first signal selection circuit and close other switches", includes: and starting a second switch in the first signal selection circuit, and closing the first switch and the third switch.

Alternatively, in the case that the first port includes a first sub-port (port 1) and a second sub-port (port 2), as shown in fig. 8, the first signal selection circuit is a connection schematic diagram, and the input signal can be selected by controlling Ctrl1 (a set of control signals), specifically: the first switch (SW _ TRX) includes a first sub-switch (SW _ TRXp) and a second sub-switch (SW _ TRXn), the second switch (SW _ RX) includes a third sub-switch (SW _ RXp) and a fourth sub-switch (SW _ RXn), and the third switch (SW _ VCM) includes a fifth sub-switch (SW _ VCMp) and a sixth sub-switch (SW _ VCMn).

Thus, in the first branch, the first terminal of the first signal selection circuit is connected to the first terminal of the first sub-switch (SW _ TRXp), the second terminal of the first signal selection circuit is connected to the first terminal of the third sub-switch (SW _ RXp), the preset ground terminal (VCM) is connected to the first terminal of the fifth sub-switch (SW _ VCMp), and the second terminal of the first sub-switch (SW _ TRXp), the second terminal of the third sub-switch (SW _ RXp), and the second terminal of the fifth sub-switch (SW _ VCMp) are connected to the third terminal of the first signal selection circuit.

Similarly, in the second branch, the first terminal of the first signal selection circuit is connected to the first terminal of the second sub-switch (SW _ TRXn), the second terminal of the first signal selection circuit is connected to the first terminal of the fourth sub-switch (SW _ RXn), the preset ground terminal (VCM) is connected to the first terminal of the sixth sub-switch (SW _ VCMn), the second terminal of the second sub-switch (SW _ TRXn), the second terminal of the fourth sub-switch (SW _ RXn), and the second terminal of the sixth sub-switch (SW _ VCMn) are connected to the third terminal of the first signal selection circuit.

Specifically, the switch SW _ TRXp (SW _ TRXn) selects the signal TRXp (TRXn), the switch SW _ RXp (SW _ RXn) selects the signal RXp (RXn), and the switch SW _ VCMp (SW _ VCMn) selects the signal fixed level VCM. The switch SW _ TRXp is closed so that the TRXp signal can pass, at which time Rp = TRXp, and the switch SW _ TRXp is open so that the TRXp signal is not allowed to pass, at which time Rp is not equal to TRXp.

In the case where the detection circuit is normally used, the switch SW _ TRXp (SW _ TRXn) is turned off, the switch SW _ RXp (SW _ RXn) is turned on, and the switch SW _ VCMp (SW _ VCMn) is turned off, at which time Rp = RXp (Rn = RXn).

In the case of testing the P port, the control means may turn on the switch SW _ TRXp, turn off the switch SW _ TRXn, turn off the switch SW _ RXp, turn off the switch SW _ RXn, turn off the switch SW _ VCMp, and turn on the switch SW _ VCMn, so that Rp = TRXp, and Rn = VCM in the detection circuit may be caused.

Similarly, in the case of testing the N port, the control device may turn on the switch SW _ TRXn, turn off the switch SW _ TRXp, turn off the switch SW _ RXp, turn off the switch SW _ RXn, turn off the switch SW _ VCMn, and turn on the switch SW _ VCMp, so that Rn = TRXn, rp = VCM in the detection circuit may be made.

In one embodiment, as shown in fig. 1, there is provided a detection circuit comprising: the device comprises a control device, a first transmitting chip and a second transmitting chip, wherein the first transmitting chip comprises a first transmitting circuit, a first port, a first received signal processing circuit, a first signal selection circuit and a first ADC sampling circuit. The first port is connected with the first end of the first received signal processing circuit, the first sending circuit is connected with the first end of the first received signal processing circuit, the first port is connected with the first end of the first signal selection circuit, the first sending circuit is connected with the first end of the first signal selection circuit, the second end of the first received signal processing circuit is connected with the second end of the first signal selection circuit, the third end of the first signal selection circuit is connected with the first ADC sampling circuit, the first transmitting chip is connected with the second transmitting chip through the common mode choke coil, and the first signal selection circuit comprises a plurality of switches.

And the control device is used for starting the target switch in the first signal selection circuit and closing other switches.

The control device is further used for acquiring a first signal through the first ADC sampling circuit, and acquiring a second signal through the first ADC sampling circuit after the first signal meets a preset first level condition and the standard signal is sent through the first sending circuit if the first signal meets the preset first level condition.

And if the second signal meets the preset second level condition, closing the standard signal sent by the first sending circuit, acquiring a third signal through the first ADC sampling circuit, and determining the state of the first port corresponding to the third signal according to the corresponding relation between the preset signal and the port state.

In one embodiment, as shown in fig. 9, the detection circuit further includes a first ADC driving circuit 600.

A first terminal of the first ADC driving circuit 600 is connected to the third terminal of the first signal selecting circuit 400, and a second terminal of the first ADC driving circuit 600 is connected to the first ADC sampling circuit 500.

In one embodiment, as shown in fig. 10, the detection circuit further includes a capacitor, the first transmitting chip 10 is connected to the common mode choke 20 through the capacitor, and the common mode choke 20 is connected to the second transmitting chip 30.

In one embodiment, as shown in fig. 11A, the detection circuit may be transmitted through a differential port, the detection circuit including a first transmitting chip and a second transmitting chip. The first port in the first transmitting chip includes port 1 and port 2, and the second port in the second transmitting chip includes port 3 and port 4. Port 1 is connected to a first end of the CMC (common mode choke) via a capacitor C1 and a cable TRXp, and port 2 is also connected to the first end of the CMC (common mode choke) via a capacitor C2 and a cable TRXn; the port 3 is connected to the second end of the CMC (common mode choke) via the capacitor C3 and the cable TRXp, and the port 4 is also connected to the second end of the CMC (common mode choke) via the capacitor C4 and the cable TRXn. The internal structure of the second transmitting chip is similar to that of the first transmitting chip, and is not described herein again.

In one embodiment, as shown in fig. 11B, the detection circuit may be transmitted through a single port, and the detection circuit includes a first transmitting chip and a second transmitting chip. The first port in the first transmitting chip comprises port 1 and the second port in the second transmitting chip comprises port 3. The port 1 is connected with a first end of the inductor through a capacitor C1 and a cable TRXp; port 3 is connected to the second end of the inductance through capacitor C3 and cable TRXp. The internal structure of the second transmitting chip is similar to that of the first transmitting chip, and is not described herein again.

In one embodiment, as shown in fig. 6, the first port of the detection circuit includes a first sub-port and a second sub-port, and the capacitor includes a first sub-capacitor and a second sub-capacitor. Each circuit in the detection circuit is connected through two paths, the first sub-port is arranged on the first branch, and the second sub-port is arranged on the second branch. The first sub-port is connected with the common mode choke coil through a first sub-capacitor, and the second sub-port is connected with the common mode choke coil through a second sub-capacitor.

The implementation of the above detection method is described below with reference to a detailed embodiment: the practical application scene of the detection method provided by the invention can be a detection scene of the connection state of the vehicle-mounted Ethernet port, the connection state of the Ethernet port is detected by switching the mux circuit (signal selection circuit), and comprehensive open-short circuit port detection can be realized only by a simple switch of the mux circuit without an additional test signal source.

The invention provides a method for detecting the connection state of a vehicle-mounted Ethernet port, which is characterized in that a mux circuit directly inputs a port signal into an ADC (analog to digital converter) driving circuit, and the connection state of the Ethernet port is detected through an ADC sampling result. When the control device detects the ports 1 and 2, the following table 1 (the TXR signal formula of the ports in different connection states when the control device does not send signals) and table 2 (the TXR signal formula of the ports in different connection states when the control device sends signals) show that the formula of the port signals TXR (TXRp or TXRn) in different connection states of the ports is obtained. In the standard 100BASE-T1 protocol, a three-level pulse amplitude modulation code PAM3 (standard signal) is transmitted. The invention firstly calculates the formula of the TXR1 signal when the port is in different states according to whether both sides have the transmission signal, such as the table 1 and the table 2, wherein A is the link gain.

TABLE 1

As can be seen from table 1, when the PAM3 signal is detected, the port is normal, when the 0 signal is detected, the port is short-circuited to ground, and when the VDD (power supply voltage) signal is detected, the port is short-circuited to power, but if the VCM is detected, the port state cannot be determined.

TABLE 2

As can be seen from table 2, if the opposite side also transmits a signal in this method, PAM3+ PAM3/a is likely to be erroneously determined as a 2 × pam3 signal, that is, the port is likely to be erroneously determined as open when the port is normal.

Thus, the invention provides a testing algorithm flow to finish the accurate test of the port.

Specifically, fig. 11A shows chip 1 (left) communicating with chip 2 (right) via differential ports 1 and 2 via differential lines connecting differential ports 3 and 4. The terminal can detect the port 1 and the port 2 of the chip 1, and the chip 1 comprises a transmitting circuit 1, a received signal processing circuit 1, a mux1, an ADC driving circuit 1 and an ADC1. Chip 2 is identical to chip 1. And the direct current blocking capacitors C1 to C4 prevent the working point of the transmitting circuit from deviating. Increasing the CMC removes common mode interference. These, along with the cable, all affect the link attenuation gain a.

In the present embodiment, mux1 (first signal selection circuit) is added, and the input signal is selected by controlling Ctrl1 (a set of control signals), specifically, the switch SW _ TRXp (SW _ TRXn) selects the signal TRXp (TRXn), the switch SW _ RXp (SW _ RXn) selects the signal RXp (RXn), and the switch SW _ VCMp (SW _ VCMn) selects the signal fixed level VCM.

The normal use case switch SW _ TRXp (SW _ TRXn) is off, the switch SW _ RXp (SW _ RXn) is on, and the switch SW _ VCMp (SW _ VCMn) is off, at which time Rp = RXp (Rn = RXn).

A test state, when testing the P (N) port, with switch SW _ TRXp (SW _ TRXn) on, switch SW _ TRXn (SW _ TRXp) off, switch SW _ RXp off, switch SW _ RXn off, switch SW _ VCMp (SW _ VCMn) off, and switch SW _ VCMn (SW _ VCMp) on, at which Rp = TRXp (Rn = TRXn), rn = VCM (Rp = VCM).

As shown in fig. 12, the testing state is switched to, the P port may be tested first, and then the N port may be tested, with the control signals as above.

Step 1, the first transmitting chip (chip 1) itself does not transmit, port 1 (P port) and port 2 (N port) are tested, as can be seen from table 1,

if the Rp1 (Rn 1) receives the PAM3 signal, the P (N) port is normal;

if Rp1 (Rn 1) receives 0 level, it represents that the P (N) port is short-circuited to the ground;

if Rp1 (Rn 1) receives the power level, it represents that the P (N) port is shorted to the power supply.

If Rp1 (Rn 1) receives the VCM level and Rn1 (Rp 1) receives the PAM3 signal, it represents that the P (N) port is open. Otherwise, the port state can not be judged, so the step 2 is carried out.

Step 2, chip 1 sends PAM3 signal by itself, as can be seen from Table 2,

if the Rp1 (Rn 1) receives the PAM3 signal, the P (N) port is normal;

if Rp1 (Rn 1) receives the VCM level, it represents that the P port and the N port are short-circuited and floating;

if Rp1 (Rn 1) receives 2 × pam3 signals, the port is likely to be erroneously determined to be open if the other side also transmits a signal when the other side transmits a signal, and thus step 3 is performed.

And 3, if the 2 × PAM3 signal is detected, closing the signal of the self-control unit.

The P (N) port is open if the 2 × pam3 signal becomes VCM, otherwise the P (N) port is normal.

The invention does not add a complex analog detection circuit, only adds a mux selection circuit, and saves power consumption and area. And (3) no additional test signal is added, only a standard PAM3 signal is used, the expression of the TXR1 signal when the port is in different states is calculated according to whether the double-transmission signal exists, and meanwhile, the influence of the other transmission signal on the normal state of the port is eliminated through the third step of confirmation. The test is comprehensive, reliable, simple and flexible.

In the following, the implementation process of the above detection method may be described in conjunction with another detailed embodiment: the practical application scene of the detection method provided by the invention can be a detection scene of the connection state of the vehicle-mounted Ethernet port, the connection state of the Ethernet port is detected by utilizing the switching of the mux circuit (signal selection circuit), and the comprehensive open-short circuit port detection can be realized only by a simple switch of the mux circuit without an additional test signal source. The signal selection circuit may be, as shown in fig. 3, a circuit for selecting an input signal by controlling Ctrl1 (a set of control signals), specifically, a switch SW _ TRX selection signal TRX and a switch SW _ RX selection signal RX. Normal use case switch SW _ TRX is off and switch SW _ RX is on, when R = RX.

At this time, the test state is switched to, and the port is tested, and the test process may be as shown in fig. 13.

Step 1, the first transmitting chip (chip 1) itself does not transmit signal, the port is tested, as can be seen from table 3,

if the Rp1 receives the PAM3 signal, the port is normal;

if Rp1 receives a 0 level signal, the port is short-circuited to the ground;

if Rp1 receives the power level (VDD), it represents a port short to the power supply.

If Rp1 receives the VCM level, the port state cannot be judged, so step 2 is performed.

TABLE 3

Step 2, chip 1 sends out PAM3 signal by itself, which can be obtained from table 4:

TABLE 4

If the Rp1 receives a PAM3 signal, the port is normal;

if Rp1 receives 2 × pam3 signals, since the other party also transmits signals when the own party transmits signals, the port is easily judged to be normally open, and thus step 3 is performed.

Step 3, if the 2 × pam3 signal is detected, the signal of the first transmitting chip (chip 1) is turned off.

If the 2 × pam3 signal becomes the VCM signal, the port may be determined to be open, otherwise the port is normal.

It should be understood that, although the steps in the flowcharts related to the embodiments as described above are sequentially displayed as indicated by arrows, the steps are not necessarily performed sequentially as indicated by the arrows. The steps are not limited to being performed in the exact order illustrated and, unless explicitly stated herein, may be performed in other orders. Moreover, at least a part of the steps in the flowcharts related to the embodiments described above may include multiple steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, and the execution order of the steps or stages is not necessarily sequential, but may be rotated or alternated with other steps or at least a part of the steps or stages in other steps.

In one embodiment, a computer device is provided, which may be a server, and the internal structure thereof may be as shown in fig. 14. The computer device includes a processor, a memory, and a network interface connected by a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of an operating system and computer programs in the non-volatile storage medium. The database of the computer device is used for storing data of the detection circuit. The network interface of the computer device is used for communicating with an external terminal through a network connection. The computer program is executed by a processor to implement a detection method.

Those skilled in the art will appreciate that the architecture shown in fig. 14 is merely a block diagram of some of the structures associated with the disclosed aspects and is not intended to limit the computing devices to which the disclosed aspects apply, as particular computing devices may include more or less components than those shown, or may combine certain components, or have a different arrangement of components.

In one embodiment, a computer device is further provided, which includes a memory and a processor, the memory stores a computer program, and the processor implements the steps of the above method embodiments when executing the computer program.

In an embodiment, a computer-readable storage medium is provided, on which a computer program is stored which, when being executed by a processor, carries out the steps of the above-mentioned method embodiments.

In an embodiment, a computer program product is provided, comprising a computer program which, when being executed by a processor, carries out the steps of the above-mentioned method embodiments.

It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, databases, or other media used in the embodiments provided herein can include at least one of non-volatile and volatile memory. The nonvolatile Memory may include Read-Only Memory (ROM), magnetic tape, floppy disk, flash Memory, optical Memory, high-density embedded nonvolatile Memory, resistive Random Access Memory (ReRAM), magnetic Random Access Memory (MRAM), ferroelectric Random Access Memory (FRAM), phase Change Memory (PCM), graphene Memory, and the like. Volatile Memory can include Random Access Memory (RAM), external cache Memory, and the like. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM), among others. The databases referred to in various embodiments provided herein may include at least one of relational and non-relational databases. The non-relational database may include, but is not limited to, a block chain based distributed database, and the like. The processors referred to in the embodiments provided herein may be general purpose processors, central processing units, graphics processors, digital signal processors, programmable logic devices, quantum computing based data processing logic devices, etc., without limitation.

The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is specific and detailed, but not construed as limiting the scope of the present application. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, and these are all within the scope of protection of the present application. Therefore, the protection scope of the present application shall be subject to the appended claims.

Claims

1. A detection method, wherein the method is applied to a detection circuit, wherein the detection circuit comprises: the device comprises a control device, a first transmitting chip and a second transmitting chip, wherein the first transmitting chip comprises a first transmitting circuit, a first port, a first received signal processing circuit, a first signal selection circuit and a first ADC sampling circuit; the first port is connected with a first end of the first received signal processing circuit, the first sending circuit is connected with a first end of the first received signal processing circuit, the first port is connected with a first end of the first signal selection circuit, the first sending circuit is connected with a first end of the first signal selection circuit, a second end of the first received signal processing circuit is connected with a second end of the first signal selection circuit, a third end of the first signal selection circuit is connected with the first ADC sampling circuit, the first transmitting chip is connected with the second transmitting chip through a common mode choke coil, and the first signal selection circuit comprises a plurality of switches;

acquiring a first signal through the first ADC sampling circuit, and acquiring a second signal through the first ADC sampling circuit after a standard signal is transmitted through a first transmitting circuit if the first signal does not meet a preset first level condition, wherein the preset first level condition is that the first signal is any one of the standard signal, the level of the first signal is zero level and the level of the first signal is power supply level;

if the second signal meets a preset second level condition, the standard signal sent by the first sending circuit is closed, and a third signal is collected through the first ADC sampling circuit, wherein the preset second level condition is that the second signal is a standard signal of a second target multiple;

determining the state of the first port corresponding to the third signal according to the corresponding relation between a preset signal and the port state;

determining the state of the first port corresponding to the third signal according to the corresponding relationship between the preset signal and the port state, including:

2. The method of claim 1, further comprising:

or, in a case where the level of the first signal is a zero level, determining that the first port is in a state of short-circuited to ground;

or, in case the level of the first signal is a preset power level, determining that the first port is in a short-circuited to a power supply state.

3. The method of claim 2, wherein the first port comprises a first sub-port and a second sub-port; each circuit in the detection circuit is connected through two paths, the first sub-port is arranged on a first branch, and the second sub-port is arranged on a second branch;

the acquiring, by the first ADC sampling circuit, a first signal comprises:

the method further comprises the following steps:

and determining that the first sub-port corresponding to the first sub-signal is in an open state if the level of the first sub-signal is the level of a preset common mode signal and the second sub-signal is the standard signal.

4. The method of claim 3, further comprising:

5. The method of claim 1, wherein the first signal selection circuit comprises a first switch, a second switch, and a third switch;

the first end of the first signal selection circuit is connected with the first end of the first switch, the second end of the first signal selection circuit is connected with the first end of the second switch, the control device is connected with the first end of the third switch, and the second end of the first switch, the second end of the second switch and the second end of the third switch are connected with the third end of the first signal selection circuit;

6. A detection circuit, characterized in that the detection circuit comprises: the device comprises a control device, a first transmitting chip and a second transmitting chip, wherein the first transmitting chip comprises a first transmitting circuit, a first port, a first received signal processing circuit, a first signal selection circuit and a first ADC sampling circuit; the first port is connected with a first end of the first received signal processing circuit, the first sending circuit is connected with a first end of the first received signal processing circuit, the first port is connected with a first end of the first signal selection circuit, the first sending circuit is connected with a first end of the first signal selection circuit, a second end of the first received signal processing circuit is connected with a second end of the first signal selection circuit, a third end of the first signal selection circuit is connected with the first ADC sampling circuit, the first transmitting chip is connected with the second transmitting chip through a common mode choke coil, and the first signal selection circuit comprises a plurality of switches;

the control device is further configured to acquire a first signal through the first ADC sampling circuit, and if the first signal does not satisfy a preset first level condition, acquire a second signal through the first ADC sampling circuit after sending a standard signal through the first sending circuit, where the preset first level condition is that the first signal is any one of the standard signal, a level of the first signal is a zero level, and a level of the first signal is a power supply level;

if the second signal meets a preset second level condition, closing the standard signal sent by the first sending circuit, acquiring a third signal through the first ADC sampling circuit, and determining the state of the first port corresponding to the third signal according to the corresponding relation between the preset signal and the port state, wherein the preset second level condition is that the second signal is a standard signal of a second target multiple;

7. The detection circuit of claim 6, further comprising a first ADC drive circuit;

8. The detection circuit of claim 6, further comprising a capacitor through which the first transmit chip is connected to the common mode choke, the common mode choke being connected to the second transmit chip.

9. The detection circuit of claim 8, wherein the first port comprises a first sub-port and a second sub-port, and the capacitor comprises a first sub-capacitance and a second sub-capacitance; each circuit in the detection circuit is connected through two paths, the first sub-switch and the first sub-port are arranged in one path, and the second sub-switch and the second sub-port are arranged in the other path; the first sub-port is connected with the common mode choke coil through the first sub-capacitor, and the second sub-port is connected with the common mode choke coil through the second sub-capacitor.

10. A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that the processor, when executing the computer program, implements the steps of the method of any of claims 1 to 5.