CN115274435B - Convex silicon carbide MPS device, preparation method thereof and chip - Google Patents
Convex silicon carbide MPS device, preparation method thereof and chip Download PDFInfo
- Publication number
- CN115274435B CN115274435B CN202211159045.4A CN202211159045A CN115274435B CN 115274435 B CN115274435 B CN 115274435B CN 202211159045 A CN202211159045 A CN 202211159045A CN 115274435 B CN115274435 B CN 115274435B
- Authority
- CN
- China
- Prior art keywords
- layer
- silicon nitride
- groove
- silicon
- type epitaxial
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 35
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 35
- 238000002360 preparation method Methods 0.000 title claims abstract description 11
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 116
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 116
- 229910052751 metal Inorganic materials 0.000 claims abstract description 45
- 239000002184 metal Substances 0.000 claims abstract description 45
- 239000007769 metal material Substances 0.000 claims abstract description 21
- 230000000873 masking effect Effects 0.000 claims abstract description 15
- 229910045601 alloy Inorganic materials 0.000 claims abstract description 10
- 239000000956 alloy Substances 0.000 claims abstract description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 46
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 46
- 239000000463 material Substances 0.000 claims description 37
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 37
- 238000000034 method Methods 0.000 claims description 33
- 229920005591 polysilicon Polymers 0.000 claims description 25
- 238000005530 etching Methods 0.000 claims description 22
- 238000000151 deposition Methods 0.000 claims description 19
- 238000011049 filling Methods 0.000 claims description 11
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 9
- 238000000137 annealing Methods 0.000 claims description 9
- 229910052799 carbon Inorganic materials 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 9
- 238000005468 ion implantation Methods 0.000 claims description 8
- 229910052782 aluminium Inorganic materials 0.000 claims description 7
- 150000002500 ions Chemical class 0.000 claims description 5
- 239000002019 doping agent Substances 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 239000002210 silicon-based material Substances 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 12
- -1 aluminum ions Chemical class 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
- 239000000243 solution Substances 0.000 description 3
- 230000008021 deposition Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 239000012634 fragment Substances 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000011084 recovery Methods 0.000 description 2
- 238000010008 shearing Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000001311 chemical methods and process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006386 neutralization reaction Methods 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/6606—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
Abstract
The utility model belongs to the technical field of power devices, a convex silicon carbide MPS device and a preparation method thereof, and a chip are provided, wherein a first groove with the interval between a plurality of grooves larger than the width of the groove is formed on the front surface of an N-type epitaxial layer, the N-type epitaxial layer is etched under the masking of a silicon nitride mask layer formed on the side wall of the first groove, so that a second groove and a third groove which are alternately arranged are formed on the front surface of the N-type epitaxial layer, a first silicon nitride layer is formed in the second groove, a second silicon nitride layer is formed on the side wall of the third groove as the masking, a P-type doped region is formed at the bottom of the third groove, an ohmic metal layer is formed on the P-type doped region, the anti-surge capacity of the device is improved, a Schottky metal material is deposited on the ohmic metal layer and the N-type epitaxial layer to form a Schottky alloy layer, the side wall and the bottom of the groove are formed into a concave Schottky junction, VF is reduced by increasing the area of the Schottky junction, the interval between PN junctions is reduced, and the leakage current of the device is reduced.
Description
Technical Field
The application belongs to the technical field of power devices, and particularly relates to a convex silicon carbide MPS device, a preparation method thereof and a chip.
Background
Silicon carbide MPS is the device that fuses PN junction and schottky, and schottky structure is inserted to its basic cell structure between 2 PN junctions, pinches off the electric field through 2 PN junctions, reduces the electric field strength of schottky department, and the knot possesses lower reverse recovery time and super soft recovery characteristic, compares JBS device, and the PN junction needs extra preparation ohmic contact, when forward opening, helps promoting surge current, is used widely in the power field. Under the era background of carbon peaking and carbon neutralization, the demand of the device is more and more extensive, and the performance of the device is required to be low in VF and leakage current.
However, under the condition of the same current density and low leakage current, the VF can be reduced by increasing the area of the chip, but the cost of the chip is increased, so that the current density is hardly accepted by the market; the size of the Schottky unit cell can be increased, and although the current density is improved, the leakage current is increased; in addition, ohmic contact resistance can be reduced through a shearing and thinning technology, VF is favorably reduced, but fragments are easily generated, and economic cost is not favorably realized; the PN junction injection region can be below 1 mu m by photoetching and etching technology, but the device is mainly produced on a line of 4-6 inches at the present stage, the photoetching and etching line width can not meet the design requirement, how to prepare the PN junction with narrow line width under the present process condition, and improve the proportion of the Schottky diode, and how to prepare the PN junction ohmic contact metal, so as to effectively improve the current density of the silicon carbide MPS device, reduce the leakage current and improve the anti-surge capability, which is a problem to be solved.
Disclosure of Invention
The application aims to provide a convex silicon carbide MPS device, a preparation method thereof and a chip, and aims to solve the problem that the current density of the silicon carbide MPS device cannot be improved, the leakage current is reduced and the anti-surge capacity is improved simultaneously in the conventional silicon carbide MPS device structure.
A first aspect of an embodiment of the present application provides a method for manufacturing a convex silicon carbide MPS device, the method comprising:
forming an N-type epitaxial layer on a silicon carbide substrate, and forming a hard mask layer on the N-type epitaxial layer; the hard mask layer comprises a plurality of first grooves, and the distance between the first grooves is larger than the width of the first grooves;
depositing a silicon nitride material on the hard mask layer and then etching to form a side wall mask layer on the side wall of the first groove;
removing the hard mask layer to form a silicon nitride mask layer, and etching the N-type epitaxial layer under the masking of the silicon nitride mask layer to form second grooves and third grooves which are alternately arranged on the front surface of the N-type epitaxial layer; wherein the width of the third groove is greater than the width of the second groove;
depositing a silicon nitride material and carrying out etching treatment so as to fill the first silicon nitride layer in the second groove and form a second silicon nitride layer on the side wall of the third groove;
under the masking of the silicon nitride mask layer, the first silicon nitride layer and the second silicon nitride layer, performing P-type doped ion implantation on the N-type epitaxial layer to form a P-type doped region at the bottom of the third groove;
filling a silicon oxide material in the third groove to form a silicon oxide layer, and removing the silicon nitride mask layer, the first silicon nitride layer and the second silicon nitride layer;
filling a polycrystalline silicon material between the adjacent silicon oxide layers to form a polycrystalline silicon layer, and removing the silicon oxide layers; wherein the thickness of the polysilicon layer is greater than the depth of the second groove and the third groove;
depositing an ohmic metal material between the adjacent polycrystalline silicon layers to form an ohmic metal layer on the P-type doped region;
and removing the polycrystalline silicon layer, and depositing a Schottky metal material on the ohmic metal layer and the N-type epitaxial layer to form a Schottky alloy layer.
In one embodiment, the first silicon nitride layer has a width equal to a width of the second silicon nitride layer;
the thickness of the first silicon nitride layer is equal to the thickness of the second silicon nitride layer.
In one embodiment, a distance between the second silicon nitride layers in the third groove is equal to a width of the first silicon nitride layer.
In one embodiment, the step of performing P-type doped ion implantation on the N-type epitaxial layer to form a P-type doped region at the bottom of the third groove includes:
under the masking of the silicon nitride mask layer, the first silicon nitride layer and the second silicon nitride layer, performing high-temperature aluminum ion implantation on the N-type epitaxial layer to form the P-type doped region in the N-type epitaxial layer at the bottom of the third groove;
and depositing a carbon film on the P-type doped region, and performing a high-temperature annealing process.
In one embodiment, the step of filling a silicon oxide material in the third recess to form a silicon oxide layer includes:
and depositing a silicon oxide material to form a silicon oxide layer after removing the carbon film, and etching the silicon oxide material under the condition without a mask until the silicon nitride mask layer, the first silicon nitride layer and the second silicon nitride layer are exposed.
In one embodiment, the thickness of the silicon oxide layer after etching is smaller than that of the second silicon nitride layer.
In one embodiment, the step of depositing an ohmic metal material between adjacent polysilicon layers to form an ohmic metal layer on the P-type doped region includes:
filling ohmic metal materials between the polycrystalline silicon layers to fill the grooves between the adjacent polycrystalline silicon layers;
and annealing the ohmic metal material to form an ohmic metal layer, and etching the ohmic metal layer.
In one embodiment, the thickness of the ohmic metal layer is less than the depth of the second and third grooves.
The second aspect of the embodiments herein also provides a convex silicon carbide MPS device made by any of the fabrication methods described above.
The third aspect of the embodiments of the present application also provides a chip comprising a convex silicon carbide MPS device prepared by the preparation method of any one of the above.
In the convex silicon carbide MPS device and the preparation method thereof and the chip provided by the application, the first grooves with the intervals among the grooves larger than the width of the grooves are formed on the front surface of the N-type epitaxial layer, the N-type epitaxial layer is etched under the masking of the silicon nitride mask layer formed on the side wall of the first groove, so that the second grooves and the third grooves which are alternately arranged are formed on the front surface of the N-type epitaxial layer, the first silicon nitride layer is formed in the second grooves, the second silicon nitride layer is formed on the side wall of the third grooves and is used as the masking, the P-type doped region is formed at the bottom of the third grooves, then the ohmic metal layer is formed on the P-type doped region, the surge resistance of the device is improved, the Schottky metal material is deposited on the ohmic metal layer and the N-type epitaxial layer to form the Schottky junctions, the side wall and the bottom of the grooves are formed into the Schottky junctions, VF is reduced by increasing the areas of the Schottky junctions, the intervals among the PN junctions are reduced, and the leakage current of the device is reduced.
Drawings
Fig. 1 is a schematic flow chart of a method for manufacturing a convex silicon carbide MPS device according to an embodiment of the present application.
Fig. 2 is a schematic diagram of forming a hard mask layer 210 according to an embodiment of the present disclosure.
Fig. 3 is a schematic diagram illustrating the formation of a sidewall mask layer 202 according to an embodiment of the present disclosure.
Fig. 4 is a schematic diagram illustrating the hard mask layer 202 being removed according to an embodiment of the present disclosure.
Fig. 5 is a schematic diagram of etching an N-type epitaxial layer 200 according to an embodiment of the present disclosure.
Fig. 6 is a schematic diagram of forming a first silicon nitride layer 310 and a second silicon nitride layer 320 according to an embodiment of the present disclosure.
Fig. 7 is a schematic diagram of forming a P-type doped region 410 according to an embodiment of the present disclosure.
Fig. 8 is a schematic diagram of forming a silicon oxide layer 510 according to an embodiment of the present disclosure.
Fig. 9 is a schematic diagram of a bump structure exposing the front surface of the N-type epitaxial layer 200 according to an embodiment of the present disclosure.
Fig. 10 is a schematic diagram of forming a polysilicon layer 520 according to an embodiment of the present application.
Fig. 11 is a schematic diagram of removing a silicon oxide layer 510 according to an embodiment of the present disclosure.
Fig. 12 is a schematic diagram of forming an ohmic metal layer 530 according to an embodiment of the present disclosure.
Fig. 13 is a schematic diagram of forming a schottky alloy layer 540 according to an embodiment of the present disclosure.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.
It will be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like, refer to an orientation or positional relationship illustrated in the drawings for convenience in describing the present application and to simplify description, and do not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the present application.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
Under the conditions of the same current density and low leakage current, VF can be reduced by increasing the area of the chip, but the cost of the chip is increased, so that the current density is hardly accepted by the market; the size of the Schottky unit cell can be increased, and although the current density is improved, the leakage current is increased; in addition, ohmic contact resistance can be reduced through a shearing and thinning technology, VF is favorably reduced, but fragments are easily generated, and economic cost is not favorably realized; the PN junction injection region can be below 1 mu m by photoetching and etching technology, but the device is mainly produced on a line of 4-6 inches at the present stage, the photoetching and etching line width can not meet the design requirement, how to prepare the PN junction with narrow line width under the present process condition, and improve the proportion of the Schottky diode, and how to prepare the PN junction ohmic contact metal, so as to effectively improve the current density of the silicon carbide MPS device, reduce the leakage current and improve the anti-surge capability, which is a problem to be solved.
The embodiment of the present application provides a method for manufacturing a convex silicon carbide MPS device, and referring to fig. 1, the method in the embodiment includes step S100 to step S800.
In step S100, an N-type epitaxial layer is formed on a silicon carbide substrate, and a hard mask layer is formed on the N-type epitaxial layer.
In the present embodiment, referring to fig. 2, an N-type epitaxial layer 200 is formed on a front surface of a silicon carbide substrate 100, a hard mask layer 210 is formed on a surface of the N-type epitaxial layer 200, the hard mask layer 210 includes a plurality of first grooves 201, the plurality of first grooves 201 penetrate into the N-type epitaxial layer 200, and a distance between adjacent first grooves 201 in the hard mask layer 210 is greater than a width of the first grooves 201.
In one embodiment, the N-type epitaxial layer 200 may be a silicon carbide N-type epitaxial layer, which may be formed by epitaxial growth on the silicon carbide substrate 100.
Specifically, an N-type epitaxial layer 200 is formed on a silicon carbide substrate 200 through epitaxial growth, then a silicon oxide material is deposited on the surface of the N-type epitaxial layer 200 to form a hard mask layer 210, and the hard mask layer 210 is etched at a line width of 1-2um, so that a plurality of first grooves 201 extending into the N-type epitaxial layer 200 are formed on the hard mask layer 210.
In this embodiment, a photoresist may be used as a mask to cover the hard mask layer 210, and then photolithography is performed at a line width of 1-2um to perform a silicon oxide etching process, and a silicon oxide layer obtained after removing the photoresist is the hard mask layer 210, and the pattern of the silicon oxide layer is as shown in fig. 2.
In one embodiment, the first groove 201 has a groove width of 1-2um.
In a specific application embodiment, the groove width of the first groove 201 is smaller than the distance between the adjacent first grooves 201, the groove width represents the distance between the left side wall and the right side wall of the first groove 201, and the distance between the adjacent first grooves 201 represents the distance between the right side wall of the first groove 201 on the left side and the left side wall of the first groove 201 on the right side.
In a specific embodiment, the distance between adjacent first grooves 201 is at least twice the groove width of the first grooves 201.
In step S200, after depositing a silicon nitride material on the hard mask layer, etching is performed to form a sidewall mask layer on the sidewall of the first groove.
In this embodiment, as shown in fig. 3, by depositing a silicon nitride material on the hard mask layer 210 and then performing a photolithography process on the deposited silicon nitride material until the hard mask layer is exposed, since the thicknesses of the deposited silicon nitride material above the hard mask layer 210 and at the bottom of the first groove 201 are the same, the silicon nitride material deposited above the hard mask layer 210 and at the bottom of the first groove 201 can be removed at the same time, so as to form the sidewall mask layer 202 on the sidewall of the first groove 201.
In one embodiment, the deposition thickness of the silicon nitride material is 0.2-0.5um, and the sidewall mask layer 202 made of the silicon nitride material may be formed on the sidewall of the first groove 201 by dry etching.
In a specific application, the deposition thickness of the silicon nitride material determines the width of the sidewall mask layer 202 and also determines the width of the opening to the N-type epitaxial layer 200 at a later time.
In step S300, the hard mask layer is removed to form a silicon nitride mask layer, and the N-type epitaxial layer is etched under the masking of the silicon nitride mask layer, so as to form second grooves and third grooves alternately arranged on the front surface of the N-type epitaxial layer.
In this embodiment, as shown in fig. 4, after the hard mask layer 202 is removed, a silicon nitride mask layer composed of a plurality of sidewall mask layers 202 is formed on the front surface of the N-type epitaxial layer 200, and the plurality of sidewall mask layers 202 constitute silicon carbide trenches with non-uniform widths.
Referring to fig. 5, the N-type epitaxial layer 200 is etched under the mask of the silicon nitride mask layer, and second grooves 203 and third grooves 204 which are alternately arranged may be formed on the front surface of the N-type epitaxial layer 200, where the width of the third grooves 204 is greater than the width of the second grooves 203.
In one embodiment, the depth of the second and third grooves 203 and 204 are the same.
In one embodiment, the depth of the second and third grooves 203 and 204 is 0.2-1um.
In a specific embodiment, the width of the second groove 203 is one third of the width of the third groove 204.
In step S400, a silicon nitride material is deposited and etched to fill the first silicon nitride layer in the second groove and form a second silicon nitride layer on the sidewall of the third groove.
In this embodiment, as shown in fig. 6, a silicon nitride material is deposited in the front direction of the silicon carbide substrate 100, so that the silicon nitride material is covered by the silicon nitride material, and the deposited silicon nitride material is etched by a dry etching process until the sidewall mask layer 202 is exposed, so that the second groove 203 is filled with the first silicon nitride layer 310, and the sidewall of the third groove 204 forms the second silicon nitride layer 320.
In this embodiment, the deposited thickness of the silicon nitride material may completely fill the second groove 203, i.e. the deposited thickness of the silicon nitride material is at least equal to the width of the second groove 203.
In one embodiment, the second silicon nitride layer 320 has a width of 0.3-0.5um.
In one embodiment, the width of the first silicon nitride layer 310 is equal to the width of the second silicon nitride layer 320; the thickness of the first silicon nitride layer 310 is equal to the thickness of the second silicon nitride layer 320.
In one embodiment, the distance between the second silicon nitride layers 320 in the third recess 204 is equal to the width of the first silicon nitride layer 310.
In step S500, under the masking of the silicon nitride mask layer, the first silicon nitride layer, and the second silicon nitride layer, P-type doped ion implantation is performed on the N-type epitaxial layer to form a P-type doped region at the bottom of the third groove.
In the present embodiment, as shown in fig. 7, under the mask of the silicon nitride mask layer, the first silicon nitride layer 310 and the second silicon nitride layer 320, P-type doping ion implantation is performed on the N-type epitaxial layer 200 to form a P-type doping region 410 at the bottom of the third groove 204.
Specifically, the P-type doped region 410 is located in the third recess 204, and the bottom region between the first silicon nitride layers 310 on the two sidewalls thereof extends into the N-type epitaxial layer 200 to form a PN junction with the N-type epitaxial layer 200.
In one embodiment, the depth of the P-type doped region 410 may be 0.2-1um.
In one embodiment, step S500 specifically includes step S510 and step S520.
In step S510, under the masking of the silicon nitride mask layer, the first silicon nitride layer, and the second silicon nitride layer, high temperature aluminum ion implantation is performed on the N-type epitaxial layer to form the P-type doped region in the N-type epitaxial layer at the bottom of the third groove.
In the present embodiment, the P-type dopant ions may be aluminum ions, and the aluminum ions are implanted into the front surface of the N-type epitaxial layer 200 under the mask of the silicon nitride mask layer, the first silicon nitride layer 310 and the second silicon nitride layer 320 and at a high temperature, so as to form a plurality of P-type doped regions 410 on the front surface of the N-type epitaxial layer 200.
In step S520, a carbon film is deposited on the P-type doped region, and a high temperature annealing process is performed.
In the present embodiment, after the front surface of the N-type epitaxial layer 200 is implanted with aluminum ions, a carbon film is deposited on the P-type doped region 410, and a high temperature annealing process is performed.
In one embodiment, the annealing temperature of the high temperature annealing process may be 1000-1200 ℃.
In step S600, a silicon oxide material is filled in the third groove to form a silicon oxide layer, and the silicon nitride mask layer, the first silicon nitride layer, and the second silicon nitride layer are removed.
In this embodiment, as shown in fig. 8, the silicon oxide layer 510 is formed by filling the third recess 204 with a silicon oxide material, and the silicon oxide layer 510 is filled in the third recess 204.
In one embodiment, the thickness of the silicon oxide layer 510 is less than the thickness of the first silicon nitride layer 310.
In a specific application embodiment, the step of filling a silicon oxide material in the third groove to form a silicon oxide layer specifically includes: the carbon film is removed and then a silicon oxide material is deposited to form a silicon oxide layer 510, and the silicon oxide material is etched without a mask until the silicon nitride mask layer, the first silicon nitride layer 310 and the second silicon nitride layer 320 are exposed.
In one embodiment, the thickness of the silicon oxide layer 510 after etching is less than the thickness of the second silicon nitride layer 320.
Referring to fig. 9, the silicon nitride mask layer, the first silicon nitride layer 310 and the second silicon nitride layer 320 are removed by a chemical process suitable for a silicon nitride material, so as to expose the protruding structures on the front surface of the N-type epitaxial layer 200, and two protruding structures are disposed between adjacent silicon oxide layers 510.
In one embodiment, the distance between two protruding structures between adjacent silicon oxide layers 510 is equal to the distance between the silicon oxide layer 510 and its adjacent protruding structures.
In step S700, a polysilicon material is filled between adjacent silicon oxide layers to form a polysilicon layer, and the silicon oxide layers are removed.
In this embodiment, as shown in fig. 10, the trench before the adjacent silicon oxide layers 510 is filled with a polysilicon material to form a polysilicon layer 520, the thickness of the polysilicon layer 520 is greater than the depth of the second and third recesses, and the polysilicon layer 520 covers the two protruding structures between the adjacent silicon oxide layers 510.
As shown in fig. 11, after the silicon oxide layer 510 is removed, a polysilicon trench is formed between the adjacent polysilicon layers 520, and the P-type doped region 410 is located at the bottom of the polysilicon trench.
In one embodiment, the P-type doped region 410 has a width less than the width of the polysilicon trench.
In step S800, an ohmic metal material is deposited between the adjacent polysilicon layers to form an ohmic metal layer on the P-type doped region.
As shown in fig. 12, an ohmic metal layer 530 may be formed on the P-type doped region 410 by filling an ohmic metal material in the polysilicon trench between the adjacent polysilicon layers, and an ohmic contact may be formed between the ohmic metal layer 530 and the P-type doped region 410.
In one embodiment, the ohmic metal layer 530 formed on the P-type doped region 410 has a thickness less than that of the bump structure.
In one embodiment, step S800 specifically includes step S810 and step S820.
In step S810, an ohmic metal material is filled between the polysilicon layers 520 to fill the grooves between the adjacent polysilicon layers 520.
In step S820, an annealing process is performed on the ohmic metal material to form the ohmic metal layer 530, and an etching process is performed on the ohmic metal layer 530.
In the present embodiment, the ohmic metal layer 530 covers the polysilicon layer 520, the ohmic metal material on the polysilicon layer 520 is removed by a metal etching process, and only the ohmic metal layer 530 in the groove between the adjacent polysilicon layers 520 is left, and the thickness of the etched ohmic metal layer 530 is smaller than the height of the protruding structure on the front surface of the N-type epitaxial layer 200.
In one embodiment, the thickness of the ohmic metal layer 530 is less than the depth of the second and third grooves.
In step S900, the polysilicon layer is removed, and a schottky metal material is deposited on the ohmic metal layer and the N-type epitaxial layer to form a schottky alloy layer.
Referring to fig. 13, after the polysilicon layer 520 is removed, the protruding structures are exposed on the front surface of the N-type epitaxial layer 200 again, and two protruding structures integrated with the N-type epitaxial layer 200 are disposed between the adjacent ohmic metal layers 530.
The schottky metal material is deposited again so that the schottky material is filled in the trenches between the raised structures and the trenches between the ohmic metal layer 530 and the raised structures, and covers the raised structures and the ohmic metal layer 530 to form a schottky alloy layer 540.
In this embodiment, after depositing the schottky metal material, a silicon carbide MPS device is prepared as shown in fig. 13, and the structure is formed into a concave trench, so that a concave schottky junction can be formed, the area of the schottky junction is increased, VF of the device can be reduced, the distance between two PN junctions is reduced, leakage current can be reduced, ohmic contact is formed between a P-type doped region and an ohmic metal layer, and the surge resistance of the device is improved.
The embodiment of the present application further provides a convex silicon carbide MPS device, which includes a silicon carbide substrate 100, an N-type epitaxial layer 200, a P-type doped region 410, an ohmic metal layer 530, and a schottky alloy layer 540.
Specifically, the N-type epitaxial layer 200 is formed on the front surface of the silicon carbide substrate 100, the front surface of the N-type epitaxial layer 200 includes a plurality of protruding structures, the plurality of protruding structures and the N-type epitaxial layer 200 are integrally formed, every two protruding structures form a protruding structure group, the distance between two protruding structures in each protruding structure group is a first distance, the distance between adjacent protruding structure groups is a second distance, the second distance is greater than the first distance, an ohmic metal layer 530 is arranged between the adjacent protruding structure groups, a P-type doped region 410 extending into the N-type epitaxial layer 200 is arranged at the bottom of the ohmic metal layer 530, the P-type doped region 410 and the N-type epitaxial layer 200 form a PN junction, the schottky alloy layer 540 covers the front surface of the N-type epitaxial layer 200, a schottky contact is formed between the schottky alloy layer 540 and the N-type epitaxial layer 200, a concave groove is formed by the plurality of protruding structures, a concave schottky junction can be formed after schottky metal is deposited, the area of the schottky junction is increased, VF of the device can be reduced, meanwhile, the distance between two PN junctions can be reduced, leakage current can also be reduced, the P-type doped region and the ohmic contact region can be formed with the ohmic contact, and surge resistance of the schottky metal layer is improved.
In one embodiment, the second distance is 3 times the first distance, and the width of the ohmic metal layer 530 is the first distance.
In one embodiment, the depth of the P-type doped region 410 may be 0.2-1um.
In one embodiment, the P-type dopant ions in the P-type doped region 410 may be aluminum ions.
In one embodiment, the thickness of the ohmic metal layer 530 is less than the height of the raised structures of the front surface of the N-type epitaxial layer 200.
Embodiments also provide a convex silicon carbide MPS device made by any of the fabrication methods described above.
Embodiments also provide a chip comprising a convex silicon carbide MPS device prepared by any of the methods of preparation described above.
According to the convex silicon carbide MPS device, the preparation method thereof and the chip, the first grooves with the intervals among the grooves larger than the width of the grooves are formed in the front face of the N-type epitaxial layer, the N-type epitaxial layer is etched under the masking of the silicon nitride mask layer formed on the side wall of the first groove, the second grooves and the third grooves which are alternately arranged are formed on the front face of the N-type epitaxial layer, the first silicon nitride layer is formed in the second grooves, the second silicon nitride layer is formed on the side wall of the third groove and serves as the masking, the P-type doped region is formed at the bottom of the third groove, the ohmic metal layer is formed on the P-type doped region, the surge resistance of the device is improved, the Schottky metal material is deposited on the ohmic metal layer and the N-type epitaxial layer to form the Schottky alloy layer, the side wall and the bottom of the groove form the concave type Schottky junction, VF is reduced by increasing the area of the Schottky junction, the intervals among PN junctions are reduced, and the leakage current of the device is reduced.
It will be clear to those skilled in the art that, for the convenience and simplicity of description, the division of the doped regions is merely illustrated, and in practical applications, the functional region allocation can be performed by different doped regions according to the requirement, i.e., the internal structure of the device is divided into different doped regions to perform all or part of the functions described above.
In the embodiment, each doped region may be integrated in one functional region, or each doped region may exist alone physically, or two or more doped regions may be integrated in one functional region, and the integrated functional regions may be implemented by using the same type of doped ions, or by using multiple types of doped ions. In addition, the specific names of the doped regions are only for the convenience of distinguishing from each other, and are not used to limit the protection scope of the present application. For a specific working process of the middle doped region in the method for manufacturing the device, reference may be made to a corresponding process in the foregoing method embodiment, which is not described herein again.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.
Claims (10)
1. A method of fabricating a convex silicon carbide MPS device, the method comprising:
forming an N-type epitaxial layer on a silicon carbide substrate, and forming a hard mask layer on the N-type epitaxial layer; the hard mask layer comprises a plurality of first grooves, and the distance between the first grooves is larger than the width of the first grooves;
depositing a silicon nitride material on the hard mask layer and then etching to form a side wall mask layer on the side wall of the first groove;
removing the hard mask layer to form a silicon nitride mask layer, and etching the N-type epitaxial layer under the masking of the silicon nitride mask layer to form second grooves and third grooves which are alternately arranged on the front surface of the N-type epitaxial layer; wherein the width of the third groove is greater than the width of the second groove;
depositing a silicon nitride material and carrying out etching treatment so as to fill the first silicon nitride layer in the second groove and form a second silicon nitride layer on the side wall of the third groove;
under the masking of the silicon nitride mask layer, the first silicon nitride layer and the second silicon nitride layer, performing P-type doped ion implantation on the N-type epitaxial layer to form a P-type doped region at the bottom of the third groove;
filling a silicon oxide material in the third groove to form a silicon oxide layer, and removing the silicon nitride mask layer, the first silicon nitride layer and the second silicon nitride layer;
filling a polycrystalline silicon material between the adjacent silicon oxide layers to form a polycrystalline silicon layer, and removing the silicon oxide layers; wherein the thickness of the polysilicon layer is greater than the depth of the second groove and the third groove;
depositing an ohmic metal material between the adjacent polycrystalline silicon layers to form an ohmic metal layer on the P-type doped region; the thickness of the ohmic metal layer is smaller than the depth of the second groove and the third groove;
and removing the polycrystalline silicon layer, and depositing a Schottky metal material on the ohmic metal layer and the N-type epitaxial layer to form a Schottky alloy layer.
2. The method of manufacturing according to claim 1, wherein a width of the first silicon nitride layer is equal to a width of the second silicon nitride layer;
the thickness of the first silicon nitride layer is equal to the thickness of the second silicon nitride layer.
3. The method of claim 2, wherein a distance between the second silicon nitride layers in the third grooves is equal to a width of the first silicon nitride layer.
4. The method of claim 1, wherein the step of implanting P-type dopant ions into the N-type epitaxial layer to form P-type dopant regions at the bottom of the third recess comprises:
under the masking of the silicon nitride mask layer, the first silicon nitride layer and the second silicon nitride layer, performing high-temperature aluminum ion implantation on the N-type epitaxial layer to form the P-type doped region in the N-type epitaxial layer at the bottom of the third groove;
and depositing a carbon film on the P-type doped region, and performing a high-temperature annealing process.
5. The method according to claim 4, wherein the step of filling the third recess with a silicon oxide material to form a silicon oxide layer comprises:
and depositing a silicon oxide material to form a silicon oxide layer after removing the carbon film, and etching the silicon oxide material under the mask-free condition until the silicon nitride mask layer, the first silicon nitride layer and the second silicon nitride layer are exposed.
6. The method according to claim 5, wherein a thickness of the silicon oxide layer after etching is smaller than a thickness of the second silicon nitride layer.
7. The method according to claim 1, wherein the step of depositing an ohmic metal material between the adjacent polysilicon layers to form an ohmic metal layer on the P-type doped region comprises:
filling ohmic metal materials between the polycrystalline silicon layers to fill the grooves between the adjacent polycrystalline silicon layers;
and annealing the ohmic metal material to form an ohmic metal layer, and etching the ohmic metal layer.
8. The method of claim 7, wherein a thickness of the ohmic metal layer is less than a depth of the second groove and the third groove.
9. A convex silicon carbide MPS device, characterized in that it is produced by the production method according to any one of claims 1 to 8.
10. A chip comprising a convex silicon carbide MPS device prepared by the method of preparation of any of claims 1-8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211159045.4A CN115274435B (en) | 2022-09-22 | 2022-09-22 | Convex silicon carbide MPS device, preparation method thereof and chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211159045.4A CN115274435B (en) | 2022-09-22 | 2022-09-22 | Convex silicon carbide MPS device, preparation method thereof and chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN115274435A CN115274435A (en) | 2022-11-01 |
| CN115274435B true CN115274435B (en) | 2023-01-03 |
Family
ID=83756907
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211159045.4A Active CN115274435B (en) | 2022-09-22 | 2022-09-22 | Convex silicon carbide MPS device, preparation method thereof and chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115274435B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113594263A (en) * | 2021-07-15 | 2021-11-02 | 淄博绿能芯创电子科技有限公司 | Silicon carbide diode and method of manufacture |
| CN116994956B (en) * | 2023-09-26 | 2023-12-05 | 深圳市万微半导体有限公司 | Silicon carbide power device, preparation method thereof and chip |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013017413A1 (en) * | 2011-08-02 | 2013-02-07 | Robert Bosch Gmbh | Super-junction-schottky-pin-diode |
| CN114883392A (en) * | 2022-04-21 | 2022-08-09 | 深圳芯能半导体技术有限公司 | Multi-groove type silicon carbide junction barrier Schottky diode and preparation method thereof |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5580872B2 (en) * | 2006-03-30 | 2014-08-27 | 日本碍子株式会社 | Semiconductor element |
| US7781312B2 (en) * | 2006-12-13 | 2010-08-24 | General Electric Company | Silicon carbide devices and method of making |
| US20160243263A1 (en) * | 2013-09-30 | 2016-08-25 | BOARD OFf REGENTS, THE UNIVERSITY OF TEXAS SYSTEM | Pegylated nanoparticle compositions |
| KR20150078454A (en) * | 2013-12-30 | 2015-07-08 | 현대자동차주식회사 | Schottky barrier diode and method for manufacturing the same |
| KR101802410B1 (en) * | 2016-08-10 | 2017-11-29 | 파워큐브세미(주) | Wide trench type SiC Junction barrier schottky diode and method of manufacturing the same |
| CN109473482A (en) * | 2017-09-08 | 2019-03-15 | 创能动力科技有限公司 | Schottky device and its manufacturing method |
| US20200321478A1 (en) * | 2019-04-05 | 2020-10-08 | AZ Power, Inc | Trench junction barrier schottky diode with voltage reducing layer and manufacturing method thereof |
| CN113838909B (en) * | 2021-08-19 | 2022-10-14 | 深圳深爱半导体股份有限公司 | Groove type primitive cell structure and preparation method |
| CN114464531B (en) * | 2022-04-13 | 2022-06-28 | 深圳芯能半导体技术有限公司 | Method for manufacturing silicon carbide Schottky diode |
| CN114582981B (en) * | 2022-04-24 | 2022-07-19 | 深圳芯能半导体技术有限公司 | Multi-groove silicon carbide JBS device and preparation method thereof |
-
2022
- 2022-09-22 CN CN202211159045.4A patent/CN115274435B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013017413A1 (en) * | 2011-08-02 | 2013-02-07 | Robert Bosch Gmbh | Super-junction-schottky-pin-diode |
| CN114883392A (en) * | 2022-04-21 | 2022-08-09 | 深圳芯能半导体技术有限公司 | Multi-groove type silicon carbide junction barrier Schottky diode and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN115274435A (en) | 2022-11-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN115274435B (en) | Convex silicon carbide MPS device, preparation method thereof and chip | |
| KR100765924B1 (en) | Trench schottky rectifier and method of forming the same | |
| CN115241062B (en) | Convex silicon carbide JBS device, preparation method thereof and chip | |
| KR100884078B1 (en) | Schottky rectifier and method of forming the same | |
| WO2005065179B1 (en) | Method of manufacturing a superjunction device | |
| US6710419B2 (en) | Method of manufacturing a schottky device | |
| CN109509795B (en) | Silicon carbide schottky device with composite groove structure and manufacturing method thereof | |
| CN111430453A (en) | RC-IGBT chip with good reverse recovery characteristic and manufacturing method thereof | |
| KR100794716B1 (en) | Trench schottky barrier rectifier and method of making the same | |
| CN114582981B (en) | Multi-groove silicon carbide JBS device and preparation method thereof | |
| CN111211168A (en) | RC-IGBT chip and manufacturing method thereof | |
| CN111415997B (en) | MOS structure groove diode device and manufacturing method thereof | |
| KR100288822B1 (en) | Semiconductor device and manufacturing method thereof | |
| CN113193036A (en) | Transistor terminal structure and preparation method thereof | |
| CN115117149B (en) | Fast recovery diode based on wet etching process and preparation method thereof | |
| CN115223868B (en) | High-voltage fast recovery diode and preparation method thereof | |
| CN114899147B (en) | RC-IGBT device and preparation method thereof | |
| CN114446784A (en) | Silicon carbide junction barrier Schottky diode and preparation method thereof | |
| CN114038906A (en) | Schottky diode and preparation method thereof | |
| CN115483294A (en) | Multi-convex silicon carbide JBS device, preparation method thereof and chip | |
| CN213184304U (en) | Semiconductor device | |
| CN216698373U (en) | Schottky diode | |
| US20230420577A1 (en) | Semiconductor device with selectively grown field oxide layer in edge termination region | |
| EP4297096A1 (en) | Semiconductor device and manufacturing method thereof | |
| KR100194691B1 (en) | Semiconductor device and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |