CN115274429A - Semiconductor patterning method - Google Patents
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- CN115274429A CN115274429A CN202210960631.2A CN202210960631A CN115274429A CN 115274429 A CN115274429 A CN 115274429A CN 202210960631 A CN202210960631 A CN 202210960631A CN 115274429 A CN115274429 A CN 115274429A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 238000000059 patterning Methods 0.000 title claims abstract description 15
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 58
- 238000005468 ion implantation Methods 0.000 claims abstract description 41
- 238000005530 etching Methods 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 150000002500 ions Chemical class 0.000 claims description 19
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- 239000001301 oxygen Substances 0.000 claims description 8
- 238000001039 wet etching Methods 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- 238000006243 chemical reaction Methods 0.000 claims description 3
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- 238000004132 cross linking Methods 0.000 claims description 3
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- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 229910021480 group 4 element Inorganic materials 0.000 claims 1
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- 230000008569 process Effects 0.000 abstract description 32
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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Abstract
The embodiment of the application discloses a patterning method for a semiconductor process, which comprises the following steps: providing a semiconductor substrate; forming a layer to be etched on the semiconductor substrate; forming a sacrificial oxide layer on the layer to be etched; forming a photoresist layer on the sacrificial oxide layer; patterning the photoresist layer to enable the sacrificial oxide layer to be provided with an exposed area; etching the photoresist layer, the sacrificial oxide layer and the part of the layer to be etched, which corresponds to the exposed area, by an ion implantation process; and removing the residual photoresist layer and the sacrificial oxide layer to finish etching the layer to be etched. The method and the device can play a role in protecting the side face of the layer to be etched, and avoid the change of the electrical property of the layer to be etched caused by ion implantation.
Description
Technical Field
The present disclosure relates to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor patterning method.
Background
Etching is an important process in the fabrication of semiconductor optoelectronic devices, and its objective is to selectively remove material from the surface of a wafer of semiconductor material by physical or chemical means to form a desired mesa or pattern. The etching process is divided into dry etching and wet etching. The pattern precision and the anisotropy degree of the dry etching are high, and the controllability of each parameter is good. The wet etching has the advantages of good repeatability, simple operation, high etching rate, no toxicity or low toxicity, good repeatability and the like.
For the wafer production process, the etching process often uses photoresist as a mask layer to protect the regions that do not need to be etched and to form a specific pattern. Since the photoresist is expensive, the amount of the photoresist used is usually reduced as much as possible in the process under the condition that sufficient photoresist remains while the requirements of the etching process are ensured, so as to reduce the production cost. Therefore, how to properly protect the non-etching region while reducing the amount of the photoresist becomes an important issue in the art.
Referring to fig. 1A to 1B, schematic diagrams of an etching process performed on a semiconductor device according to the prior art are shown. As shown in fig. 1A, the semiconductor device comprises, from bottom to top, a lower layer 1, a layer to be etched 2, a photoresist layer 3, and a hard shell 4, wherein the lower layer comprises at least a semiconductor substrate. Although the prior art has proposed the formation of a crust on the photoresist surface to protect the non-etched region, this requires precise calculation of the ion implantation angle in consideration of the shadow effect, and once a slight deviation is calculated, the ions are implanted into the sidewall of the layer to be etched (as shown in fig. 1B), which causes the problems of electrical variation and yield reduction. On the other hand, the semiconductor process of fig. 1A requires additional limitation of the implantation energy in the ion implantation process to ensure that the depth of the ion implantation is less than the depth of the etched layer.
In view of the foregoing, there is a need for a novel method of semiconductor patterning that ameliorates the above-mentioned deficiencies.
Disclosure of Invention
In view of the above problems, an object of the present application is to reduce the amount of photoresist used and to prevent the side surface of the trench to be etched from being contaminated by ions after implantation to change the electrical properties of the chip.
In order to achieve the above object, the present application discloses a semiconductor patterning method, which can well improve the problems of the prior art.
Specifically, the embodiment of the present application provides a semiconductor patterning method, including the following steps: providing a semiconductor substrate; forming a layer to be etched on the semiconductor substrate; forming a sacrificial oxide layer on the layer to be etched; forming a photoresist layer on the sacrificial oxide layer; patterning the photoresist layer to enable the sacrificial oxide layer to be provided with an exposed area; carrying out ion implantation on the photoresist layer to enable the surface of the photoresist layer to generate a crust; etching the sacrificial oxide layer and the layer to be etched in the exposed area to form a groove in the exposed area; removing the residual photoresist layer on the sacrificial oxide layer; and removing the sacrificial oxide layer.
Optionally, in some embodiments of the present application, the hard shell is a carbonized cross-linked polymer formed by a cross-linking reaction on a surface of the photoresist layer after ion implantation.
Optionally, in some embodiments of the present application, the removing the photoresist layer is removing the photoresist layer by oxygen plasma.
Optionally, in some embodiments of the present application, the removing the photoresist layer is a wet stripping.
Optionally, in some embodiments of the present application, the removing the sacrificial oxide layer is wet etching.
Optionally, in some embodiments of the present application, a material of the sacrificial oxide layer is silicon oxide, for example, siO2.
Optionally, in some embodiments of the present application, the ion implanted ions include at least one of elements from group III, group IV and group V of the periodic table.
Optionally, in some embodiments of the present application, the model used for the ion implantation includes one of HEI, MCI, and HCI.
Optionally, in some embodiments of the present application, the ion implantation dose is greater than or equal to 10 14 eV。
Optionally, in some embodiments of the present application, a thickness of the sacrificial oxide layer is proportional to the energy.
The scheme provided by the application adds the sacrificial oxide layer to prevent ions from being injected into the lower layer area so as to prevent the part of the non-etching area in the layer to be etched from being etched. In addition, according to different ion implantation energies, ions are prevented from being implanted into the non-etching area of the layer to be etched by adjusting the thickness of the sacrificial oxide layer (for example, increasing the thickness of the sacrificial oxide layer), and the oxide layer is removed by wet etching to finally generate a target pattern. The present application provides the following solutions to the problems of the prior art: because the sacrificial oxide layer is provided, the energy injected in the ion injection process is not required to be limited to ensure that the depth of the ion injection is less than the depth of the etched layer to be etched; in addition, the sacrificial oxide layer can play a role in protecting the side surface of the layer to be etched, and the electrical property of the layer to be etched is prevented from being changed due to ion implantation. The technical key point and the protection point are that the sacrificial oxide layer is added, the hard shell is generated by the method that the to-be-etched layers with different thicknesses can be subjected to ion implantation, the use of photoresist is reduced, meanwhile, the side face of the to-be-etched layer is prevented from being polluted after the ion implantation, and the electrical property of a chip is changed.
In summary, the present application effectively solves the problems of the prior art through the above-mentioned novel scheme, and does not increase much cost, well improves the defects in the prior art in terms of economic benefits, and provides better efficiency in production.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings that are described below in the description of the embodiments and that need to be used are briefly described below, and it is obvious that the drawings in the description below are only some embodiments of the present application, and it is obvious for those skilled in the art that other drawings may be obtained according to these drawings without creative efforts.
Fig. 1A and 1B are schematic diagrams illustrating an etching process performed on a semiconductor device according to the prior art.
Fig. 2A to 2G are schematic diagrams illustrating different stages of an etching process performed on a semiconductor device according to the present application.
Fig. 3 illustrates a patterning method of the semiconductor process corresponding to fig. 2A to 2G.
Description of the symbols:
s302 to S308: a step of; 11: a semiconductor substrate; 12: etching the layer to be etched; 13: sacrificing the oxide layer; 14: a photoresist layer; 15: an exposed area; 16: and (4) hardening.
Detailed Description
The disclosure is described with respect to the following examples, which are intended to be illustrative only, since various modifications and changes in light thereof will be suggested to persons skilled in the art and are to be included within the spirit and purview of this disclosure and scope of the appended claims. Throughout the specification and claims, the terms "a" and "an" and "the" include the recitation of "a" or at least one "of the recited components or ingredients, unless the content clearly dictates otherwise. In addition, as used in this disclosure, the singular articles "a", "an", and "the" include plural referents or components unless the exclusion of plural referents is clear from the particular context. Also, as used in this description and throughout the claims that follow, the meaning of "in" may include "in" and "on" unless the content clearly dictates otherwise. The words used in the specification and claims have the ordinary meaning as is accorded to such words in the art, in the context of the disclosure herein and in the specific context unless otherwise indicated. Certain words used to describe the disclosure are discussed below or elsewhere in this specification to provide additional guidance to the practitioner in describing the disclosure. Examples anywhere throughout the specification, including the use of any examples of words discussed herein, are intended to be illustrative only and certainly do not limit the scope or meaning of the disclosure or any exemplified words. Likewise, the present disclosure is not limited to the various embodiments set forth in this specification.
As used herein, the term "about" or "approximately" shall generally mean within 20%, and preferably within 10%, of a given value or error. Further, the amounts provided herein can be approximate, meaning that the word "about" or "approximately" can be used if not expressly stated. When an amount, concentration, or other value or parameter, is given a range, preferred range or table that sets forth the upper and lower desired values, it is intended that all ranges from any upper and lower pair of values or desired values be specifically disclosed, regardless of whether ranges are separately disclosed. For example, if a range is disclosed having a length of X cm to Y cm, it is contemplated that a length of H cm is disclosed and H can be any real number in between X and Y.
It is understood that the terms "including," "having," "containing," and the like, as used herein, are open-ended terms that mean including, but not limited to. Moreover, not all objects, advantages, or features disclosed herein are necessarily achieved in any one embodiment or claim of the present application. In addition, the abstract and the title of this application are provided to facilitate patent document searching and are not intended to limit the scope of the application.
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application. Furthermore, it should be understood that the detailed description and specific examples, while indicating exemplary embodiments of the invention, are given by way of illustration and explanation only, and are not intended to limit the scope of the invention. In this application, unless indicated to the contrary, the use of the directional terms "upper" and "lower" generally refer to the upper and lower positions of the device in its actual use or operating state, particularly in the direction of the drawing figures, and the terms "inner" and "outer" refer to the contours of the device.
Refer to the drawings wherein like reference numbers refer to like elements throughout. The following description is based on illustrated embodiments of the application and should not be taken as limiting the application with respect to other embodiments that are not detailed herein.
In summary, the technical problem to be solved in the present disclosure is how to reduce the usage amount of the photoresist as much as possible to achieve the required patterning effect, and to avoid the shadow effect (as shown in fig. 1A) from causing unnecessary etching of the non-etching region in the layer to be etched.
Please refer to fig. 2A to fig. 2G, which are schematic diagrams illustrating different stages of an etching process performed on a semiconductor device according to the present application.
First, as shown in fig. 2A, a semiconductor substrate 11 is provided, and a layer to be etched 12 is formed on the semiconductor substrate 11. Wherein the material of the semiconductor substrate 11 is silicon.
Next, as shown in fig. 2B, a sacrificial oxide layer 13 is formed on the layer to be etched 12.
Next, as shown in fig. 2C, a photoresist layer 14 is formed on the sacrificial oxide layer 13, and the photoresist layer 14 is patterned, so that the sacrificial oxide layer 13 has an exposed region 15. Wherein the patterned photoresist layer 14 may be formed by exposure development and masking.
As shown in fig. 2D, the photoresist (containing organic compounds of C, H, and O) of the photoresist layer 14 chemically reacts with the ions through the ion implantation process, so that a hard crust 16 of carbon-containing polymer is formed on the surface of the patterned photoresist layer 14, and the sacrificial oxide layer 13 does not chemically react with the ions, so that the crust 16 is not formed on the surface of the sacrificial oxide layer 13 not covered by the photoresist layer 14. Alternatively, in some embodiments of the present application, the ions implanted in the ion implantation process are preferably at least one of elements in group III, group IV, and group V of the periodic table, but are not limited thereto, as long as ions that can be ion-doped are available. For example, the implanted ions may be one or a combination of H, B, BF2, BF3, BF4, P, as, in, C, ge, N2, sb, F, ne, si.
In some embodiments, the crust 16 may be a carbonized cross-linked polymer formed by a cross-linking reaction at the surface of the photoresist layer after ion implantation. In detail, during the ion implantation, the surface properties of the photoresist may be changed by the ion implantation to generate a so-called "crust". In the case of a larger ion implantation dose, the "crust" formation phenomenon becomes more pronounced.
Optionally, in some embodiments of the present application, the apparatus used in the ion implantation process may be a single-chip type, preferably one of three types, i.e., a high-energy ion implanter (HEI), a medium-beam ion implanter (MCI), and a high-beam ion implanter (HCI), but the present application is not limited thereto, and other types capable of implementing ion implantation are within the protection scope of the present application. The energy range of the ion implantation in the ion implantation process preferably includes energy ranges that can be covered by the three types of HEI, MCI and HCI, but the present application is not particularly limited.
As shown in fig. 2E, after the ion implantation is completed, the non-etched region blocked by the hard shell still has part of the sacrificial oxide layer 13 and the photoresist layer 14; while the sacrificial oxide layer 13 and the photoresist layer 14 in the exposed areas 15 are completely etched.
Then, as shown in fig. 2F and fig. 2G, the residual photoresist layer 14 and the sacrificial oxide layer 13 are removed to complete the whole process. Alternatively, in some embodiments of the present application, oxygen plasma stripping may be used to remove the photoresist layer 14. Furthermore, in other embodiments, the photoresist layer 14 may be removed by a wet stripping process. The oxygen plasma photoresist removing is to generate oxygen plasma under the action of a microwave generator by utilizing oxygen, the active oxygen plasma and an organic polymer generate oxidation reaction, and the organic polymer is oxidized into a water vapor, carbon dioxide and the like to be discharged from a cavity, so that the purpose of removing the photoresist is achieved, and the process is also called ashing or photoresist sweeping. Compared with a wet photoresist removing process, the oxygen plasma photoresist removing process is simpler and has better adaptability, and the photoresist removing process is a pure dry process without liquid or organic solvent.
Optionally, in some embodiments of the present application, the sacrificial oxide layer 13 is removed by wet etching, and the material of the sacrificial oxide layer 13 may be silicon oxide, such as SiO 2 。
Please refer to fig. 3, which is a method of patterning the semiconductor process corresponding to fig. 2A to 2G, comprising the steps of:
step S302: providing a semiconductor substrate, and forming a layer to be etched on the semiconductor substrate;
step S304: forming a sacrificial oxide layer on the layer to be etched, and forming a photoresist layer on the sacrificial oxide layer;
step S306: patterning the photoresist layer to enable the sacrificial oxide layer to be provided with an exposed area;
step S308: etching the photoresist layer, the sacrificial oxide layer and the part of the layer to be etched, which corresponds to the exposed area, by an ion implantation process;
step S310: and removing the residual photoresist layer and the sacrificial oxide layer to complete the etching of the layer to be etched.
Please note that, the application is not limited to follow the above steps completely as long as the same/similar effect can be achieved, for example, some additional steps can be inserted therein and some steps can be omitted under specific conditions.
In summary, the scheme provided by the present application increases the thickness of the sacrificial oxide layer to prevent the ion implantation into the lower layer region, so as to prevent the ion implantation from being performed on the non-etching region of the layer to be etched. In addition, according to different ion implantation doses, ions are prevented from being implanted into the part, not in the etching area, of the layer to be etched by adjusting the thickness of the sacrificial oxide layer, the oxide layer is removed by wet etching, and finally the target pattern is generated. The thickness of the sacrificial oxide layer depends on the dose of the ion implantation process, which is preferably greater than or equal to 10 in order to form a sufficient crust on the photoresist 14 eV, while the thickness of the sacrificial oxide layer should increase as the energy of the ion implantation process increases. In general, the sacrificial oxide layer is grown by a high temperature thermal oxidation process at a temperature of 800-1000 deg.C, and the thickness of the final sacrificial oxide layer is about 100-250 angstroms
Thus, the energy of the ion implantation process is already applied. In summary, the present application provides the following solutions to the problems of the prior art: because the sacrificial oxide layer is provided (as mentioned above, the thin sacrificial oxide layer can be well matched with the high-energy ion implantation), the implantation energy in the ion implantation process does not need to be limited particularly to ensure that the depth of the ion implantation is less than the depth of the etched layer to be etched; in addition, the sacrificial oxide layer can play a role in protecting the side surface of the layer to be etched, and the electrical property of the layer to be etched is prevented from being changed due to ion implantation.
The technical key point and the protection point are that the sacrificial oxide layer is added, the hard shell is generated by the method that the to-be-etched layers with different thicknesses can be subjected to ion implantation, the use of photoresist is reduced, meanwhile, the side face of the to-be-etched layer is prevented from being polluted after the ion implantation, and the electrical property of a chip is changed.
To sum up, the application effectively solves the problem through the novel scheme, does not increase too much cost, well improves the defects in the prior art under the condition of meeting the economic benefit, and provides better experience for users.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to the related descriptions of other embodiments. The embodiments described above are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present application, except for the design of the embodiments in the present application, which is consistent with the embodiments in the present application, belong to the protection scope of the present application.
The foregoing embodiments of the present application have been described in detail, and the principles and implementations of the present application are described herein with reference to specific examples, which are provided only to help understand the technical solutions and their core ideas of the present application. Those of ordinary skill in the art will understand that: it is to be understood that modifications may be made to the technical solutions described in the foregoing embodiments, or equivalents may be substituted for some of the technical features thereof, without departing from the scope of the technical solutions of the embodiments of the present application.
In summary, although the present application has been described with reference to the preferred embodiments, the above-described preferred embodiments are not intended to limit the present application, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, so that the scope of the present application shall be determined by the appended claims.
Claims (10)
1. A method of semiconductor patterning, comprising:
providing a semiconductor substrate;
forming a layer to be etched on the semiconductor substrate;
forming a sacrificial oxide layer on the layer to be etched;
forming a photoresist layer on the sacrificial oxide layer;
patterning the photoresist layer to enable the sacrificial oxide layer to be provided with an exposed area;
carrying out ion implantation on the photoresist layer to generate a crust on the surface of the photoresist layer;
etching the sacrificial oxide layer and the layer to be etched in the exposed area to form a groove in the exposed area;
removing the residual photoresist layer on the sacrificial oxide layer; and
and removing the sacrificial oxide layer.
2. The method of claim 2, wherein the crust is a carbonized crosslinked polymer formed by a crosslinking reaction on the surface of the photoresist layer after ion implantation.
3. The method of claim 1, wherein removing the photoresist layer is by oxygen plasma stripping.
4. The method of claim 1, wherein removing the photoresist layer is a wet strip.
5. The method of claim 1, wherein removing the sacrificial oxide layer is by wet etching.
6. The method of claim 1, wherein the sacrificial oxide layer is silicon oxide.
7. The method of claim 1, wherein the ion implanted ions comprise at least one of group III, group IV, and group V elements of the periodic table.
8. The method of claim 1, wherein the ion implantation is performed in one of a HEI, MCI, and HCI model.
9. As in claimThe method of claim 8, wherein the ion implantation is performed at a dose of 10 or more 14 eV。
10. The method of claim 9, wherein a thickness of the sacrificial oxide layer is proportional to the dose.
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| CN202210960631.2A CN115274429A (en) | 2022-08-11 | 2022-08-11 | Semiconductor patterning method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117059482A (en) * | 2023-10-11 | 2023-11-14 | 粤芯半导体技术股份有限公司 | Silicon dioxide wet etching method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117059482A (en) * | 2023-10-11 | 2023-11-14 | 粤芯半导体技术股份有限公司 | Silicon dioxide wet etching method |
| CN117059482B (en) * | 2023-10-11 | 2024-01-26 | 粤芯半导体技术股份有限公司 | Silicon dioxide wet etching method |
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