CN115273945A - Self-adaptive adjustment deleting voltage algorithm - Google Patents
Self-adaptive adjustment deleting voltage algorithm Download PDFInfo
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- CN115273945A CN115273945A CN202210942029.6A CN202210942029A CN115273945A CN 115273945 A CN115273945 A CN 115273945A CN 202210942029 A CN202210942029 A CN 202210942029A CN 115273945 A CN115273945 A CN 115273945A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
- G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/3468—Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
- G11C16/3472—Circuits or methods to verify correct erasure of nonvolatile memory cells whilst erasing is in progress, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate erasure
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Abstract
The invention discloses an algorithm for adaptively adjusting and deleting voltage; the method comprises the following steps: s1, realizing the first erasing pulse operation, and verifying that the operation does not pass; s2, sequentially increasing the erasing verification voltage, and performing multiple verification operations until verification passes or the verification fails when the preset maximum operation times are reached; s3, recording the number of times of dynamic verification; s4, modulating the voltage of the erasing pulse according to the data value, and performing erasing operation; the dynamic deletion verification performed after the first deletion verification fails can effectively judge the threshold voltage of the storage unit after the pulse is deleted, and the threshold voltage is fed back to the voltage of the next deletion pulse according to the dynamic verification result, so that the purpose of effectively increasing the deletion voltage is achieved, the number of times of deleting the pulse in the whole deletion operation can be reduced, the deletion performance of the storage unit is improved, and the durability of the tunneloxide is enhanced.
Description
Technical Field
The invention belongs to the technical field of storage and deletion, and particularly relates to an algorithm for adaptively adjusting and deleting voltage.
Background
The Nand-flash memory is one of flash memories, and a nonlinear macro-unit mode is adopted in the Nand-flash memory, so that a cheap and effective solution is provided for realizing a solid-state large-capacity memory. The Nand-flash memory has the advantages of large capacity, high rewriting speed and the like, and is suitable for storing a large amount of data, so that the Nand-flash memory is more and more widely applied in the industry, for example, embedded products comprise a digital camera, an MP3 walkman memory card, a small-sized U-disk and the like, but various storage deletion in the market still has various problems.
Existing NAND erase mechanisms: refer to FIGS. 4-5; grounding a Control Gate (CG) of a cell, applying +20V voltage to Pwell, driving electrons on a floating gate by an electric field to be deleted through tunnel oxide, and reducing the VT of the deleted cell; the erase operation performance of the NAND Cell mainly depends on the number of erase pulses required to complete the erase operation, the erase operation performance of the NAND Cell is worse as the number of erase pulses required is larger, the NAND Cell durability mainly depends on the condition of the tunnel oxide, and the tunnel oxide stress is larger as the number of erase pulses is larger, and the durability is also reduced.
Conventional erase operation flow (see fig. 6):
1. starting the erase pulse operation at a lower initial voltage;
2. verifying the threshold voltage of the Cell after the pulse is ended;
3. if the verification is passed, the deleting operation is finished;
4. if the verify fails, the pulse operation is continued by increasing the erase voltage by a fixed value and repeating step 2,3,4.
The defects of the prior art are as follows: the threshold voltage of the memory cell cannot be effectively estimated after the first erase pulse, and the erase pulse result of the first erase pulse cannot be fed back to the voltage of the next erase pulse, so that the erase voltage of the next erase pulse cannot be effectively increased, and therefore, more erase pulse times are required to complete the erase operation, which causes performance degradation and durability degradation of a tunnel oxide layer of the device during the periodic erase operation. For this purpose, we propose an adaptive adjustment erase voltage algorithm.
Disclosure of Invention
The invention aims to provide an algorithm for adaptively adjusting the erase voltage, so as to solve the problems in the background art.
In order to achieve the purpose, the invention provides the following technical scheme: the self-adaptive adjustment deleting voltage algorithm comprises the following steps:
s1, realizing the first erasing pulse operation and verifying: verifying after the first erasing pulse of the deleting operation, and if the verification is passed, finishing the erasing operation; if the verification fails, applying a self-adaptive erasing voltage adjusting algorithm;
s2, sequentially increasing the erasing verification voltage, and performing multiple erasing verification operations: verifying for multiple times after the verification after the first erasing is failed, wherein the voltage on the control grid of the memory unit is increased along with the increase of the current verification times;
s3, recording the times of the erasing pulse: recording the current cycle number when the verification passes or recording the current maximum cycle number when the verification does not pass when the maximum cycle number is reached, wherein the recorded value reflects the threshold voltage of the storage unit at the moment;
s4, modulating the voltage of the erasing pulse according to the data value, and performing erasing operation: and adjusting the next erasing voltage according to the recorded value to achieve the aim of effectively improving the erasing voltage so as to reduce the number of erasing pulses of the whole erasing operation.
Preferably, the erase pulse in S1 is selected to be a low voltage and word line is held at ground to bias the iP-well for erase without requiring a negative voltage, and the physical mechanism is Fowler-Nordheim tunneling.
Preferably, the erase pulse is such that a high electric field is applied to the memory matrix during the erase process in order to achieve a complete erase operation, the erased areas being shifted towards negative Vth values, and in order to minimize the floating gate coupling, it is generally recommended to write after erase, in order to be able to bring the erased areas close to the limit of 0V.
Preferably, the Vth value is such that erased Flash cells have a Vth value below 0V, and written cells have a Vth value below a positive value, and the Vth value is less than 4V, in practice, when 0V is used to bias the gate of a selected cell, all cells in series will conduct current, and only the addressed cell will be erased.
Preferably, the verify operation in S1 is a verify test performed as a sense operation after applying an erase pulse to determine if the Vth value of a memory cell has dropped below a verify voltage, the verify test testing the erase level of a set of nand strings by sensing current in the nand strings.
Preferably, the algorithm for adaptively adjusting the erase voltage in S1 includes two algorithms, which are respectively:
adjusting a base voltage value of the deletion operation according to an adaptive adjustment deletion voltage algorithm;
the fixed voltage difference between each erase pulse of the erase operation is adjusted according to an adaptive erase voltage adjustment algorithm.
Preferably, the voltages in S2 all increase with the increase of the current verification times, that is, the voltage for the initial first erasing is a low voltage, the voltage verification is performed after the erasing, and after the verification does not reach a standard value, the pulse erasing voltage is increased until the pulse erasing can be performed, and the verification passes.
Preferably, the cycle count or the maximum cycle count in S3 is the current operation count after multiple verifications after pulse erasing pass, and the maximum cycle count is the maximum count of multiple verifications that the verification result still fails, and the cycle count is counted by the indicator.
Preferably, the storage unit includes a physical page, the cycle number is written to a spare area of the physical page, if the erase count table of the storage unit is damaged, the cycle number of the storage unit is acquired from the spare area, the cycle number is all integrated together to form a new erase count table again, and the whole erase count table is backed up.
Preferably, the adjustment of the next erase voltage is to erase the memory cell, and the electrons on the floating gate are driven by the electric field to be erased through the tunnel oxide, and the VT of the erased cell is reduced.
Compared with the prior art, the invention has the beneficial effects that:
according to the invention, after the first erasing pulse of the deleting operation is carried out, the dynamic erasing verification operation is carried out according to the current verification result, and then the voltage of the next erasing pulse is adjusted according to the result of the dynamic erasing verification, the threshold voltage of the memory unit after the deleting pulse can be effectively judged through the dynamic erasing verification carried out after the first erasing verification fails, and the threshold voltage is fed back to the voltage of the next erasing pulse according to the dynamic verification result, so that the aim of effectively increasing the erasing voltage is achieved, therefore, the number of times of erasing pulses of the whole erasing operation can be reduced, the erasing performance of the memory unit is improved, and the durability of the tunnel oxide is enhanced.
Drawings
FIG. 1 is a schematic flow chart of the steps of the present invention;
FIG. 2 is a diagram illustrating a basic value of a trimming voltage according to the present invention;
FIG. 3 is a schematic diagram of step size for adjusting the erase voltage according to the present invention;
FIG. 4 is one of the erase mechanisms of the NAND of the present invention;
FIG. 5 is a second schematic diagram illustrating the erase mechanism of the NAND device of the present invention;
FIG. 6 is a diagram illustrating a prior art erase operation of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.
Referring to fig. 1-3, the present invention provides a technical solution: the self-adaptive adjustment deleting voltage algorithm comprises the following steps:
s1, realizing the first erasing pulse operation and verifying: verifying after the first erasing pulse of the deleting operation, and if the verification is passed, finishing the erasing operation; if the verification fails, applying a self-adaptive erasing voltage adjustment algorithm;
s2, sequentially increasing the erasing verification voltage, and performing multiple erasing verification operations: verifying for many times after the verification after the first erasing is not passed, wherein the voltage on the control grid of the memory unit is increased along with the increase of the current verification times when the verification for each time is verified;
s3, recording the times of the erasing pulse: recording the current cycle number when the verification passes or recording the current maximum cycle number when the verification does not pass when the maximum cycle number is reached, wherein the recorded value reflects the threshold voltage of the storage unit at the moment;
s4, modulating the voltage of the erasing pulse according to the data value, and performing erasing operation: and adjusting the next erasing voltage according to the recorded value to achieve the aim of effectively improving the erasing voltage so as to reduce the number of erasing pulses of the whole erasing operation.
In order to implement the erase operation, in this embodiment, it is preferable that the erase pulse in S1 is implemented by selecting a low voltage and keeping word line grounded to bias iP-well, so as to erase without requiring a negative voltage, and the physical mechanism is Fowler-Nordheim tunneling effect.
In order to determine the erase operation, in this embodiment, it is preferable that the erase pulse has a high electric field applied to the memory matrix during the erase operation to complete the erase operation once, and the erased area is shifted toward the negative Vth value.
In order to calculate the voltage of the erase pulse and implement the erase pulse processing, in this embodiment, it is preferable that the Vth value is a Vth value of less than 0V for an erased Flash memory cell, a Vth value of a written memory cell has a positive value, and the Vth value is less than 4V, and in fact, when 0V is used to bias the gate terminal of a selected memory cell, all the memory cells connected in series will conduct current, and only the addressed memory cell will be erased.
In order to implement the verify test of the erase data after the erase pulse, in the present embodiment, it is preferable that the verify operation in S1 is to perform a verify test as a sensing operation after the erase pulse is applied to determine whether the Vth value of the memory cell has dropped below a verify voltage, the verify test testing the erase level of a set of nand strings by sensing the current in the nand strings.
In order to implement adaptive adjustment of the erase pulse, in this embodiment, preferably, the adaptive adjustment erase voltage algorithm in S1 includes two algorithms, which are respectively:
adjusting a basic voltage value of the deleting operation according to an adaptive deleting voltage adjusting algorithm;
the fixed voltage difference between each erase pulse of the erase operation is adjusted according to an adaptive erase voltage adjustment algorithm.
In order to implement voltage adjustment on the current verification times, in this embodiment, preferably, the voltages in S2 all increase as the current verification times increase, that is, the voltage for the initial first erasing is a low voltage, the voltage verification is performed after the erasing, and after the verification does not reach a standard value, the pulse erasing voltage is increased until the pulse erasing can be implemented, and the verification passes.
In order to implement the counting of the number of times of the erase pulse, in this embodiment, it is preferable that the number of cycles in S3 is a current operation number after multiple verification passes after the pulse erase, or a maximum number of cycles, where the maximum number of cycles is a maximum number of times that the multiple verification finds that the verification result still fails, and the number of cycles is counted by the indicator.
In order to implement table recording storage of the number of erased cycles, in this embodiment, it is preferable that the storage unit includes a physical page, the number of cycles is written to a spare area of the physical page, if the erase count table of the storage unit is damaged, the number of cycles of the storage unit is obtained from the spare area, the number of cycles is all integrated together to form a new erase count table again, and the whole erase count table is backed up.
In order to erase data information, in this embodiment, it is preferable that the adjusting the next erase voltage is to erase the memory cell, and electrons on the floating gate are driven by the electric field to be erased through the tunnel oxide, and the VT of the erased cell is reduced.
The working principle and the using process of the invention are as follows:
the first step, the first erasing pulse operation is realized, and the verification is realized: verifying after the first erasing pulse of the deleting operation, and if the verifying is passed, finishing the erasing operation; if the verification fails, applying a self-adaptive erasing voltage adjusting algorithm;
and step two, sequentially increasing the erasing verification voltage, and performing multiple erasing verification operations: verifying for multiple times after the verification after the first erasing is failed, wherein the voltage on the control grid of the memory unit is increased along with the increase of the current verification times;
thirdly, recording the times of erasing pulses: recording the current cycle times when the verification passes or recording the current maximum cycle times when the verification does not pass;
fourthly, modulating the voltage of the erasing pulse according to the data value, and performing erasing operation: and adjusting the next erasing voltage according to the recorded value to achieve the aim of effectively improving the erasing voltage so as to reduce the number of erasing pulses of the whole erasing operation.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (10)
1. The self-adaptive adjustment deleting voltage algorithm is characterized by comprising the following steps of:
s1, realizing the first erasing pulse operation and verifying: verifying after the first erasing pulse of the deleting operation, and if the verification is passed, finishing the erasing operation; if the verification fails, applying a self-adaptive erasing voltage adjusting algorithm;
s2, sequentially increasing the erasing verification voltage, and performing multiple erasing verification operations: verifying for multiple times after the verification after the first erasing is failed, wherein the voltage on the control grid of the memory unit is increased along with the increase of the current verification times;
s3, recording the times of the erasing pulse: recording the current cycle number when the verification passes or recording the current maximum cycle number when the verification does not pass when the maximum cycle number is reached, wherein the recorded value reflects the threshold voltage of the storage unit at the moment;
s4, modulating the voltage of the erasing pulse according to the data value, and performing erasing operation: and adjusting the next erasing voltage according to the recorded value to achieve the aim of effectively improving the erasing voltage so as to reduce the number of erasing pulses of the whole erasing operation.
2. The adaptive adjustment erasure voltage algorithm of claim 1, wherein: the erase pulse in S1 selects a low voltage and keeps word grounded to bias the iP-well to erase without a negative voltage, the physical mechanism is Fowler-Nordheim tunneling.
3. The adaptive adjustment erasure voltage algorithm of claim 1, wherein: the erase pulse applies an electric field to the memory matrix during an erase operation to effect an erase operation, shifting the erased region toward a negative Vth value, and bringing the erased region closer to the 0V limit.
4. The adaptive erasure voltage adjustment algorithm of claim 3, wherein: the Vth value is such that the erased Flash memory cell has a Vth value below 0V, while the Vth of a written cell has a positive value, and the Vth value is less than 4V in magnitude.
5. The adaptive adjustment erasure voltage algorithm of claim 4, wherein: the verify operation in S1 is to perform a verify test as a sense operation after applying an erase pulse to determine if the Vth value of a memory cell has dropped below a verify voltage, the verify test testing the erase level of a set of nand strings by sensing the current in the nand strings.
6. The adaptive adjustment erasure voltage algorithm of claim 1, wherein: the self-adaptive erasing voltage adjusting algorithm in the S1 includes two algorithms, which are respectively:
adjusting a basic voltage value of the deleting operation according to an adaptive deleting voltage adjusting algorithm;
the fixed voltage difference between each erase pulse of the erase operation is adjusted according to an adaptive erase voltage adjustment algorithm.
7. The adaptive adjustment erasure voltage algorithm of claim 1, wherein: and in the S2, the initial voltage for the first erasing is low voltage, the voltage is verified after erasing, and after the verification does not reach a standard value, the pulse erasing voltage is increased until pulse erasing can be realized, and the verification is passed.
8. The adaptive adjustment erasure voltage algorithm of claim 1, wherein: and in the step S3, the cycle number is the current operation number after passing the multiple verification after the pulse erasing, and the maximum cycle number is the maximum number of times that the verification result is still not passed after the multiple verification is found, and the cycle number is counted by the indicator.
9. The adaptive adjustment erasure voltage algorithm of claim 1, wherein: the storage unit comprises a physical page, the cycle times are written to a standby area of the physical page, if an erase count table of the storage unit is damaged, the cycle times of the storage unit are acquired from the standby area, the cycle times are all integrated together to form a new erase count table again, and the whole erase count table is backed up.
10. The adaptive erasure voltage adjustment algorithm of claim 1, wherein: the adjustment of the next erase voltage is to erase the memory cell, and the electrons on the floating gate are driven by the electric field through the tunnel oxide to be erased, and the VT of the erased cell is lowered.
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