CN115270107A - Information verification method and device, readable medium and electronic equipment - Google Patents
Information verification method and device, readable medium and electronic equipment Download PDFInfo
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- CN115270107A CN115270107A CN202211173716.2A CN202211173716A CN115270107A CN 115270107 A CN115270107 A CN 115270107A CN 202211173716 A CN202211173716 A CN 202211173716A CN 115270107 A CN115270107 A CN 115270107A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/30—Authentication, i.e. establishing the identity or authorisation of security principals
- G06F21/44—Program or device authentication
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2221/00—Indexing scheme relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F2221/21—Indexing scheme relating to G06F21/00 and subgroups addressing additional information or applications relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F2221/2133—Verifying human interaction, e.g., Captcha
Abstract
The invention discloses an information verification method, an information verification device, a readable medium and electronic equipment, wherein the method comprises the following steps: determining information to be verified, and writing the information to be verified into a preset storage address; activating a verification platform in response to a write operation to the memory address; the activated verification platform acquires the information to be verified from the storage address and determines a verification result of the SOC by using the information to be verified; the verification platform is activated when the specific storage address is written in, so that the verification platform does not need to actively monitor the storage address, performance resources do not need to be occupied, and the overall operation efficiency of the verification platform is improved; the information to be verified can be written in batch without reserving a larger storage space to store all the information to be verified, and the occupation of the storage space of the SOC is saved.
Description
Technical Field
The invention relates to the technical field of computers, in particular to an information verification method, an information verification device, a readable medium and electronic equipment.
Background
A System On Chip (SOC) is an integrated circuit with a dedicated target. A corresponding verification program (e.g., C-stimulus) may be downloaded to the SOC environment to simulate the operation of the actual circuit, so as to further verify the correctness of the circuit.
In this verification process, the SOC needs to agree with a specific memory address in advance with a verification platform for performing verification. During the process of running the verification program, the SOC writes the information to be verified generated by the running into the memory address. The verification platform needs to keep monitoring the storage address actively, and when the storage address is found to be written into the information to be verified, the information to be verified can be obtained to complete verification.
The prior art has the defect that the verification platform actively monitors whether the storage address is written with the information to be verified, and certain performance resources in the verification platform are occupied, so that the overall operation efficiency of the verification platform is influenced.
Disclosure of Invention
The invention provides an information verification method, an information verification device, a readable medium and electronic equipment, which can improve the overall operation efficiency of a verification platform as much as possible in the verification process.
In a first aspect, the present invention provides an information verification method, including:
determining information to be verified, and writing the information to be verified into a preset storage address;
activating a verification platform in response to a write operation to the memory address; and the activated verification platform acquires the information to be verified from the storage address and determines the verification result of the SOC by using the information to be verified.
Preferably, the determining information to be verified includes:
and running a verification program by utilizing the SOC to determine the information to be verified.
Preferably, the writing the information to be verified into a preset storage address includes:
and writing the information to be verified to the storage address in an ASCII code form by using a printf function.
Preferably, the method further comprises the following steps:
and writing the verification control instruction into the storage address in the form of ASCII code.
Preferably, the activated authentication platform obtaining the information to be authenticated from the storage address further comprises:
the activated authentication platform obtains the authentication control instruction from the storage address.
Preferably, the determining the verification result of the SOC by using the information to be verified includes:
and executing the verification control instruction by using the verification platform so as to determine a verification result of the SOC according to the information to be verified.
Preferably, the verification platform is activated in response to a write operation to the memory address; enabling the activated authentication platform to acquire the information to be authenticated from the storage address comprises:
when the writing operation of the information to be verified written in the storage address starts, sending an activation instruction to the verification platform so that the verification platform is activated;
and when the writing operation of writing the information to be verified into the storage address is finished, acquiring the information to be verified from the storage address by using the verification platform.
In a second aspect, the present invention provides an information verification apparatus, comprising:
the to-be-verified information determining module is used for determining the to-be-verified information;
the writing module is used for writing the information to be verified into a preset storage address;
an activation module to activate a verification platform in response to a write operation to the memory address; and the activated verification platform acquires the information to be verified from the storage address and determines the verification result of the SOC by using the information to be verified.
In a third aspect, the invention provides a readable medium comprising executable instructions, which when executed by a processor of an electronic device, perform the method according to any of the first aspect.
In a fourth aspect, the present invention provides an electronic device, comprising a processor and a memory storing execution instructions, wherein when the processor executes the execution instructions stored in the memory, the processor performs the method according to any one of the first aspect.
The invention provides an information verification method, an information verification device, a readable medium and electronic equipment, wherein a verification platform is activated when a specific storage address is written in, so that the verification platform does not need to actively monitor the storage address, performance resources do not need to be occupied, and the overall operation efficiency of the verification platform is improved; the information to be verified can be written in batch without reserving a larger storage space to store all the information to be verified, and the occupation of the storage space of the SOC is saved.
Further effects of the above-described unconventional preferred modes will be described below in conjunction with the detailed description.
Drawings
In order to more clearly illustrate the embodiments or the prior art solutions of the present invention, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments described in the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive labor.
Fig. 1 is a schematic flowchart of an information verification method according to an embodiment of the present invention;
fig. 2 is a schematic flow chart of an information verification apparatus according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of an electronic device according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be described in detail and completely with reference to the following embodiments and accompanying drawings. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.
In the process of verifying the correctness of the SOC, the SOC needs to agree with a specific memory address in advance with a verification platform. During the operation of the verification program, the SOC writes the information to be verified generated during the operation into the memory address. The verification platform needs to keep monitoring the storage address actively, and when the storage address is found to be written into the information to be verified, the information to be verified can be obtained to complete verification.
The main defect of the prior art is that the verification platform actively monitors whether the storage address is written with the information to be verified, and certain performance resources in the verification platform are occupied, so that the overall operation efficiency of the verification platform is affected. In addition, another drawback of the prior art is that when the SOC and the verification platform agree on a memory address in advance, a large memory space is generally required to be reserved so as to store all the information to be verified generated in the verification process. This also occupies a significant amount of memory resources in the SOC.
In view of the above, the present invention provides an information verification method. Referring to fig. 1, a specific embodiment of an information verification method according to the present invention is shown. In this embodiment, the method includes:
In this embodiment, the SOC is used to run the verification program to determine the information to be verified. That is to say, the information to be verified refers to relevant data information generated in the process of running the verification program, and the correctness of the SOC for the circuit can be verified through the information to be verified.
Among the memory spaces of the SOC, a specific memory address may be beforehand. The memory address is used exclusively for temporarily storing the information to be verified in the method of the present embodiment. I.e., after the SOC generates the information to be verified, it is written to the memory address.
Specifically, the SOC may write the information to be verified in the form of ASCII code to the memory address using a printf function. The printf function is a formatting output function in C language, and can process and output a formatted character string. In this embodiment, an xput function is adaptively used to replace the pushrake function originally included in the printf function, so that the information to be verified is written to the storage address in the form of an ASCII code.
In addition, the SOC cannot directly control the verification platform, so that a verification flow of the verification platform is designed and established. Therefore, the verification control instruction can be further written into the storage address in the form of ASCII code by using the printf function while the information to be verified is written. The verification instruction is a control instruction that can be executed by the verification platform in a subsequent verification process.
For example, the line break is a character string terminator, and when the line break is received, the previously saved character is printed by $ display; stop character string pause simulation, and calling $ stop pause simulation after receiving the stop character string; finish simulation of finish character string, and the like, and call $ finish simulation after receiving the finish character string. The SOC may indirectly override the actual verification process in this manner.
The method in the embodiment is different from the prior art in that whether the information to be verified is written in the storage address is not actively monitored by the verification platform; but when the SOC writes the information to be verified into the memory address, the verification platform is activated in response to the write operation, so that the activated verification platform starts to participate in the subsequent flow. By the method, the phenomenon that the verification platform actively monitors the storage address to occupy performance resources is avoided, and the influence on the overall operation efficiency of the verification platform caused by the performance resources is avoided.
Specifically, the SOC performs a write operation through the SOC bus. When the information to be verified is written to the memory address through the SOC bus, the start of this write operation can be determined according to the communication protocol. Then triggered thereby, an activation instruction may be sent to the verification platform to cause the verification platform to be activated. That is, in this embodiment, only when the specific memory address is written, the verification platform is activated and performs the subsequent related operations. In other cases, the verification platform does not need to actively monitor the storage address, and therefore does not need to occupy performance resources.
And 103, the activated verification platform acquires the information to be verified from the storage address, and determines the verification result of the SOC by using the information to be verified.
The verification platform should learn the storage address. For example, the storage address may be learned by the SOC in advance before being triggered, i.e., the verification platform may be notified after the SOC determines the storage address, similar to the pre-agreed storage address in the prior art. Or the memory address may be learned by the timing of the write operation over the SOC bus after being triggered.
After the verification platform is triggered, the information to be verified can be obtained from the memory address learned by the verification platform. According to the potential signal representing the write operation in the communication protocol of the SOC bus, the verification platform can determine whether the write operation is finished. Therefore, preferably, in this embodiment, the verification platform may acquire the information to be verified by using the verification platform after the write operation of the information to be verified to the memory address is finished. Thereby ensuring that the writing process and the obtaining process of the information to be verified do not interfere with each other.
After the verification platform obtains the information to be verified, the information to be verified can be stored in a memory of the verification platform. Thereby allowing the SOC to release the memory address described above. In addition, in this embodiment, the SOC may further write all the information to be verified in batches into the storage address, and enable the verification platform to acquire the information in batches. And the whole information to be verified can be reintegrated in the memory of the verification platform until all the writing operations and the obtaining operations are finished. Therefore, the SOC only needs to allocate a memory address with a smaller corresponding memory space, and the requirements of the method in the embodiment can be met. It is not necessary to reserve a large storage space to store all the information to be verified, as in the prior art. Therefore, the method in the embodiment can save the occupation of the storage space of the SOC.
After the information to be verified is obtained, the verification platform can perform circuit correctness verification of the SOC according to the information to be verified, and accordingly a corresponding verification result is obtained.
In addition, when the SOC writes information to be verified and writes a verification control instruction to the memory address, the activated verification platform may further obtain the verification control instruction from the memory address. And in the verification process, the verification platform can execute the verification control instruction so as to verify the information to be verified and obtain a verification result. Thus, the SOC indirectly achieves the setting and control of the verification process.
According to the technical scheme, the beneficial effects of the embodiment are as follows: the verification platform is activated when the specific storage address is written in, so that the verification platform does not need to actively monitor the storage address, performance resources do not need to be occupied, and the overall operation efficiency of the verification platform is improved; the information to be verified can be written in batch without reserving a larger storage space to store all the information to be verified, and the occupation of the storage space of the SOC is saved.
Fig. 2 shows an embodiment of an information verification apparatus according to the present invention. The apparatus of this embodiment is a physical apparatus for executing the method described in fig. 1. The technical solution is essentially the same as that in the above embodiment, and the corresponding description in the above embodiment is also applicable to this embodiment. In this embodiment, the apparatus includes:
and the to-be-verified information determining module 201 is configured to determine the to-be-verified information.
The writing module 202 is configured to write the information to be verified into a preset storage address.
An activation module 203 for activating the verification platform in response to a write operation to the memory address; and the activated verification platform acquires the information to be verified from the storage address and determines the verification result of the SOC by using the information to be verified.
In addition, on the basis of the embodiment shown in fig. 2, it is preferable that:
the to-be-verified information determination module 201 includes:
an operation unit 211 for operating the verification program with the SOC.
An information determining unit 212, configured to determine information to be verified.
The writing module 202 includes:
the first writing unit 221 is configured to write the information to be verified to the storage address in the form of ASCII code using a printf function.
And a second writing unit 222 for writing the verification control instruction to the memory address in the form of ASCII code.
The activation module 203 includes:
the platform activation unit 231 is configured to send an activation instruction to the verification platform when a write operation of writing the information to be verified into the storage address starts, so that the verification platform is activated;
the information obtaining module 232 is configured to obtain the information to be verified from the storage address by using the verification platform when the write operation of writing the information to be verified into the storage address is finished.
Fig. 3 is a schematic structural diagram of an electronic device according to an embodiment of the present invention. On the hardware level, the electronic device comprises a processor and optionally an internal bus, a network interface and a memory. The Memory may include a Memory, such as a Random-Access Memory (RAM), and may further include a non-volatile Memory, such as at least 1 disk Memory. Of course, the electronic device may also include hardware required for other services.
The processor, the network interface, and the memory may be connected to each other via an internal bus, which may be an ISA (Industry Standard Architecture) bus, a PCI (Peripheral Component Interconnect) bus, an EISA (Extended Industry Standard Architecture) bus, or the like. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one double-headed arrow is shown in FIG. 3, but this does not indicate only one bus or one type of bus.
And the memory is used for storing the execution instruction. In particular, a computer program that can be executed by executing instructions. The memory may include both memory and non-volatile storage and provides execution instructions and data to the processor.
In a possible implementation manner, the processor reads the corresponding execution instruction from the nonvolatile memory to the memory and then runs the corresponding execution instruction, and the corresponding execution instruction can also be obtained from other equipment so as to form the information verification device on a logic level. The processor executes the execution instruction stored in the memory, so that the information verification method provided by any embodiment of the invention is realized through the executed execution instruction.
The method executed by the information verification apparatus according to the embodiment of the present invention shown in fig. 2 may be applied to or implemented by a processor. The processor may be an integrated circuit chip having signal processing capabilities. In implementation, the steps of the above method may be performed by integrated logic circuits of hardware in a processor or instructions in the form of software. The Processor may be a general-purpose Processor, including a Central Processing Unit (CPU), a Network Processor (NP), and the like; but also Digital Signal Processors (DSPs), application Specific Integrated Circuits (ASICs), field Programmable Gate Arrays (FPGAs) or other Programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components. The various methods, steps and logic blocks disclosed in the embodiments of the present invention may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
The steps of the method disclosed in connection with the embodiments of the present invention may be directly implemented by a hardware decoding processor, or implemented by a combination of hardware and software modules in the decoding processor. The software modules may be located in ram, flash, rom, prom, or eprom, registers, etc. as is well known in the art. The storage medium is located in a memory, and a processor reads information in the memory and combines hardware thereof to complete the steps of the method.
An embodiment of the present invention further provides a readable storage medium, where the readable storage medium stores an execution instruction, and when the stored execution instruction is executed by a processor of an electronic device, the electronic device can be caused to execute the information verification method provided in any embodiment of the present invention, and is specifically configured to execute the method shown in fig. 1.
The electronic device described in the foregoing embodiments may be a computer.
It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as a method or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects.
The embodiments of the present invention are described in a progressive manner, and the same and similar parts among the embodiments can be referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the apparatus embodiment, since it is substantially similar to the method embodiment, the description is relatively simple, and reference may be made to the partial description of the method embodiment for relevant points.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising one of 8230; \8230;" 8230; "does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises that element.
The above description is only an example of the present invention, and is not intended to limit the present invention. Various modifications and alterations to this invention will become apparent to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the claims of the present invention.
Claims (10)
1. An information verification method, comprising:
determining information to be verified, and writing the information to be verified into a preset storage address;
activating a verification platform in response to a write operation to the memory address; and the activated verification platform acquires the information to be verified from the storage address and determines the verification result of the SOC by using the information to be verified.
2. The method of claim 1, wherein the determining information to be verified comprises:
and running a verification program by utilizing the SOC to determine the information to be verified.
3. The method according to claim 1, wherein the writing the information to be verified to a preset storage address comprises:
and writing the information to be verified to the storage address in an ASCII code form by using a printf function.
4. The method of claim 3, further comprising:
and writing the verification control instruction into the storage address in the form of ASCII code.
5. The method of claim 4, wherein the activated authentication platform obtaining the information to be authenticated from the storage address further comprises:
the activated authentication platform obtains the authentication control instruction from the storage address.
6. The method of claim 5, wherein the determining the verification result of the SOC using the information to be verified comprises:
and executing the verification control instruction by using the verification platform so as to determine a verification result of the SOC according to the information to be verified.
7. The method according to any one of claims 1 to 6, wherein a verification platform is activated in response to a write operation to the storage address; so that the activated authentication platform acquiring the information to be authenticated from the storage address comprises:
when the writing operation of the information to be verified written in the storage address begins, sending an activation instruction to the verification platform so as to enable the verification platform to be activated;
and when the writing operation of the information to be verified in the storage address is finished, the verification platform is utilized to obtain the information to be verified from the storage address.
8. An information authentication apparatus, comprising:
the to-be-verified information determining module is used for determining the to-be-verified information;
the writing module is used for writing the information to be verified into a preset storage address;
an activation module to activate a verification platform in response to a write operation to the memory address; and the activated verification platform acquires the information to be verified from the storage address and determines the verification result of the SOC by using the information to be verified.
9. A computer-readable storage medium storing a computer program for executing the information authentication method according to any one of claims 1 to 7.
10. An electronic device, the electronic device comprising:
a processor;
a memory for storing the processor-executable instructions;
the processor is used for reading the executable instructions from the memory and executing the instructions to realize the information verification method of any one of the claims 1 to 7.
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| CN114138570A (en) * | 2021-10-29 | 2022-03-04 | 山东云海国创云计算装备产业创新中心有限公司 | FPGA test method, system, equipment and medium |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2011100351A (en) * | 2009-11-06 | 2011-05-19 | Ricoh Co Ltd | Asic verification apparatus and image forming apparatus |
| CN107797846A (en) * | 2017-09-26 | 2018-03-13 | 记忆科技(深圳)有限公司 | A kind of Soc chip verification methods |
| CN111339731A (en) * | 2020-01-21 | 2020-06-26 | 中国人民解放军军事科学院国防科技创新研究院 | FPGA (field programmable Gate array) verification platform and method for SoC (System on chip) |
| CN114138570A (en) * | 2021-10-29 | 2022-03-04 | 山东云海国创云计算装备产业创新中心有限公司 | FPGA test method, system, equipment and medium |
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