CN114942871A - NFC chip testing method and device, readable medium and electronic equipment - Google Patents

NFC chip testing method and device, readable medium and electronic equipment Download PDF

Info

Publication number
CN114942871A
CN114942871A CN202210847754.5A CN202210847754A CN114942871A CN 114942871 A CN114942871 A CN 114942871A CN 202210847754 A CN202210847754 A CN 202210847754A CN 114942871 A CN114942871 A CN 114942871A
Authority
CN
China
Prior art keywords
power
nfc chip
execution
determining
control flow
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202210847754.5A
Other languages
Chinese (zh)
Inventor
黄金煌
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Beijing Unigroup Tsingteng Microsystems Co Ltd
Original Assignee
Beijing Unigroup Tsingteng Microsystems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Beijing Unigroup Tsingteng Microsystems Co Ltd filed Critical Beijing Unigroup Tsingteng Microsystems Co Ltd
Priority to CN202210847754.5A priority Critical patent/CN114942871A/en
Publication of CN114942871A publication Critical patent/CN114942871A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2273—Test methods
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W4/00—Services specially adapted for wireless communication networks; Facilities therefor
    • H04W4/80—Services using short range communication, e.g. near-field communication [NFC], radio-frequency identification [RFID] or low energy communication
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

The invention discloses a test method, a test device, a readable medium and electronic equipment of an NFC chip, wherein the test method comprises the following steps: determining power failure setting parameters according to the power failure setting information; determining a corresponding control flow according to the power failure setting parameters; when a power-off trigger instruction is received, executing the control flow to control the power supply state of the NFC chip; after the control flow is executed, determining a power-off test result of the NFC chip; the invention realizes the accurate control of the power-off protection test through the control flow, and can accurately control key factors such as the time length, the frequency and the like of the power-off; and the control time for power failure can cover the whole time range of data erasing of the NFC chip, so that the evaluation on the power failure protection function of the NFC chip is more accurate and efficient.

Description

NFC chip testing method and device, readable medium and electronic equipment
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a method and an apparatus for testing an NFC chip, a readable medium, and an electronic device.
Background
NFC (Near Field Communication) is a widely used Communication technology. The NFC chip is the most core hardware structure in the NFC communication technology. The operating environment of the NFC chip is subject to various complicated external factors, so that a sudden power failure may occur in some cases. And the NFC chip needs to carry out high-frequency data erasing and writing when working. Once power failure occurs during data erasing, a serious data risk is faced.
Therefore, the NFC chip needs to have a reliable power-off protection function to ensure data security. Correspondingly, in the design and production process of the NFC chip, the power-off protection function also needs to be tested to ensure the reliability of the power-off protection function.
In the power-off protection test, the NFC chip needs to be powered off according to rules, so that the reliability and the data safety of the NFC chip in a power-off state are judged. The existing power-off protection test of the NFC chip is inaccurate in power-off control, continuous multiple power-off can not be supported usually, and the control time of the power-off can not cover the whole time range of data erasing of the NFC chip.
Disclosure of Invention
The invention provides a test method and device of an NFC chip, a readable medium and electronic equipment, so as to realize more accurate power-off test of the NFC chip.
In a first aspect, the present invention provides a method for testing an NFC chip, including:
determining power-off setting parameters according to the power-off setting information;
determining a corresponding control flow according to the power failure setting parameters;
when a power-off trigger instruction is received, executing the control flow to control the power supply state of the NFC chip;
and after the control flow is executed, determining a power-off test result of the NFC chip.
Preferably, the method further comprises the following steps:
when the power-off trigger instruction is received, a task execution instruction is sent to the NFC chip, so that the NFC chip executes a corresponding communication task;
and determining the execution result of the communication task after the control flow is executed.
Preferably, the determining the power-off test result of the NFC chip includes:
and determining the power-off test result according to the execution result of the communication task.
Preferably, the determining the corresponding control flow according to the power-off setting parameter includes:
determining at least one execution operation which is arranged in sequence in the execution flow according to the power failure setting parameter; and determining the execution condition corresponding to each execution operation.
Preferably, the executing the control flow to control the power supply state of the NFC chip includes:
and when the execution condition corresponding to any one execution operation in the control flow is met, executing the corresponding execution operation to control the power supply state of the NFC chip.
Preferably, the controlling the power supply state of the NFC chip includes:
and controlling the NFC chip to be powered off or controlling the NFC chip to be powered on.
Preferably, the method is applied to a test development board of the NFC chip, and the test development board includes an MCU unit.
In a second aspect, the present invention provides a testing apparatus for an NFC chip, including:
the power failure setting parameter determining module is used for determining power failure setting parameters according to the power failure setting information;
the control flow determining module is used for determining a corresponding control flow according to the power failure setting parameter;
the control flow execution module is used for executing the control flow to control the power supply state of the NFC chip when receiving a power-off trigger instruction;
and the test result determining module is used for determining the power-off test result of the NFC chip after the control flow is executed.
Preferably, the method further comprises the following steps:
the communication task execution module is used for sending a task execution instruction to the NFC chip when receiving the power-off trigger instruction so as to enable the NFC chip to execute a corresponding communication task; and determining the execution result of the communication task after the control flow is executed.
Preferably, the control flow determination module includes:
the execution operation determining unit is used for determining at least one execution operation which is arranged in sequence in the execution flow according to the power failure setting parameter;
and the execution condition determining unit is used for determining the execution condition corresponding to each execution operation according to the power-off setting parameter.
Preferably, the control flow executing module includes:
the power-off execution unit is used for executing corresponding execution operation when the execution condition corresponding to the execution operation in the control flow is met so as to control the NFC chip to be powered off;
and the power-on execution unit is used for executing corresponding execution operation when the execution condition corresponding to the execution operation in the control flow is met so as to control the NFC chip to be powered on.
In a third aspect, the invention provides a readable medium comprising executable instructions which, when executed by a processor of an electronic device, cause the electronic device to perform the method according to any one of the first aspect.
In a fourth aspect, the present invention provides an electronic device, comprising a processor and a memory storing execution instructions, wherein when the processor executes the execution instructions stored in the memory, the processor performs the method according to any one of the first aspect.
The invention provides a test method and a test device of an NFC chip, a readable medium and electronic equipment, which realize the accurate control of power-off protection test through a control flow and can accurately control key factors such as power-off duration, times, frequency and the like; and the control time for power failure can cover the whole time range of data erasing of the NFC chip, so that the evaluation on the power failure protection function of the NFC chip is more accurate and efficient.
Further effects of the above-mentioned unconventional preferred modes will be described below in conjunction with specific embodiments.
Drawings
In order to more clearly illustrate the embodiments or the prior art solutions of the present invention, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments described in the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive labor.
Fig. 1 is a schematic flowchart of a testing method for an NFC chip according to an embodiment of the present invention;
fig. 2 is a schematic flowchart of another testing method for an NFC chip according to an embodiment of the present invention;
fig. 3 is a diagram illustrating an instruction in another testing method for an NFC chip according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a testing apparatus for an NFC chip according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of an electronic device according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be described in detail and completely with reference to the following embodiments and accompanying drawings. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The operating environment of the NFC chip is subject to various complicated external factors, so that a sudden power failure may occur in some cases. And the NFC chip needs to erase and write high-frequency data when working. Once power failure occurs in the data erasing process, the data erasing process is subject to serious data risks such as data errors and data loss.
Therefore, the NFC chip needs to have a reliable power-off protection function to ensure data security. Correspondingly, in the design and production process of the NFC chip, the power-off protection function also needs to be tested to ensure the reliability of the power-off protection function.
In the power-off protection test, the NFC chip needs to be powered off according to rules, so that the reliability and the data safety of the NFC chip in a power-off state are judged. In the conventional power-off protection test of the NFC chip, the control of power-off is not accurate, namely, key factors such as the time length, the frequency and the frequency of power-off cannot be accurately controlled; and for the control time of power failure, the whole time range of data erasing of the NFC chip cannot be covered, and the power failure protection function of the NFC chip is difficult to be accurately evaluated.
In view of this, the present invention provides a method for testing an NFC chip. Fig. 1 shows a specific embodiment of a testing method for an NFC chip according to the present invention.
It should be noted that, from the perspective of hardware, the test method in this embodiment will involve three parties, namely, an upper computer, a test development board for an NFC chip, and an NFC chip. The upper computer body can be a server, a personal computer or other equipment for carrying out necessary setting and macro control for the test method. The test development board is an actual execution platform of the test method and is also a carrying platform of the NFC chip in the test process. An MCU Unit (i.e., Microcontroller Unit) is included in the test development board. The NFC chip is the test object for which the test method is directed. The test method described in this embodiment is applied to a test development board of an NFC chip, that is, the test development board is used as an execution subject of each method step. In the method flow, the test development board is communicated and interacted with the upper computer and the NFC chip.
Specifically, the method in this embodiment includes the following steps:
step 101, determining power failure setting parameters according to power failure setting information.
In the present embodiment, the power-off setting information is generated by the upper computer. The power-off setting information is used for setting a specific power-off mode in the power-off test. Such as the number of power outages, the frequency of power outages, the time of each power outage, the duration of each power outage, and so forth. And the power-off test is carried out according to a specific power-off mode, so that the power-off protection function of the NFC chip can be more accurately measured.
The test development board receives the power-off setting information from the upper computer and determines specific power-off setting parameters according to the power-off setting information. For example, the power down setting parameters may be a specific time node for each power down, and a specific time node for each power up.
And step 102, determining a corresponding control flow according to the power failure setting parameters.
The power-off setting parameters can be set into the control flow by the MCU of the test development board. The MCU can further control the power management unit in the test development board through the control flow, so that the power supply state of the NFC chip is changed by using the power management unit. Therefore, power supply control is carried out on the NFC chip in the whole power-off test process.
For example, in this embodiment, the power-off setting parameters are specific time nodes for each power-off and specific time nodes for each power-on. The control flow is executed, that is, the NFC chip can be controlled to be powered off or powered on in order according to each specific time node in the power-off test process, so that the setting of the power-off setting information on factors such as the number of times of power-off, the frequency of power-off, the time of each power-off, the duration of each power-off and the like is met. Therefore, the method in the embodiment realizes the accurate control of the power-off protection test power-off mode by setting the control flow; and multiple power-off in the test process can be realized by controlling the flow, so that the whole test process is more complete, and more accurate test results can be obtained.
Therefore, the early-stage setting for the specific power-off test is completed in the embodiment, and a precondition is provided for the actual power-off test.
And 103, when a power-off trigger instruction is received, executing the control flow to control the power supply state of the NFC chip.
When the actual power-off test is started, the test development board receives a power-off trigger instruction from the upper computer. And the test development board responds to the power-off trigger instruction and executes the control flow for completing the setting. Namely, the power supply state of the NFC chip is orderly controlled at each specific time node according to the setting in the control flow. The control of the power supply state of the NFC chip mainly includes controlling the NFC chip to be powered off or controlling the NFC chip to be powered on. Of course, in other cases, controlling the power supply state of the NFC chip may also be adjusting the power supply voltage, the power supply circuit or the power supply power of the NFC chip according to the setting, and so on.
In addition, when the test development board receives a power-off trigger instruction from the upper computer, a task execution instruction may be sent to the NFC chip, so that the NFC chip executes a corresponding communication task. For example, the NFC chip may be made register erasable.
That is to say, the test development board can make the NFC chip enter the operating state in the same time period of controlling the power supply state of the NFC chip. In other words, the NFC chip is powered off in the operating state. In this case, the test development board may further determine the execution result of the communication task after the control flow is executed. Namely, the execution result of the communication task by the NFC chip under the condition that the power failure is determined to occur. Thereby learning whether the NFC chip normally performs a communication task if power-off occurs in the middle of the operating state.
And step 104, determining a power-off test result of the NFC chip after the control flow is executed.
After the control flow is executed, in this embodiment, the power-off test result may be determined according to the execution result of the communication task. The execution result is the execution result of the NFC chip on the communication task in the case of power failure. That is, it can be determined from the execution result whether the NFC chip normally executes the communication task if power-off occurs in the operating state.
Namely, if the execution result is normal, even if the NFC chip is powered off in the working state, the communication task can be successfully completed. The power-off protection function of the NFC chip is qualified. Otherwise, if the execution result is abnormal, and a data error or data loss occurs, it indicates that the communication task cannot be successfully completed once the NFC chip is powered off in the working state. The power-off protection function of the NFC chip is unqualified.
So far, the method in this embodiment completes the power-off protection test for the NFC chip.
According to the technical scheme, the beneficial effects of the embodiment are as follows: the accurate control of the power-off protection test is realized through the control flow, and the key factors such as the power-off duration, the power-off frequency and the power-off frequency can be accurately controlled; and the control time for power failure can cover the whole time range of data erasing of the NFC chip, so that the evaluation on the power failure protection function of the NFC chip is more accurate and efficient.
Fig. 1 shows only a basic embodiment of the method of the present invention, and based on this, certain optimization and expansion can be performed, and other preferred embodiments of the method can also be obtained.
Fig. 2 shows another embodiment of the testing method of the NFC chip according to the present invention. The present embodiment is further described on the basis of the foregoing embodiments. In this embodiment, the method includes the steps of:
step 201, determining power failure setting parameters according to the power failure setting information.
In the present embodiment, it is assumed that the power is turned off 2 times in the test process by the power-off setting information, the 1 st power-off is started 30 milliseconds after the command is issued, the duration of each power-off is 20 milliseconds, and the interval of the 2 power-off is 10 milliseconds. The power down setting parameters may be as follows:
time of day (millisecond) 0 30 50 60 80
Give out an instruction Power off Powering on Power off Powering up
Step 202, determining at least one execution operation arranged in sequence in an execution flow according to the power failure setting parameter; and determining the execution condition corresponding to each execution operation.
In the embodiment, the execution operations arranged in sequence in the execution flow are 4 in total, namely power-off-power-on-power-off-power-on. And each execution operation corresponds to an execution condition, namely a corresponding time. For example, the 1 st execution operation is "power off", and the corresponding execution condition is 30 ms (after instruction issue).
And 203, when an execution condition corresponding to any one execution operation in the control flow is met, executing the corresponding execution operation to control the power supply state of the NFC chip.
And when a power-off trigger instruction is received, timing can be started. And judging whether an execution condition corresponding to a certain execution operation is reached. If the execution condition is reached, the corresponding execution operation can be executed. As shown in fig. 3.
In this embodiment, when the time after receiving the power-off trigger instruction reaches 30 milliseconds, the execution condition of the 1 st execution operation is reached, and the NFC chip is controlled to be powered off. At which time the 1 st power down begins at a set time node.
When the time reaches 50 milliseconds, the execution condition of the 2 nd execution operation is reached, and the NFC chip is controlled to be powered on. The 1 st power-off is completed, and the power-off time is 20 milliseconds.
When the time reaches 60 milliseconds, the execution condition of the 3 rd execution operation is reached, and the NFC chip is controlled to be powered off again. At which time the 2 nd power down begins after a set time interval of 10 milliseconds.
When the time reaches 80 milliseconds, the execution condition of the 4 th execution operation is reached, and the NFC chip is controlled to be powered on again. At this point the 2 nd power down is complete.
At this time, the whole execution flow is completed. It can be seen that the power supply state of the NFC chip conforms to the setting of the power-off setting information in the execution process.
And step 204, determining a power-off test result of the NFC chip after the control flow is executed.
In this embodiment, the content in step 204 is the same as the content of the relevant step in the embodiment shown in fig. 1. The description is not repeated again.
Fig. 4 shows a specific embodiment of a testing apparatus for an NFC chip according to the present invention. The apparatus of this embodiment is a physical apparatus for performing the method described in fig. 1 to 3. The technical solution is essentially the same as that in the above embodiment, and the corresponding description in the above embodiment is also applicable to this embodiment. The device in this embodiment includes:
and an outage setting parameter determining module 401, configured to determine an outage setting parameter according to the outage setting information.
And a control flow determining module 402, configured to determine a corresponding control flow according to the power outage setting parameter.
A control flow executing module 403, configured to execute the control flow when receiving the power-off trigger instruction, so as to control a power supply state of the NFC chip.
A test result determining module 404, configured to determine a power-off test result of the NFC chip after the control flow is executed.
In addition, on the basis of the embodiment shown in fig. 4, it is preferable that:
a communication task execution module 405, configured to send a task execution instruction to the NFC chip when the power-off trigger instruction is received, so that the NFC chip executes a corresponding communication task; and determining the execution result of the communication task after the control flow is executed.
The control flow determination module 402 includes:
an execution operation determining unit 421, configured to determine at least one sequentially arranged execution operation in the execution flow according to the power-off setting parameter.
An execution condition determining unit 422, configured to determine, according to the power-off setting parameter, an execution condition corresponding to each of the execution operations.
The control flow execution module 403 includes:
a power-off execution unit 431, configured to execute a corresponding execution operation when an execution condition corresponding to the execution operation in the control flow is met, so as to control the NFC chip to power off.
A power-on execution unit 432, configured to execute the corresponding execution operation when the execution condition corresponding to the execution operation in the control flow is met, so as to control the NFC chip to power on.
Fig. 5 is a schematic structural diagram of an electronic device according to an embodiment of the present invention. On the hardware level, the electronic device comprises a processor and optionally an internal bus, a network interface and a memory. The Memory may include a Memory, such as a Random-Access Memory (RAM), and may further include a non-volatile Memory, such as at least 1 disk Memory. Of course, the electronic device may also include hardware required for other services.
The processor, the network interface, and the memory may be connected to each other via an internal bus, which may be an ISA (Industry Standard Architecture) bus, a PCI (Peripheral Component Interconnect) bus, an EISA (Extended Industry Standard Architecture) bus, or the like. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one double-headed arrow is shown in FIG. 5, but this does not indicate only one bus or one type of bus.
And the memory is used for storing the execution instruction. In particular, a computer program that can be executed by executing instructions. The memory may include both memory and non-volatile storage and provides execution instructions and data to the processor.
In a possible implementation manner, the processor reads corresponding execution instructions from the nonvolatile memory into the memory and then runs the corresponding execution instructions, and corresponding execution instructions can also be obtained from other devices, so as to form the test device of the NFC chip on a logic level. The processor executes the execution instruction stored in the memory, so that the test method of the NFC chip provided in any embodiment of the present invention is implemented by the executed execution instruction.
The method executed by the testing apparatus for the NFC chip according to the embodiment of the present invention shown in fig. 4 may be applied to or implemented by a processor. The processor may be an integrated circuit chip having signal processing capabilities. In implementation, the steps of the above method may be performed by integrated logic circuits of hardware in a processor or by instructions in the form of software. The Processor may be a general-purpose Processor, including a Central Processing Unit (CPU), a Network Processor (NP), and the like; but also Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) or other Programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components. The various methods, steps and logic blocks disclosed in the embodiments of the present invention may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
The steps of the method disclosed in connection with the embodiments of the present invention may be directly implemented by a hardware decoding processor, or implemented by a combination of hardware and software modules in the decoding processor. The software modules may be located in ram, flash, rom, prom, or eprom, registers, etc. as is well known in the art. The storage medium is located in a memory, and a processor reads information in the memory and completes the steps of the method in combination with hardware of the processor.
An embodiment of the present invention further provides a readable storage medium, where the readable storage medium stores an execution instruction, and when the stored execution instruction is executed by a processor of an electronic device, the electronic device can be caused to execute the method for testing an NFC chip provided in any embodiment of the present invention, and is specifically configured to execute the method shown in fig. 1 or fig. 2.
The electronic device described in the foregoing embodiments may be a computer.
It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as a method or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects.
All the embodiments in the invention are described in a progressive manner, and the same and similar parts among the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, as for the apparatus embodiment, since it is substantially similar to the method embodiment, the description is relatively simple, and for the relevant points, reference may be made to the partial description of the method embodiment.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The above description is only an example of the present invention and is not intended to limit the present invention. Various modifications and alterations to this invention will become apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the scope of the claims of the present invention.

Claims (13)

1. A test method of an NFC chip is characterized by comprising the following steps:
determining power-off setting parameters according to the power-off setting information;
determining a corresponding control flow according to the power failure setting parameters;
when a power-off trigger instruction is received, executing the control flow to control the power supply state of the NFC chip;
and after the control flow is executed, determining a power-off test result of the NFC chip.
2. The method of claim 1, further comprising:
when the power-off trigger instruction is received, a task execution instruction is sent to the NFC chip, so that the NFC chip executes a corresponding communication task;
and determining the execution result of the communication task after the control flow is executed.
3. The method of claim 2, wherein the determining the power-down test result of the NFC chip comprises:
and determining the power-off test result according to the execution result of the communication task.
4. The method of claim 1, wherein determining the corresponding control flow according to the power-off setting parameter comprises:
determining at least one execution operation which is arranged in sequence in the execution flow according to the power failure setting parameter; and determining the execution condition corresponding to each execution operation.
5. The method of claim 4, wherein the executing the control flow to control the power state of the NFC chip comprises:
and when the execution condition corresponding to any execution operation in the control flow is met, executing the corresponding execution operation to control the power supply state of the NFC chip.
6. The method according to any one of claims 1 to 5, wherein the controlling the power supply state of the NFC chip comprises:
and controlling the NFC chip to be powered off or controlling the NFC chip to be powered on.
7. The method according to any one of claims 1 to 5, wherein the method is applied to a test development board of the NFC chip, and the test development board comprises an MCU unit.
8. A test device for NFC chips, comprising:
the power failure setting parameter determining module is used for determining power failure setting parameters according to the power failure setting information;
the control flow determining module is used for determining a corresponding control flow according to the power failure setting parameter;
the control flow execution module is used for executing the control flow to control the power supply state of the NFC chip when receiving a power-off trigger instruction;
and the test result determining module is used for determining the power-off test result of the NFC chip after the control flow is executed.
9. The apparatus of claim 8, further comprising:
the communication task execution module is used for sending a task execution instruction to the NFC chip when receiving the power-off trigger instruction so as to enable the NFC chip to execute a corresponding communication task; and determining the execution result of the communication task after the control flow is executed.
10. The apparatus of claim 8, wherein the control flow determining module comprises:
the execution operation determining unit is used for determining at least one execution operation which is arranged in sequence in the execution flow according to the power failure setting parameter;
and the execution condition determining unit is used for determining the execution condition corresponding to each execution operation according to the power-off setting parameter.
11. The apparatus of claim 10, wherein the control flow execution module comprises:
the power-off execution unit is used for executing corresponding execution operation when the execution condition corresponding to the execution operation in the control flow is met so as to control the NFC chip to be powered off;
and the power-on execution unit is used for executing corresponding execution operation when the execution condition corresponding to the execution operation in the control flow is met so as to control the NFC chip to be powered on.
12. A computer-readable storage medium storing a computer program for executing the method for testing an NFC chip according to any one of claims 1 to 7.
13. An electronic device, the electronic device comprising:
a processor;
a memory for storing the processor-executable instructions;
the processor is configured to read the executable instructions from the memory and execute the instructions to implement the method for testing an NFC chip according to any one of claims 1 to 7.
CN202210847754.5A 2022-07-19 2022-07-19 NFC chip testing method and device, readable medium and electronic equipment Pending CN114942871A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210847754.5A CN114942871A (en) 2022-07-19 2022-07-19 NFC chip testing method and device, readable medium and electronic equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210847754.5A CN114942871A (en) 2022-07-19 2022-07-19 NFC chip testing method and device, readable medium and electronic equipment

Publications (1)

Publication Number Publication Date
CN114942871A true CN114942871A (en) 2022-08-26

Family

ID=82910891

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210847754.5A Pending CN114942871A (en) 2022-07-19 2022-07-19 NFC chip testing method and device, readable medium and electronic equipment

Country Status (1)

Country Link
CN (1) CN114942871A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115856589A (en) * 2023-02-28 2023-03-28 北京紫光青藤微系统有限公司 Test circuit and test method for NFC chip power tube transmitting circuit
CN118016143A (en) * 2024-03-21 2024-05-10 星汉智能科技股份有限公司 Smart card power-off test method, terminal and storage medium

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130268218A1 (en) * 2012-04-06 2013-10-10 Hon Hai Precision Industry Co., Ltd. Testing system and method
CN103605947A (en) * 2013-12-04 2014-02-26 东信和平科技股份有限公司 Contact type power-off card reader
CN106093659A (en) * 2016-07-22 2016-11-09 工业和信息化部电子工业标准化研究院 Smart card power-off protection test device, system and method
CN107729196A (en) * 2017-09-30 2018-02-23 东信和平科技股份有限公司 Smart card power failure test method
CN113850092A (en) * 2021-08-12 2021-12-28 北京握奇智能科技有限公司 Card reader, system and test method supporting smart card power-off test

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130268218A1 (en) * 2012-04-06 2013-10-10 Hon Hai Precision Industry Co., Ltd. Testing system and method
CN103605947A (en) * 2013-12-04 2014-02-26 东信和平科技股份有限公司 Contact type power-off card reader
CN106093659A (en) * 2016-07-22 2016-11-09 工业和信息化部电子工业标准化研究院 Smart card power-off protection test device, system and method
CN107729196A (en) * 2017-09-30 2018-02-23 东信和平科技股份有限公司 Smart card power failure test method
CN113850092A (en) * 2021-08-12 2021-12-28 北京握奇智能科技有限公司 Card reader, system and test method supporting smart card power-off test

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115856589A (en) * 2023-02-28 2023-03-28 北京紫光青藤微系统有限公司 Test circuit and test method for NFC chip power tube transmitting circuit
CN115856589B (en) * 2023-02-28 2023-06-20 北京紫光青藤微系统有限公司 Test circuit and test method for NFC chip power tube transmitting circuit
CN118016143A (en) * 2024-03-21 2024-05-10 星汉智能科技股份有限公司 Smart card power-off test method, terminal and storage medium

Similar Documents

Publication Publication Date Title
CN114942871A (en) NFC chip testing method and device, readable medium and electronic equipment
CN112199244B (en) Method, system, equipment and medium for detecting power failure of server
CN110704304B (en) Application program testing method and device, storage medium and server
US8176281B2 (en) Controlling access to an embedded memory of a microcontroller
US11221933B2 (en) Holdup self-tests for power loss operations on memory systems
CN102737724A (en) System and method for testing nonvolatile random access memory (NVRAM)
CN113342669B (en) Verification method and device for shortening convergence time of chip code coverage rate
CN106681877B (en) Chip debugging system and method and system chip
CN114020682A (en) Chip working mode control method and device, chip and storage medium
CN111176917B (en) Method, system, terminal and storage medium for testing stability of CPU SST-BF function
CN110473585B (en) Replacement method, device and equipment for erasing failed storage unit and storage medium
CN116401086A (en) Test method, device, equipment and medium for memory funnel error reporting mechanism
US6948086B2 (en) Computer system
CN113722212B (en) CPLD upgrading test method, device, equipment and medium
JP4940757B2 (en) Mobile radio communication terminal, information collecting method and program when abnormality occurs
KR100809684B1 (en) verification apparatus for verify the power off effect on Register Transfer Level and modeling method for power off effect
CN115204081A (en) Chip simulation method, chip simulation platform, chip simulation system, and computer-readable storage medium
CN112463508A (en) Server dormancy state testing method, system, terminal and storage medium
CN113986635B (en) BIOS testing method, system, storage medium and device
CN116595933B (en) Random verification method and device for voltage configuration, electronic equipment and storage medium
CN111552594B (en) Method, device and system for detecting power failure of solid state disk and electronic equipment
CN115270107B (en) Information verification method and device, readable medium and electronic equipment
CN115114101B (en) Link testing method, device, system and storage medium
US11836025B2 (en) Device and method for updating register transfer level power model
KR100296327B1 (en) Test circuit and test method of flash memory device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20220826