CN115270057A

CN115270057A - Multi-mode FFT implementation device and method

Info

Publication number: CN115270057A
Application number: CN202210890150.9A
Authority: CN
Inventors: 曾江州; 张继辉; 梁靖康; 林耀文
Original assignee: Xingcheng Guangzhou Technology Application Co ltd
Current assignee: Xingcheng Guangzhou Technology Application Co ltd
Priority date: 2022-07-27
Filing date: 2022-07-27
Publication date: 2022-11-01

Abstract

The invention relates to a multi-mode FFT (fast Fourier transform) implementation device and a multi-mode FFT implementation method, wherein the length of data to be operated is divided into P x N, and the value range of the divided P is as follows: integer values which are more than or equal to 1 and less than or equal to 4, or product combination of points supported by a 3-point FFT calculating unit and a 4-point FFT calculating unit; the value range of the divided N is the product combination of the number of points supported by the 4-point FFT computing unit, and the 4-point FFT computing unit is configured to carry out 4-point FFT operation and 2-point FFT operation; therefore, when the FFT operation is carried out subsequently, at least one of the 3-point FFT calculating unit and the 4-point FFT calculating unit is called to read the data to be operated from the memory, so that the P-point FFT operation of the data to be operated in the first stage can be completed, then the operation result of the first stage is used as input, and the N-point FFT operation of the second stage can be completed by calling the 4-point FFT calculating unit.

Description

Multi-mode FFT implementation device and method

Technical Field

The present invention relates to the field of communications, and in particular, to a device and a method for implementing a multi-mode FFT.

Background

In the field of mobile communication technology, the 5G standard, such as the fifth generation mobile communication system (5G NR), supports FFT (Fast Fourier Transform) of various lengths to cover diverse application scenarios; to support multiple length FFTs, there are two approaches:

one way is to adopt an FFT computing unit with a fixed length M (also called as point number) to preprocess input data to be computed so as to adapt to the FFT with the fixed length M, and in order to take account of all FFT lengths, the fixed length M supported by the FFT computing unit and the actual length N of the actually input data to be computed need to satisfy a multiple relation, that is, the value of M/N or N/M is a positive integer, so when N is less than M, the length N of the data to be computed needs to be supplemented to the length M supported by the FFT processing unit by means of interpolation (for example, 0 insertion, or copying of specific data, etc.), and then the FFT computation is performed; when N is larger than M, the data needs to be subjected to sectional calculation, and then the data subjected to the sectional calculation is subjected to splicing operation to obtain a result; this introduces excessive computation, reduces computational efficiency, and increases computational power consumption and processing delay.

Another rule is to set one FFT calculating unit for each length N of data to be calculated, for example, assuming that the current communication system needs to be compatible with 8 lengths of FFTs, 8 FFT calculating units with corresponding lengths need to be set. This method requires a large amount of FFT computation resources in the FFT operator, which has high resource redundancy cost and a complex system, and only one FFT computation unit corresponding to the actual input length N is used at any time, resulting in a low utilization rate of the FFT resources.

Disclosure of Invention

In view of the above shortcomings in the prior art, an object of the present invention is to provide a multimode FFT implementation apparatus and method, which are used to support FFTs of various lengths and simultaneously solve the problem of calculation efficiency, resource utilization rate and simplified structure.

In order to solve the above technical problem, the present invention provides a multimode FFT implementation device, including:

an FFT operator including at least one 3-point FFT calculation unit and at least one 4-point FFT calculation unit, the 4-point FFT calculation unit being configured to be capable of performing a 4-point FFT operation and a 2-point FFT operation;

the memory is used for storing data to be operated;

the controller is used for dividing the length of the data to be operated into P x N, calling at least one of the 3-point FFT calculating unit and the 4-point FFT calculating unit to read the data to be operated from the memory, performing first-stage P-point FFT operation on the data to be operated, taking an operation result of the first stage as input, and calling the 4-point FFT calculating unit to finish second-stage N-point FFT operation;

the value range of P is as follows: an integer value of 1 or more and 4 or a product combination of points supported by at least one of the 3-point FFT computation unit and the 4-point FFT computation unit;

the value range of the N is the product combination of the number of points supported by the 4-point FFT computing unit.

Optionally, the value of P is {1,2,3,6,4 × K }, where K is an integer value greater than or equal to 1 and less than or equal to 4;

the value of N is 256 or 128.

Optionally, the controller is configured to, when P is 1, invoke the 3-point FFT computing unit or the 4-point FFT computing unit to read data to be operated from the memory, and perform a first-stage P-point FFT operation on the data to be operated;

the controller is used for calling the 4-point FFT computing unit to read data to be operated from the memory and carrying out first-stage P-point FFT operation on the data to be operated when the P is 2,4,8 or 16;

the controller is used for calling the 3-point FFT computing unit to read data to be computed from the memory when the P is 3, and performing first-stage P-point FFT computation on the data to be computed;

the controller is used for calling the 3-point FFT calculating unit and the 4-point FFT calculating unit to read data to be operated from the memory when the P is 6 or 12, and performing first-stage P-point FFT operation on the data to be operated.

Optionally, the controller is configured to divide N into 4 × 4 when N is 256, and invoke one 4-point FFT computation unit to sequentially perform 4-stage 4-point FFT computation;

the controller is used for dividing the N into 4 x 2 when the N is 128, and calling the 4-point FFT calculation unit to sequentially perform 3-level 4-point FFT calculation and then perform one-level 2-point FFT calculation.

Optionally, the FFT operator comprises one 3-point FFT computation unit and at least 4-point FFT computation units;

the controller is used for dividing the N into 4 x 4 when the N is 256, and calling 4-point FFT computing units to sequentially perform 4-level 4-point FFT operation;

the controller is used for dividing the N into 4 x 2 when the N is 128, calling 4-point FFT calculation units to sequentially perform 3-stage 4-point FFT calculation, and finally performing one-stage 2-point FFT calculation.

Optionally, the length of the data to be operated is {256, 384, 512, 768, 1024, 1536, 2048, 3072, 4096}.

Based on the same inventive concept, the invention also provides a multi-mode FFT implementation method, which comprises the following steps:

the controller divides the length of the data to be operated into P × N, and the value range of P is as follows: an integer value greater than or equal to 1 and less than or equal to 4, or a product combination of points supported by at least one of a 3-point FFT computing unit and a 4-point FFT computing unit, where a value range of N is the product combination of points supported by the 4-point FFT computing unit; the 4-point FFT calculation unit is configured to be capable of performing a 4-point FFT operation and a 2-point FFT operation;

the controller calls at least one of the 3-point FFT computing unit and the 4-point FFT computing unit to read data to be operated from the memory, performs first-stage P-point FFT operation on the data to be operated, takes an operation result of the first stage as input of second-stage N-point FFT operation, and calls the 4-point FFT computing unit to finish the second-stage N-point FFT operation.

the value of N is 256 or 128.

Optionally, when the P is 1, the controller invokes the 3-point FFT computing unit or the 4-point FFT computing unit to perform a first-stage P-point FFT operation;

when the P is 2,4,8 or 16, the controller calls the 4-point FFT computing unit to carry out first-stage P-point FFT operation;

when the P is 3, the controller calls the 3-point FFT computing unit to carry out first-stage P-point FFT operation;

and when the P is 6 or 12, the controller calls the 3-point FFT calculating unit and the 4-point FFT calculating unit to carry out first-stage P-point FFT operation.

Optionally, when N is 256, the controller divides N into 4 × 4, and invokes one 4-point FFT computation unit to sequentially perform 4-stage 4-point FFT computation, or invokes 4-point FFT computation units to sequentially perform 4-stage 4-point FFT computation;

when the N is 128, the controller divides the N into 4 × 2, and invokes one of the 4-point FFT calculation units to sequentially perform 3-level 4-point FFT calculation and then perform one-level 2-point FFT calculation, or invokes 4 of the 4-point FFT calculation units to sequentially perform 3-level 4-point FFT calculation and then perform one-level 2-point FFT calculation.

Advantageous effects

The multi-mode FFT realizing equipment and the method divide the length of data to be operated into P x N, wherein the value range of the divided P is as follows: integer values which are more than or equal to 1 and less than or equal to 4, or product combination of points supported by a 3-point FFT calculating unit and a 4-point FFT calculating unit; the value range of the divided N is the product combination of the number of points supported by the 4-point FFT computing unit, and the 4-point FFT computing unit is configured to carry out 4-point FFT operation and 2-point FFT operation; therefore, when FFT operation is performed subsequently, at least one of the 3-point FFT calculating unit and the 4-point FFT calculating unit is called to read the data to be operated from the memory, so that the P-point FFT operation of the data to be operated in the first stage can be completed, then the operation result of the first stage is used as input, and the N-point FFT operation of the second stage can be completed by calling the 4-point FFT calculating unit, thus:

in the application, in the whole calculation process, only a 4-point FFT calculation unit or a 3-point FFT calculation unit and a 4-point FFT calculation unit is needed, namely, the calculation of the FFTs with various lengths can be realized only by arranging the 3-point FFT calculation unit and the 4-point FFT calculation unit, the FFT calculation units supporting various lengths are not needed, the cost can be reduced, the resource utilization rate can be improved, and the calculation process is regular, simple in structure, easy to realize and convenient to maintain and optimize; in addition, preprocessing such as interpolation and the like is not needed to be carried out on the data, only the length of the data to be operated is needed to be set, and the time delay from the input of the data to be operated to the completion of the calculation is basically related to the length of the data to be operated, so that the data operation time delay can be reduced, and the processing efficiency is improved; and the whole calculation process only involves the calling of a 3-point FFT calculation unit and/or a 4-point FFT calculation unit, so that the calculation complexity is reduced, and the calculation efficiency is further improved.

Drawings

Fig. 1 is a schematic structural diagram of a multi-mode FFT implementation apparatus according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of an FFT operator according to an embodiment of the present invention;

fig. 3 is a flowchart illustrating a multi-mode FFT implementation method according to an embodiment of the present invention.

Detailed Description

To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.

The embodiment provides a multi-mode FFT implementation device, which can support FFT with various lengths, and meanwhile, has the advantages of calculation efficiency, resource utilization rate and simplified structure. Referring to fig. 1, the multi-mode FFT implementation apparatus provided in this embodiment includes:

an FFT operator 1, wherein the FFT operator 1 includes at least one 3-point FFT computation unit 11 and at least one 4-point FFT computation unit 12, and the 4-point FFT computation unit 12 is configured to be capable of performing a 4-point FFT operation and a 2-point FFT operation; that is, in this embodiment, both the 4-point FFT operation and the 2-point FFT operation are implemented by the 4-point FFT computing unit 12, and the 4-point FFT computing unit 12 can be dynamically controlled to currently perform the 4-point FFT operation or perform the 2-point FFT operation;

the memory 2 comprises a storage unit for storing data to be operated, and can be set to comprise at least one of a storage unit for storing an intermediate operation result, a storage unit for storing a final operation result and a storage twiddle factor according to requirements, and can be specifically set according to application requirements without limitation;

the controller 3 is used for dividing the length of the data to be operated into P x N; the value range of P divided in this embodiment is: integer values greater than or equal to 1 and less than or equal to 4, or product combinations of the number of points supported by at least one of the 3-point FFT computation unit 11 and the 4-point FFT computation unit 12; the value range of N is the product combination of the number of points supported by the 4-point FFT computation unit 12.

For example, the product combination of the number of points supported by at least one of the 3-point FFT computation unit 11 and the 4-point FFT computation unit 12 includes, but is not limited to: 3 × 2 (the effective points when the 4-point FFT computing unit performs 2-point FFT computation), 3 × 4,4 × 4,3 × 4 × 2 and the like, and particularly, flexible product combination can be performed according to requirements;

the product combination of the number of points supported by the 4-point FFT computation unit 12 includes, but is not limited to: 4 x 4 \8230; \ 8230; \ 4,4 x 4 \8230;. 2, in particular, flexible product combinations can be carried out according to requirements.

For example, in an application example of the present embodiment, the length L = {256, 384, 512, 768, 1024, 1536, 2048, 3072, 4096} of the data to be operated that needs to be supported, and in addition to the length L =384, other data may be expressed as L = p1 × n1, where p1= {1,2,3,4,6,8, 12, 16}, n1=256; l =384 can be expressed as L = p2 × n2, p2=3, n2=128. Therefore, during the division, P1 and P2 can be unified as P, and the value of P is an integer value greater than or equal to 1 and less than or equal to 4, or a product combination of the number of points supported by the 3-point FFT computing unit 11 and the 4-point FFT computing unit 12, N1 and N2 are unified as N, and the value of N is 256 or 128;

in this example, P after P1 and P2 are unified may be further divided into {1,2,3,6,4 × K }, where K is an integer value greater than or equal to 1 and less than or equal to 4, for example:

when P is 6, it can be realized by combining the product of the number of points supported by the 3-point FFT computation unit 11 and the 4-point FFT computation unit 12 by 3 × 2;

when P is 8 (that is, K takes a value of 2), it can be implemented by combining 4 × 2 with the product of the number of points supported by the 4-point FFT computation unit 12;

when P is 12 (that is, K takes a value of 3), it can be realized by combining the product of the number of points supported by the 3-point FFT computing unit 11 and the 4-point FFT computing unit 12 by 3 × 4;

when P is 16 (that is, K has a value of 4), it can be implemented by combining 4 × 4 with the product of the number of points supported by the 4-point FFT computation unit 12;

of course, in other examples, when the value of P is greater than 16, the above rules may be repeated in the same manner, and details are not repeated herein.

In this embodiment, after determining the length division rule of the data to be calculated, the controller 3 may control to invoke at least one of the 3-point FFT computing unit 11 and the 4-point FFT computing unit 12 to read the data to be calculated from the memory 2, perform the first-stage P-point FFT operation on the data to be calculated, and invoke the 4-point FFT computing unit 12 to complete the second-stage N-point FFT operation with the operation result of the first stage as input.

For example, take over the example above:

the controller 3 may be configured to, when P is 1, that is, the number of FFT points in the first stage is 1, indicate a pass-through, that is, a sub-FFT operation is not required, so that any one of the 3-point FFT calculating unit 11 and the 4-point FFT calculating unit may be called to read data to be operated from the memory 2, and perform a first-stage 1-point FFT operation on the data to be operated;

the controller 3 can be used for calling the 4-point FFT computing unit 12 to read the data to be operated from the memory 2 when P is 2,4,8 or 16, and performing the first-stage P-point FFT operation on the data to be operated; for example, when the value of P is 2, the 4-point FFT computing unit 12 may be called to read the data to be computed from the memory 2 and perform 2-point FFT computation on the data; when the value of P is 4, the 4-point FFT computation unit 12 may be invoked to read the data to be computed from the memory 2 and perform 4-point FFT computation thereon; when the value of P is 8, the 4-point FFT computation unit 12 may be invoked to read the data to be computed from the memory 2 and sequentially perform 4-point FFT computation and 2-point FFT computation on the data; of course, the call here may only call one 4-point FFT computation unit 12 to perform 4-point FFT computation first, and then perform 2-point FFT computation, or call two 4-point FFT computations to perform 4-point FFT computation and 2-point FFT computation in sequence, respectively; and it should be understood that, in this example, the 2-point FFT operation may be performed first, and then the 4-point FFT operation may be performed; when the value of P is 16, the 4-point FFT computation unit 12 may be invoked to read data to be computed from the memory 2 and sequentially perform 2-level 4-point FFT computation;

the controller 3 is configured to invoke the 3-point FFT computation unit 11 to read the data to be computed from the memory 2 when P is 3, and perform the first-stage 3-point FFT computation on the data to be computed;

the controller 3 is configured to invoke the 3-point FFT computation unit 11 and the 4-point FFT computation unit 12 to read the data to be computed from the memory 2 when P is 6 or 12, and perform the first-stage P-point FFT computation on the data to be computed. For example, when the value of P is 6, the 3-point FFT computing unit 11 and the 4-point FFT computing unit 12 may be invoked to read data to be computed from the memory 2 and sequentially perform 3-point FFT computation and 2-point FFT computation on the data; when the value of P is 12, the 3-point FFT computation unit 11 and the 4-point FFT computation unit 12 may be invoked to read the data to be computed from the memory 2 and perform 3-point FFT computation and 4-point FFT computation on the data in sequence.

As can be known from the above examples, in this embodiment, the P-point FFT operation of the values of each P in the first stage can be completed by at least one of the 3-point FFT computing unit 11 and the 4-point FFT computing unit 12, that is, all possible values of the P in the first stage can be completed by at least one of the 3-point FFT computing unit 11 and the 4-point FFT computing unit 12.

In this example, the controller 3 may be configured to, when the value 256 of N is taken, divide N into 4 × 4, and invoke one 4-point FFT computation unit 12 to sequentially perform 4-level 4-point FFT computation (for example, see fig. 1), or invoke 4-point FFT computation units 12 to sequentially perform 4-level 4-point FFT computation (for example, see fig. 2);

when N is 128, the controller 3 is configured to divide N into 4 × 2, and invoke one 4-point FFT computation unit 12 (see, for example, fig. 1) to sequentially perform 3-stage 4-point FFT computation and then perform one-stage 2-point FFT computation, or invoke 4-point FFT computation units 12 (see, for example, fig. 2) to sequentially perform 3-stage 4-point FFT computation and finally perform one-stage 2-point FFT computation.

In the above example, when one 4-point FFT computing unit 12 is called to perform multi-stage FFT computation, there is no need to set one 4-point FFT computing unit 12 for each stage of FFT computation, so that the setting of the 4-point FFT computing unit 12 can be greatly reduced, resources are reduced, the structure is simplified, and the cost is reduced; when a plurality of 4-point FFT computation units 12 are called to sequentially perform multi-stage FFT computation, the computation efficiency can be relatively improved. Of course, it should be understood that two rules may also be used in combination, for example, when dividing N into 4 × 4, 2 or 3 4-point FFT computation units 12 may be called, wherein a part of the 4-point FFT computation units 12 performs two or more 4-point FFT operations, and another part performs one-level 4-point FFT operation, which is also an equivalent alternative in this embodiment and is also within the scope of this embodiment.

As can be seen from the above example, in the present embodiment, in the second stage, only a single FFT computation unit, i.e., the 4-point FFT computation unit 12, can support various possible values of N. And the first stage and the second stage sectional FFT operation are adopted, so that the utilization rate of the computing unit can be improved.

In addition, it should be understood that, in the present embodiment, the 4-point FFT computation unit 12 called in the first stage and the 4-point FFT computation unit 12 called in the second stage may be the same 4-point FFT computation unit 12, and at this time, the setting of the 4-point FFT computation unit 12 may be further reduced, for example, as shown in fig. 1. Of course, in other examples, the 4-point FFT computation unit 12 invoked in the first stage and the 4-point FFT computation unit 12 invoked in the second stage may also be different 4-point FFT computation units 12, for example, as shown in fig. 2.

As can be seen from the above example, in the entire FFT operation process in this example, only part of the values of P need to call the 3-point FFT computation unit 11 in the first stage, most of the values of P in the first stage only need to call the 4-point FFT computation unit 12, and all the values of N in the second stage only need to call the 4-point FFT computation unit 12, while the 4-point FFT computation unit 12 does not need to perform multiplication operation, and only needs to perform simple operations such as addition and subtraction, and the like, and the operation rate is fastest, the universality is better, so that the operation rule can be simplified, the comprehensive operation efficiency can be improved, and the operation delay can be reduced. And it should be understood that, in this example, when the FFT operation of the next stage is required after the completion of the FFT operation of one stage, the result obtained by the FFT operation of the previous stage may be multiplied by the corresponding twiddle factor to be used as the input of the FFT operation of the next stage.

In the present embodiment, only one 3-point FFT computation unit 11 may be provided, and in some application examples, only one 4-point FFT computation unit 12 may also be provided, thereby achieving a very simple configuration of the FFT operation unit.

The embodiment also provides a method for implementing a multi-mode FFT, as shown in fig. 3, which includes but is not limited to:

s301: the controller 3 divides the length of the data to be operated into P × N; for a specific division rule, reference is made to the above example, which is not described herein again.

S302: the controller 3 calls at least one of the 3-point FFT computing unit and the 4-point FFT computing unit to read the data to be operated from the memory 2, and carries out first-stage P-point FFT operation on the data to be operated.

S303: the controller 3 takes the operation result of the first stage as the input of the second stage N-point FFT operation, and invokes the 4-point FFT computation unit 12 to complete the second stage N-point FFT operation.

For example, in a 5G standard, let the FFT length L = {256, 384, 512, 768, 1024, 1536, 2048, 3072, 4096} that needs to be supported.

Assuming that the length L of the current data to be budgeted is 384, dividing the data into 3 × 128, i.e., P =3, N =128, and dividing N =128 into 4 × 2; then, the 3-point FFT computation unit 11 in fig. 1 or fig. 2 is called to perform a first-stage 3-point FFT computation on the data to be computed, the computation result in the first stage is used as an input, and one or more 4-point FFT computation units 12 are called to sequentially perform 4-stage 4 × 2 computation.

Assuming that the length L of the current data to be budgeted is 1536, the data is divided into 6 × 256, that is, P =6, n =256, and P =6 is divided into 2 × 3, n =256 is divided into 4 × 4; then, the 3-point FFT computing unit 11 and the 4-point FFT computing unit 12 in fig. 1 or fig. 2 are called to perform the first stage 3 × 2-point FFT operation on the data to be operated, and the operation result of the first stage is used as an input, and one or more 4-point FFT computing units 12 are called to sequentially perform 4 × 4 operations of 4 stages.

Assuming that the length L of the current data to be budgeted is 3072, the data is divided into 12 × 256, that is, P =12, n =256, and P =12 is divided into 3 × 4, n =256 is divided into 4 × 4; then, the 3-point FFT computation unit 11 and the 4-point FFT computation unit 12 in fig. 1 or fig. 2 are called to perform the first stage 3 × 4-point FFT computation on the data to be computed, the computation result of the first stage is used as input, and one or more 4-point FFT computation units 12 are called to sequentially perform 4 × 4 computation of 4 stages.

Assuming that the length L of the current data to be budgeted is 4096, the data is divided into 16 × 256, i.e., P =16, n =256, and P =16 is divided into 4 × 4, n =256 is divided into 4 × 4; then, the 4-point FFT computation unit 12 in fig. 1 or fig. 2 is called to perform a first-stage 4 × 4-point FFT computation on the data to be computed, the computation result of the first stage is used as an input, and one or more 4-point FFT computation units 12 are called to sequentially perform 4 stages of 4 × 4 operations.

Of course, it should be understood that the FFT length L required to be supported in the present embodiment is not limited to the value shown in the above example, and is not limited to be applied to a 5G network, and may also be applied to a 4G network, a 6G network, or the like.

For example, assume that in a 4G network, when one of L takes a value of 128, it is divided into 1 × 128, i.e., P =1, N =128, and N =128 is divided into 4 × 2; then, the 3-point FFT computation unit 11 or the 4-point FFT computation unit 12 in fig. 1 or fig. 2 are called to perform the first-stage 1-point FFT computation (pass-through) on the data to be computed, the computation result of the first stage is used as an input, and one or more 4-point FFT computation units 12 are called to sequentially perform 4-stage 4-by-2 computation (of course, the computation may be adjusted to sequentially perform 4-stage 2-by-4 computation according to the requirement).

For another example, in a 6G network, when one of the values of L is greater than 4608, it is divided into 18 × 256, that is, P =18, n =256, and P =18 is divided into 3 × 2, n =256 is divided into 4 × 4; then, the 3-point FFT computation unit 11 and the 4-point FFT computation unit 12 in fig. 1 or fig. 2 are called to sequentially perform a first stage 3 × 2-point FFT computation (pass-through) on the data to be computed, and the computation result of the first stage is taken as an input, and one or more 4-point FFT computation units 12 are called to sequentially perform 4 stages of 4 × 4 operations.

As can be seen from the above examples, the application scenario of the multi-mode FFT implementation apparatus and method provided in this embodiment can be flexibly applied according to the length division rule and the call rule of the 3-point FFT computation unit 11 and the 4-point FFT computation unit 12 provided in this embodiment, and can be applied to various communication networks using this rule, which is not limited in this embodiment. And the multi-mode FFT implementing apparatus and method in the present embodiment can be applied to, but not limited to, a terminal (e.g., a 4G terminal, a 5G terminal, or a 6G terminal, etc.) and various base stations. After the method is applied, the terminal or the base station only needs to use a 4-point FFT computing unit or a 3-point FFT computing unit and a 4-point FFT computing unit in the whole FFT computing process, namely, the calculation of the FFTs with various lengths can be realized only by setting the 3-point FFT computing unit and the 4-point FFT computing unit, the FFT computing units supporting various lengths are not needed, the cost can be reduced, the resource utilization rate is improved, the computing process is regularized, the structure is simple, the implementation is easy, and the maintenance and the optimization are convenient; in addition, preprocessing such as interpolation and the like is not needed to be carried out on the data, only the length of the data to be operated is needed to be set, and the time delay from the input of the data to be operated to the completion of calculation is basically related to the length of the data to be operated, so that the data operation time delay can be reduced, and the processing efficiency is improved; and the whole calculation process only involves the calling of a 3-point FFT calculation unit and/or a 4-point FFT calculation unit, so that the calculation complexity is reduced, and the calculation efficiency is further improved.

It is to be understood that the invention is not limited to the examples described above, but that modifications and variations may be effected thereto by those of ordinary skill in the art in light of the foregoing description, and that all such modifications and variations are intended to be within the scope of the invention as defined by the appended claims.

Claims

1. A multi-mode FFT implementation device, comprising:

the memory is used for storing data to be operated;

the controller is used for dividing the length of the data to be operated into P x N, calling at least one of the 3-point FFT calculating unit and the 4-point FFT calculating unit to read the data to be operated from the memory, performing first-stage P-point FFT operation on the data to be operated, taking an operation result of the first stage as input, and calling the 4-point FFT calculating unit to complete second-stage N-point FFT operation;

the value range of the P is as follows: an integer value of 1 or more and 4 or a product combination of points supported by at least one of the 3-point FFT computation unit and the 4-point FFT computation unit;

2. The multi-mode FFT implementation device of claim 1, wherein P takes on a value of {1,2,3,6,4 x K }, K being an integer value equal to or greater than 1 and equal to or less than 4;

the value of N is 256 or 128.

3. The multi-mode FFT implementing device of claim 2, wherein the controller is configured to invoke the 3-point FFT computing unit or the 4-point FFT computing unit to read data to be operated from the memory and perform a first-stage P-point FFT operation on the data to be operated when the P is 1;

4. The multi-mode FFT implementing device of claim 2, wherein the controller is configured to divide N into 4 x 4 and invoke one of the 4-point FFT computing units to sequentially perform 4-level 4-point FFT operations when N is 256;

5. The multi-mode FFT implementing device of claim 2, wherein the FFT operator includes one 3-point FFT computing unit and at least 4-point FFT computing units;

6. The multi-mode FFT implementation device according to any of claims 1-5, wherein the length of the data to be operated on is {256, 384, 512, 768, 1024, 1536, 2048, 3072, 4096}.

7. A multi-mode FFT implementation method is characterized by comprising the following steps:

the controller divides the length of the data to be operated into P × N, and the value range of P is as follows: an integer value greater than or equal to 1 and less than or equal to 4, or a product combination of points supported by at least one of a 3-point FFT computing unit and a 4-point FFT computing unit, where a value range of N is the product combination of the points supported by the 4-point FFT computing unit; the 4-point FFT calculation unit is configured to be capable of performing a 4-point FFT operation and a 2-point FFT operation;

the controller calls at least one of the 3-point FFT computing unit and the 4-point FFT computing unit to read data to be operated from the memory, performs first-stage P-point FFT operation on the data to be operated, takes an operation result of the first stage as input of second-stage N-point FFT operation, and calls the 4-point FFT computing unit to complete the second-stage N-point FFT operation.

8. The multi-mode FFT implementation method according to claim 7, wherein the value of P is {1,2,3,6,4 x K }, the K being an integer value greater than or equal to 1 and less than or equal to 4;

the value of N is 256 or 128.

9. The multi-mode FFT implementation method of claim 8, wherein the controller invokes the 3-point FFT computation unit or the 4-point FFT computation unit to perform a first stage P-point FFT operation when the P is 1;

10. The multi-mode FFT implementation method of claim 8, wherein the controller divides N into 4 x 4 and invokes one of the 4-point FFT computation elements to perform 4-level 4-point FFT operations in sequence, or invokes 4 of the 4-point FFT computation elements to perform 4-level 4-point FFT operations in sequence, when N is 256;

and when the N is 128, the controller divides the N into 4 × 2, calls one 4-point FFT calculation unit to sequentially perform 3-level 4-point FFT calculation and then perform one-level 2-point FFT calculation, or calls 4-point FFT calculation units to sequentially perform 3-level 4-point FFT calculation and then perform one-level 2-point FFT calculation.