CN114389574A - Frequency response masking filter system and method of generation - Google Patents

Frequency response masking filter system and method of generation Download PDF

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Publication number
CN114389574A
CN114389574A CN202011109562.1A CN202011109562A CN114389574A CN 114389574 A CN114389574 A CN 114389574A CN 202011109562 A CN202011109562 A CN 202011109562A CN 114389574 A CN114389574 A CN 114389574A
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array
frm
dsp
parameter
filter
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郭振健
常静
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Datang Mobile Communications Equipment Co Ltd
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Datang Mobile Communications Equipment Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks
    • H03H2017/0298—DSP implementation

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Abstract

The application provides a frequency response shielding FRM filter system and a generation method, wherein the system comprises: a controller, a memory array and a FRM filter component; one end of the controller is connected with the signal input end, and the other end of the controller is connected with the control end of the storage array; the configuration end of the FRM filter component is connected with the output end of the storage array, the input end of the FRM filter component is connected with the signal input end, and the output end of the FRM filter component is used for outputting signals processed by FRM; and the controller is configured to call a target parameter corresponding to the current working bandwidth from the storage array and send the target parameter to the FRM filter component so as to generate an FRM filter matched with the current working bandwidth according to the target parameter. Therefore, by the FRM filter system, the FRM filter link multiplexing of the multi-bandwidth cell is realized, and the resource occupation is reduced.

Description

Frequency response masking filter system and method of generation
Technical Field
The present disclosure relates to the field of mobile communications technologies, and in particular, to a Frequency-Response-Masking (FRM) filter system and a generating method thereof.
Background
An Active Antenna Unit (AAU) is different from the RRU and Antenna separation scheme in the 4G era, and the AAU fuses an Antenna and an RRU, which is a key device of 5G.
In the related art, under the condition that one cell needs multiple bandwidth configurations, the AAU product needs to support the working modes of carriers under different bandwidth configurations, but the FRM filters with different coefficients need to be switched under different bandwidth configurations, which results in high resource occupation.
Disclosure of Invention
The FRM filter system and the generation method provided by the application are used for solving the problem that in the related technology, under the condition that one cell needs multiple bandwidth configurations, an AAU needs to switch FRM filters with different coefficients under different bandwidth configurations, and the resource occupation is high.
An embodiment of an aspect of the present application provides an FRM filter system, including: a controller, a memory array and a frequency response mask FRM filter component; one end of the controller is connected with the signal input end, and the other end of the controller is connected with the control end of the storage array; the configuration end of the FRM filter component is connected with the output end of the storage array, the input end of the FRM filter component is connected with the signal input end, and the output end of the FRM filter component is used for outputting signals processed by FRM; the controller configured to retrieve a target parameter corresponding to a current operating bandwidth from within the storage array to cause the storage array to send the target parameter to the FRM filter component; the FRM filter component configured to generate a FRM filter that matches the current operating bandwidth according to the target parameters.
Optionally, in a possible implementation manner of the embodiment of the first aspect of the present application, the FRM filter component includes: the digital signal processing device comprises a first shift register, a first Digital Signal Processor (DSP) array, a second DSP array, a third DSP array, an adder and a subtracter;
the configuration end of the first shift register, the configuration end of the first DSP array, the configuration end of the second DSP array and the configuration end of the third DSP array are respectively connected with the output ends of the storage array;
the input end of the first DSP array and the input end of the first shift register are connected with the signal input end, and the output end of the first DSP array is respectively connected with the input end of the second DSP array and the first input end of the subtracter;
the output end of the second DSP array is connected with the first input end of the adder;
the output end of the first shift register is connected with the second input end of the subtracter;
the output end of the subtracter is connected with the input end of the third DSP array;
the output end of the third DSP array is connected with the second input end of the adder;
the adder is configured to output the processed signal.
Optionally, in another possible implementation manner of the embodiment of the first aspect of the present application, the first DSP array includes M1 first DSPs that are sequentially connected and end-to-end, where M1 is a value obtained by rounding up N1/2;
the second DSP array comprises M2 second DSPs which are sequentially connected and are connected end to end, wherein M2 is a value obtained by rounding up N2/2;
the third DSP array comprises M3 sequentially connected third DSPs which are connected end to end, wherein M3 is a value obtained by rounding N3/2 upwards;
wherein N1 is the highest order of the interpolated prototype filter in each FRM filter corresponding to the system, N2 is the highest order of the first shielding filter in each FRM filter corresponding to the system, and N3 is the highest order of the second shielding filter in each FRM filter corresponding to the system.
Optionally, in yet another possible implementation manner of the embodiment of the first aspect of the present application, the system further includes: 2(M1-1) second shift registers connected in sequence;
the input end of the first second shift register is connected with the signal input end;
the configuration end of each second shift register is connected with the output end of a memory used for storing a first delay parameter in the memory array, and the output end of the ith second shift register and the output ends of the 2(M1-1) - (i-1) th second shift registers are respectively connected with one input end of the (i + 1) th first DSP, wherein i is a positive integer which is greater than 0 and less than or equal to M1-1.
Optionally, in another possible implementation manner of the embodiment of the first aspect of the present application, the storage array includes K memories, where K is M1+ M2+ M3+2, where M1 memories are respectively configured to store parameters corresponding to M1 first DSPs; m2 memories respectively configured to store parameters corresponding to the M2 second DSPs; m3 memories respectively configured to store parameters corresponding to M3 third DSPs, one memory configured to store second delay parameters corresponding to the first shift register, and the other memory configured to store first delay parameters corresponding to the M1-1 second shift register.
Optionally, in yet another possible implementation manner of the embodiment of the first aspect of the present application, the system corresponds to L kinds of operating bandwidths, and L kinds of parameters respectively corresponding to the L kinds of operating bandwidths are stored in each of the memories.
Another aspect of the present application provides a FRM filter generation method, including: acquiring the current working bandwidth of the system; reading a target parameter corresponding to the current working bandwidth from a storage array; and sending the target parameters to an FRM filter component to generate an FRM filter matched with the current working bandwidth.
Optionally, in a possible implementation manner of the embodiment of the second aspect of the present application, the reading, from the storage array, the target parameter corresponding to the current operating bandwidth includes:
acquiring the corresponding relation between each parameter and the bandwidth in each memory of the memory array;
determining a target address corresponding to the current working bandwidth according to the corresponding relation between each parameter and the bandwidth and the position of each parameter in a memory;
and reading target parameters corresponding to the target address from the storage array.
Optionally, in another possible implementation manner of the embodiment of the second aspect of the present application, an order of an interpolated prototype filter in the FRM filter corresponding to the current operating bandwidth is N1, and determining a target address corresponding to the current operating bandwidth according to the correspondence between each parameter and the bandwidth and a location of each parameter in a memory includes:
determining M1 memories respectively corresponding to the interpolation prototype filter of the N1 order, wherein M1 is a value obtained by rounding up N1/2;
and determining M1 target addresses corresponding to the current working bandwidth according to the corresponding relation between each parameter and the bandwidth in each memory and the position of each parameter in the memory.
Optionally, in another possible implementation manner of the embodiment of the second aspect of the present application, the FRM filter component includes a first DSP array, a first shift register, a second DSP array, and a third DSP array, the target parameter includes a filtering parameter, a second delay parameter, a first masking parameter, and a second masking parameter, and the sending the target parameter to the FRM filter component includes:
sending the filtering parameters to a first DSP array;
sending the second delay parameter to the first shift register;
sending the first mask parameter to the second DSP array;
and sending the second mask parameter to the third DSP array.
Optionally, in another possible implementation manner of the embodiment of the second aspect of the present application, the FRM filter component further includes 2(M1-1) second shift registers connected in sequence, the target parameter further includes a first delay parameter, and the sending the target parameter to the FRM filter component includes:
and respectively sending the first delay parameters to the 2(M1-1) second shift registers, wherein M1 is a value obtained by rounding up N1/2, and N1 is the highest order of an interpolated prototype filter in each FRM filter corresponding to the FRM filter component.
According to the FRM filter system and the generation method provided by the embodiment of the application, the target parameters corresponding to each working bandwidth are stored through the storage array, the target parameters corresponding to the current working bandwidth are called from the storage array through the controller and are sent to the FRM filter component, and the FRM filter component generates the FRM filter matched with the current working bandwidth according to the target parameters. Therefore, the target parameters corresponding to the working bandwidths are stored in the storage array in advance, the target parameters are called from the storage assembly according to the actual working bandwidths, the FRM filter assembly is adjusted, switching among different filter modules is not needed when the working bandwidths are changed, the working modes corresponding to various working bandwidths can be supported only through one FRM filter module, the FRM filter link multiplexing of a multi-bandwidth cell is realized, and the resource occupation amount is reduced.
Additional aspects and advantages of the present application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the present application.
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The foregoing and/or additional aspects and advantages of the present application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
fig. 1 is a schematic structural diagram of an FRM filter system according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of another FRM filter system according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of another FRM filter system according to an embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of another FRM filter system according to an embodiment of the present disclosure;
fig. 5 is a schematic flowchart of a FRM filter generation method according to an embodiment of the present disclosure;
fig. 6 is a flowchart illustrating another FRM filter generation method according to an embodiment of the present disclosure.
Detailed Description
In the embodiment of the present application, the term "and/or" describes an association relationship of associated objects, and means that there may be three relationships, for example, a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship.
In the embodiments of the present application, the term "plurality" means two or more, and other terms are similar thereto.
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The embodiment of the application provides a FRM filter system and a generation method, which are used for solving the problem that in the related art, under the condition that one cell needs multiple bandwidth configurations, an AAU needs to switch FRM filters with different coefficients under different bandwidth configurations, and the resource occupation is high.
The method and the device are based on the same application concept, and because the principles of solving the problems of the method and the device are similar, the implementation of the device and the method can be mutually referred, and repeated parts are not repeated.
The FRM filter system provided in the embodiment of the application stores the target parameters corresponding to the respective working bandwidths through the storage array, calls the target parameters corresponding to the current working bandwidths from the storage array through the controller, and sends the target parameters to the FRM filter component, so that the FRM filter component generates the FRM filter matched with the current working bandwidths according to the target parameters. Therefore, the target parameters corresponding to the working bandwidths are stored in the storage array in advance, the target parameters are called from the storage assembly according to the actual working bandwidths, the FRM filter assembly is adjusted, switching among different filter modules is not needed when the working bandwidths are changed, the working modes corresponding to various working bandwidths can be supported only through one FRM filter module, the FRM filter link multiplexing of a multi-bandwidth cell is realized, and the resource occupation amount is reduced.
The FRM filter system and the generation method provided by the present application are described in detail below with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of an FRM filter system according to an embodiment of the present disclosure.
As shown in fig. 1, the FRM filter system 100 includes: controller 110, memory array 120, and FRM filter component 130.
Wherein, one end of the controller 110 is connected to the signal input end, and the other end is connected to the control end of the memory array 120;
the configuration end of the FRM filter component 130 is connected with the output end of the storage array 120, the input end of the FRM filter component 130 is connected with the signal input end, and the output end of the FRM filter component 130 is used for outputting a signal processed by FRM;
a controller 110 configured to retrieve a target parameter corresponding to a current operating bandwidth from within storage array 120 to cause storage array 120 to send the target parameter to FRM filter component 130;
an FRM filter component 130 configured to generate an FRM filter that matches the current operating bandwidth according to the target parameters.
The controller 110 refers to a component that can direct each component in the system to coordinate according to the function requirement of the instruction. For example, the controller 110 may be a processor with a complex structure and a strong operation capability, such as a CPU and a GPU, or may also be an MCU with a simple structure and a low operation capability, and the like, which is not limited in the embodiment of the present application.
The memory array 120 may be any storage medium including a large number of memory cells and having writing and reading functions. For example, memory array 120 may be a ROM.
The FRM filter component 130 refers to a filter module having an FRM filtering function, and may be composed of a plurality of filters. In practical use, the FRM filter component 130 may be designed according to actual needs, which is not limited in this application.
In this embodiment, the FRM filter system 100 of this embodiment may perform filtering processing on an input signal to generate a filtered signal. However, since the performance and parameters of the filter required for the input signals with different bandwidths are different, the filter parameters corresponding to each operating bandwidth may be determined according to all possible operating bandwidths in the practical application scenario, and are stored in the storage array 120 respectively.
In this embodiment, one end of the controller 110 is connected to the signal input end, so that when the controller 110 acquires a signal input by the signal input end, the current working bandwidth can be determined according to the acquired signal; thereafter, the controller 110 may retrieve a target parameter corresponding to the current operating bandwidth from the storage array 120 according to the corresponding relationship between the operating bandwidth and the filter parameter. After the target parameters are determined, the target parameters may be sent to FRM filter component 130 through storage array 120 so that FRM filter component 130 may switch the internal parameters to the target parameters to generate an FRM filter that matches the current operating bandwidth; and performs filtering processing on the signal input to the FRM filter component 130 by using the generated FRM filter matched with the current operating bandwidth to output the FRM-processed signal.
As a possible implementation manner, filter parameters corresponding to each operating bandwidth may be determined according to specific characteristics of each operating bandwidth, and the corresponding relationship between the bandwidth and the filter parameters may be stored in the storage array 120. Therefore, after determining the current operating bandwidth, the controller 110 may obtain the corresponding relationship between each parameter and the bandwidth in each memory of the storage array 120 from the storage array 120, then may determine the target parameter corresponding to the current operating bandwidth according to the corresponding relationship between each parameter and the bandwidth, further determine the position of the target parameter in the memory according to the position of each parameter in the memory, determine the position of the target parameter in the memory as the target address corresponding to the current operating bandwidth, and read the target parameter corresponding to the target address from the storage array 120.
The FRM filter system provided in the embodiment of the application stores the target parameters corresponding to the respective working bandwidths through the storage array, calls the target parameters corresponding to the current working bandwidths from the storage array through the controller, and sends the target parameters to the FRM filter component, so that the FRM filter component generates the FRM filter matched with the current working bandwidths according to the target parameters. Therefore, the target parameters corresponding to the working bandwidths are stored in the storage array in advance, the target parameters are called from the storage assembly according to the actual working bandwidths, the FRM filter assembly is adjusted, switching among different filter modules is not needed when the working bandwidths are changed, the working modes corresponding to various working bandwidths can be supported only through one FRM filter module, the FRM filter link multiplexing of a multi-bandwidth cell is realized, and the resource occupation amount is reduced.
In one possible implementation form of the present application, the FRM filter component may be designed by a complementary filter and a shielding filter to further reduce the computational complexity of the design of the FRM filter component.
The FRM filter system provided by the embodiments of the present application is further described below with reference to fig. 2.
Fig. 2 is a schematic structural diagram of another FRM filter system according to an embodiment of the present disclosure.
As shown in fig. 2, based on the embodiment shown in fig. 1, FRM filter component 130 may include: a first shift register 131, a first Digital Signal Processor (DSP) array 132, a second DSP array 133, a third DSP array 134, an adder 135, and a subtractor 136;
the configuration end of the first shift register 131, the configuration end of the first DSP array 132, the configuration end of the second DSP array 133, and the configuration end of the third DSP array 134 are respectively connected to the output ends of the storage array 120;
the input end of the first DSP array 132 and the input end of the first shift register 131 are connected to the signal input end, and the output end of the first DSP array 132 is connected to the input end of the second DSP array 133 and the first input end of the subtractor 136, respectively;
an output of second DSP array 133 is connected to a first input of adder 135;
the output end of the first shift register 131 is connected with the second input end of the subtractor 136;
the output end of the subtractor 136 is connected with the input end of the third DSP array 134;
the output of the third DSP array 134 is connected to a second input of the adder 135;
an adder 135 configured to output the processed signal.
In the embodiment of the present application, the first DSP array 132 may be an interpolation prototype filter, and the second DSP array 133 and the third DSP array 134 may be mask filters. The first shift register 131 and the subtractor 136 can be used to determine the output of the interpolation complementary prototype filter corresponding to the interpolation prototype filter according to the signal input from the signal input terminal and the output of the first DSP array 132 (i.e., the interpolation prototype filter).
It should be noted that FRM filter component 130 may be implemented by a pair of complementary filters to reduce the number of DSPs in FRM filter component 130 and reduce the hardware complexity of FRM filter component 130. Wherein if two linear phase filters HaAnd HcSatisfies | Ha(ejw)+Hc(ejw) If 1, they are called complementary filters, where H isa(ejw) Is a linear phase filter HaFrequency response of Hc(ejw) Is a linear phase filter HcThe frequency response of (c). The frequency response is passed to the Z domain, | Ha(z)+Hc(z)|＝z-(N-1)*M/2Where N is the length of the linear phase filter and M is the interpolation factor. It can be seen that for a pair of complementary filters, the linear phase filter HcMay be subtracted from the delayed version of the input signal by a linear phase filter HaThe output of (c) is obtained.
Therefore, in the embodiment of the present application, a first shift register 131 and a subtractor 136 may be introduced into the FRM filter component 130, and an input terminal of the first shift register 131 is connected to a signal input terminal, and an output terminal of the first shift register 131 is connected to a second input terminal of the subtractor 136, so as to perform delay processing on the input signal through the first shift register 131, generate a delayed version of the input signal, and input the delayed version to the subtractor 136; and the output of the first DSP array 132 is coupled to a first input of the subtractor 136 to subtract the delayed versions of the input signal from the output of the first DSP array 132 via the subtractor 136 to generate the output of the interpolated complementary prototype filter corresponding to the first DSP array 132.
In the embodiment of the present application, as shown in fig. 2, the FRM filter component 130 includes two branches, an upper branch is composed of a first DSP array 132 (i.e., an interpolated prototype filter) and a second DSP array 133 (i.e., a first masking filter), and a lower branch is composed of a first shift register 131, a subtractor (i.e., an interpolated complementary prototype filter) and a third DSP array 134 (a second masking filter). Wherein the second DSP array 133 functions to select a desired frequency component from the output of the first DSP array 132 (i.e., the interpolation prototype filter); the third DSP array 134 functions to select the desired frequency components from the output of the subtractor 136 (i.e., the interpolated complementary prototype filter). Thereafter, the output of the second DSP array 133 and the output of the third DSP array 134 are subjected to addition processing by an adder 135 to generate an output-processed signal.
It should be noted that the second DSP array 133 and the third DSP array 134 need to have the same group delay, so that when the outputs of the two are added by the adder 135, the two can be properly complemented within the pass band. When the parameters of the two DSP arrays 133 and the third DSP array 134 are not consistent, a small amount of delay is added back and forth to equalize the group delay characteristics.
In this embodiment, since the first shift register 131, the first DSP array 132, the second DSP array 133 and the third DSP array 134 have respective parameters, the configuration ends of the first shift register 131, the first DSP array 132, the second DSP array 133 and the third DSP array 134 may be all connected to the output end of the storage array 120, so that the storage array 120 respectively transfers the parameters corresponding to the first shift register 131, the first DSP array 132, the second DSP array 133 and the third DSP array 134 included in the target parameters to the first shift register 131, the first DSP array 132, the second DSP array 133 and the third DSP array 134, so that the first shift register 131, the first DSP array 132, the second DSP array 133 and the third DSP array 134 respectively adjust the internal parameters according to the respective parameters to generate the FRM filter matching the current working bandwidth, and further process the signal input to the system through the generated FRM filter, to generate a processed signal.
Furthermore, the interpolation prototype filter and the masking filter can be composed of a plurality of DSPs, and the DSPs at the symmetrical positions can be multiplexed, so that the number of the DSPs is reduced, and the hardware complexity of the FRM filter component is further reduced. That is, in a possible implementation form of the embodiment of the present application, as shown in fig. 3, on the basis of the embodiment shown in fig. 2, the first DSP array 132 may include M1 first DSPs (1321) connected in sequence and end to end, where M1 is a value rounded up from N1/2; the second DSP array 133 includes M2 second DSPs (not shown in the figure) connected in sequence and end to end, where M2 is a value obtained by rounding up N2/2; the third DSP array 134 comprises M3 sequentially connected and end-to-end third DSPs (not shown in the figure), wherein M3 is a value rounded up by N3/2; wherein, N1 is the highest order of the interpolation prototype filter in each FRM filter corresponding to the system, N2 is the highest order of the first shielding filter in each FRM filter corresponding to the system, and N3 is the highest order of the second shielding filter in each FRM filter corresponding to the system.
It should be noted that, when the cells operate in different bandwidths, orders of the FRM filters in the system may be different, so that the maximum order of the FRM filter in different bandwidths may be determined as the highest order of the FRM filter. For example, for a cell capable of operating in three bandwidths of 60M, 80M and 100M, when the cell operates in three bandwidths of 60M, 80M and 100M, respectively, the order numbers corresponding to the interpolation prototype filters are 29, 39 and 39, respectively, so that the highest order number N1 of the interpolation prototype filter can be determined to be 39.
In the embodiment of the present application, since the first DSP (1321) parameters in the first DSP array 132 are symmetrically set, and the symmetric parameters may be multiplexed in the same DSP, the number of the first DSPs (1321) included in the first DSP array 132 may be determined according to one-half of the highest order number of the interpolation prototype filter. For example, if the highest order N1 of the interpolation prototype filter is 39, then M1 is 19, that is, the first DSP array 132 includes 19 first DSPs (1321) connected end to end in sequence. Correspondingly, the values of M2 and M3 can also be determined in the same manner as described above, and are not described herein again; the connection of the second DSP in the second DSP array 133 and the connection of the third DSP in the third DSP array 134 are the same as the connection of the first DSP (1321) in the first DSP array 132, and thus are not shown in fig. 3.
Further, the interpolation factor M may also cause the delay between the DSPs in the interpolation prototype filter to be different, so that the delay parameter may be delivered to each first DSP through different delay registers, respectively, to perform the group delay processing on the first DSP array 132. That is, in a possible implementation form of the embodiment of the present application, as shown in fig. 4, on the basis of the embodiment shown in fig. 3, the FRM filter system 100 may further include: 2(M1-1) second shift registers 140 connected in series;
the input end of the first second shift register is connected with the signal input end;
the configuration terminal of each second shift register 140 is connected to the output terminal of the memory for storing the first delay parameter in the memory array 120, and the output terminal of the ith second shift register 140 and the output terminals of the 2(M1-1) - (i-1) th second shift registers 140 are respectively connected to one input terminal of the (i + 1) th first DSP (1321), where i is a positive integer greater than 0 and less than or equal to M1-1.
As a possible implementation manner, since the symmetric delay parameters can multiplex the same DSP to reduce the number of DSPs, the output ends of the two second shift registers 140 with symmetric delay parameters can be connected to the input end of the same first DSP (1321) to implement the multiplexing of the DSPs.
For example, if N1 is 39, M1 is 19, the number of the second shift registers 140 is 36, and since the 1 st first DSP (1321) does not need to perform a delay, the output terminals of the 1 st and 36 th second shift registers 140 may be connected to one input terminal of the 2 nd first DSP (1321); connecting the output terminals of the 2 nd and 35 th second shift registers 140 to one input terminal of a 3 rd first DSP (1321); the outputs of the 3 rd and 34 th second shift registers 140 are connected to one input of the 4 th first DSP (1321) and so on.
In this embodiment, the delay parameter between the first DSPs (1321) in the first DSP array 132 may be determined according to the interpolation factor of the interpolation prototype filter, and stored in the memory of the storage array 120, so that the controller 110 may retrieve the delay parameter from the memory storing the delay parameter when acquiring the signal input by the signal input end, and send the delay parameter to the second shift registers 140 through the storage array 120, further perform delay processing on the signal input by the signal input end through the second shift registers 140, and then each second shift register 140 sends the signal after delay processing to the first DSP (1321) connected thereto.
It should be noted that the manner of retrieving the delay parameter from the storage array 120 is the same as the manner of retrieving the target parameter from the storage array 120, and specific implementation processes and principles may refer to the detailed description of the foregoing embodiments, which is not described herein again.
Further, different memories in the memory array 120 may be used to store parameters of different DSPs to increase the data reading speed. That is, in one possible implementation manner of the embodiment of the present application, the storage array 120 may include K memories, where K is M1+ M2+ M3+2, where M1 memories are respectively configured to store parameters corresponding to M1 first DSPs; m2 memories respectively configured to store parameters corresponding to the M2 second DSPs; and the M3 memories are respectively configured to store parameters corresponding to the M3 third DSPs, one memory is configured to store second delay parameters corresponding to the first shift register, and the other memory is configured to store first delay parameters corresponding to the M1-1 second shift registers.
In this embodiment, a memory in the memory array 120 may store parameters corresponding to one DSP, so as to directly read the parameters corresponding to each DSP from the memory according to the location or address information of the memory, thereby improving the data reading speed. Therefore, it is assumed that the first DSP (1321), the second DSP, and the third DSP are all 19, i.e., M1-M2-M3-19, so that it can be determined that 59 memories can be included in the memory array 120. The 19 memories are respectively used for storing parameters corresponding to 19 first DSPs (1321), the 19 memories are respectively used for storing parameters corresponding to 19 second DSPs, and the 19 memories are respectively used for storing parameters corresponding to 19 third DSPs; in addition, one of the remaining two memories is used to store the second delay parameter corresponding to the first shift register 131, and the other memory is used to store the first delay parameter corresponding to each second shift register 140.
Further, since the parameters corresponding to each DSP may be different when there are multiple operating bandwidths of the cell, multiple parameters corresponding to one DSP may be stored in one memory. That is, in a possible implementation form of the embodiment of the present application, the FRM filter system 100 corresponds to L kinds of operating bandwidths, and L kinds of parameters respectively corresponding to the L kinds of operating bandwidths are stored in each memory.
For example, if the FRM filter system 100 is applied to a cell capable of operating at three bandwidths of 60M, 80M, and 100M, the FRM filter system 100 corresponds to 3 operating bandwidths, so that 3 parameters corresponding to each DSP in the FRM filter component 130 under the 3 operating bandwidths can be calculated in advance, and then the 3 parameters corresponding to one DSP are stored in the same memory.
According to the FRM filter system provided by the embodiment of the application, the target parameters corresponding to each working bandwidth are stored through the storage array, the target parameters corresponding to the current working bandwidth are called from the storage array through the controller and are sent to the FRM filter component, so that the FRM filter component generates an FRM filter matched with the current working bandwidth according to the target parameters; and the FRM filter component is designed through the complementary filter and the shielding filter, the DSP is multiplexed through the symmetrical parameters, and then a memory in the memory array is used for storing the parameters corresponding to the DSP, so that the FRM filter link multiplexing of the multi-bandwidth cell is realized, the resource occupation amount is reduced, the number of the DSPs is further reduced, the hardware complexity of the FRM filter is reduced, and the data reading speed is improved.
In order to implement the above embodiments, the present application further provides a FRM filter generation method.
Fig. 5 is a flowchart illustrating a method for generating an FRM filter according to an embodiment of the present disclosure.
As shown in fig. 5, the FRM filter generation method includes the following steps:
step 101, acquiring the current working bandwidth of the system.
It should be noted that the system may be the FRM filter system in the foregoing embodiment, and the FRM filter system in the embodiment of the present application may perform filtering processing on an input signal to generate a filtered signal. However, because the performance and parameters of the filters required by the input signals with different bandwidths are different, the filter parameters corresponding to each operating bandwidth can be determined according to all possible operating bandwidths in the actual application scene, and are respectively stored in the storage arrays of the FRM filter system.
In this embodiment of the application, one end of a controller of the FRM filter system may be connected to the signal input end, so that when the controller acquires a signal input by the signal input end, the current working bandwidth may be determined according to the acquired signal.
And 102, reading a target parameter corresponding to the current working bandwidth from the storage array.
In the embodiment of the present application, after the current operating bandwidth is determined by the controller, the target parameter corresponding to the current operating bandwidth may be retrieved from the storage array according to the corresponding relationship between the operating bandwidth and the filter parameter.
As a possible implementation manner, the step 102 may include:
acquiring the corresponding relation between each parameter and the bandwidth in each memory of the memory array;
determining a target address corresponding to the current working bandwidth according to the corresponding relation between each parameter and the bandwidth and the position of each parameter in a memory;
and reading the target parameter corresponding to the target address from the storage array.
As a possible implementation manner, filter parameters corresponding to each operating bandwidth may be determined according to specific characteristics of each operating bandwidth, and a correspondence between the bandwidth and the filter parameters may be stored in the storage array. Therefore, after the current working bandwidth is determined, the corresponding relation between each parameter and the bandwidth in each memory of the storage array can be obtained from the storage array, then the target parameter corresponding to the current working bandwidth can be determined according to the corresponding relation between each parameter and the bandwidth, the position of the target parameter in the memory is further determined according to the position of each parameter in the memory, the position of the target parameter in the memory is determined as the target address corresponding to the current working bandwidth, and the target parameter corresponding to the target address is read from the storage array.
Further, since each FRM filter in the FRM filter system may include a plurality of DSPs, and parameters corresponding to each DSP may be stored in one memory, each memory corresponding to each FRM filter may be determined first, and then specific addresses of each parameter corresponding to the FRM filter may be further determined. That is, in one possible implementation form of the embodiment of the present application, if the order of the interpolation prototype filter in the FRM filter corresponding to the current operating bandwidth is N1, the determining the target address corresponding to the current operating bandwidth according to the correspondence between each parameter and the bandwidth and the position of each parameter in the memory may include:
determining M1 memories corresponding to the interpolation prototype filters of the N1 order respectively, wherein M1 is a value obtained by rounding up N1/2;
and determining M target addresses corresponding to the current working bandwidth according to the corresponding relation between each parameter and the bandwidth in each memory and the position of each parameter in the memory.
In the embodiment of the present application, since the interpolation prototype filter and the two masking filters may be included in the FRM filter system, and both the interpolation prototype filter and the two masking filters may include a plurality of DSPs, one memory in the memory array may be used to store parameters corresponding to one DSP, so as to increase the data reading speed. Therefore, the memories corresponding to the filters can be determined in sequence, and the addresses corresponding to the mig filters can be determined from the positions of the memories corresponding to the filters in the storage array. The interpolation prototype filter will be described in detail below.
In the embodiment of the present application, the order of the interpolation prototype filter may determine the number of parameters and the number of DSPs corresponding to the interpolation prototype filter. For example, the number of DSPs corresponding to the N-th order interpolation prototype filter may be M1, and correspondingly, the number of parameters is M1, so that the positions of M1 memories corresponding to the N-th order interpolation prototype filter in the storage array may be determined first, and then M1 target parameters corresponding to the current operating bandwidth may be determined according to the corresponding relationship between the parameters and the operating bandwidth; and further determining the positions of the M1 target parameters in the M1 memories respectively according to the positions of the parameters in the M1 memories in the memories, namely M1 target addresses corresponding to the current working bandwidth.
It should be noted that, the method for determining the target addresses of the parameters corresponding to other filters in the system is the same as the above method, and is not described herein again.
Step 103, sending the target parameters to the FRM filter component to generate an FRM filter matched with the current working bandwidth.
In the embodiment of the application, after the target parameter is determined by the controller, the target parameter can be sent to an FRM filter component in the system through the storage array, so that the FRM filter component can switch the internal parameter to the target parameter to generate an FRM filter matched with the current working bandwidth; and the generated FRM filter matched with the current working bandwidth is used for filtering the signal input into the FRM filter component so as to output the signal after the FRM processing.
According to the FRM filter generation method provided by the embodiment of the application, the target parameters corresponding to the working bandwidths are stored through the storage array, the target parameters corresponding to the current working bandwidth are called from the storage array through the controller, and the target parameters are sent to the FRM filter component, so that the FRM filter component generates the FRM filter matched with the current working bandwidth according to the target parameters. Therefore, the target parameters corresponding to the working bandwidths are stored in the storage array in advance, the target parameters are called from the storage assembly according to the actual working bandwidths, the FRM filter assembly is adjusted, switching among different filter modules is not needed when the working bandwidths are changed, the working modes corresponding to various working bandwidths can be supported only through one FRM filter module, the FRM filter link multiplexing of a multi-bandwidth cell is realized, and the resource occupation amount is reduced.
In a possible implementation form of the application, the FRM filter component may include a plurality of filters, so that parameters corresponding to the filters may be sent to the filters, respectively, so as to improve efficiency and accuracy of parameter transmission.
The FRM filter generation method provided in the embodiment of the present application is further described below with reference to fig. 6.
Fig. 6 is a flowchart illustrating another FRM filter generation method according to an embodiment of the present disclosure.
As shown in fig. 6, the FRM filter generation method includes the following steps:
step 201, acquiring the current working bandwidth of the system.
The detailed implementation process and principle of step 201 may refer to the detailed description of the above embodiments, and are not described herein again.
Step 202, reading a target parameter corresponding to the current working bandwidth from the storage array, wherein the target parameter includes a filtering parameter, a second delay parameter, a first masking parameter and a second masking parameter.
In this embodiment, the FRM filter component may include a first DSP array, a first shift register, a second DSP array, and a third DSP array, and thus the target parameter may include a filtering parameter corresponding to the first DSP array, a second delay parameter corresponding to the first shift register, a first masking parameter corresponding to the second DSP array, and a second masking parameter corresponding to the third DSP array.
For other specific implementation processes and principles of the step 202, reference may be made to the detailed description of the foregoing embodiments, which are not described herein again.
Step 203, sending the filter parameters to the first DSP array.
In the embodiment of the application, since the first shift register, the first DSP array, the second DSP array and the third DSP array all have respective parameters, therefore, the configuration ends of the first shift register, the first DSP array, the second DSP array and the third DSP array can be connected with the output end of the memory array, so that the memory array respectively transmits the filtering parameter, the second delay parameter, the first mask parameter and the second mask parameter included in the target parameter to the first DSP array, the first shift register, the second DSP array and the third DSP array, so that the first DSP array, the first shift register, the second DSP array and the third DSP array respectively adjust the internal parameters according to the respective parameters to generate the FRM filter matched with the current working bandwidth, and further processing the signal input into the system from the signal input end through the generated FRM filter to generate a processed signal.
Furthermore, the interpolation prototype filter and the masking filter can be composed of a plurality of DSPs, and the DSPs at the symmetrical positions can be multiplexed, so that the number of the DSPs is reduced, and the hardware complexity of the FRM filter component is further reduced. That is, in a possible implementation form of the embodiment of the present application, the FRM filter component may further include 2(M1-1) second shift registers connected in sequence, and the target parameter may further include a first delay parameter; accordingly, the step 203 may include:
and respectively sending the first delay parameters to 2(M1-1) second shift registers, wherein M1 is a value obtained by rounding up N1/2, and N1 is the highest order of the interpolation prototype filter in each FRM filter corresponding to the FRM filter component.
In the embodiment of the present application, the interpolation factor M also causes the delay between the DSPs in the interpolation prototype filter to be different, so that the delay parameter can be delivered to each first DSP through different delay registers, so as to perform the group delay processing on the first DSP array 132.
As a possible implementation manner, since the symmetric delay parameters can multiplex the same DSP to reduce the number of DSPs, the output ends of two second shift registers with symmetric delay parameters can be connected to the input end of the same first DSP in the first DSP array to implement multiplexing of the DSPs.
For example, if N1 is 39, M1 is 19, the number of second shift registers is 36, and since the 1 st first DSP does not need to perform a delay, the output terminals of the 1 st and 36 th second shift registers may be connected to one input terminal of the 2 nd first DSP; connecting the output ends of the 2 nd and 35 th second shift registers with one input end of the 3 rd first DSP; the outputs of the 3 rd and 34 th second shift registers are connected to one input of the 4 th first DSP and so on.
In this embodiment of the application, the delay parameter between the first DSPs in the first DSP array may be determined according to the interpolation factor of the interpolation prototype filter, and stored in the memory of the storage array, so that when the controller acquires the signal input by the signal input end, the delay parameter may be retrieved from the memory storing the delay parameter, and sent to the second shift registers through the storage array, and then the signal input by the signal input end is delayed through the second shift registers, and then the delayed signal is sent to the first DSP connected to the second shift registers.
It should be noted that the manner of retrieving the delay parameter from the storage array is the same as the manner of retrieving the target parameter from the storage array, and specific implementation processes and principles may refer to the detailed description of the foregoing embodiments, which is not described herein again.
Step 204, sending the second delay parameter to the first shift register.
Step 205, the first mask parameter is sent to the second DSP array.
Step 206, sending the second mask parameter to the third DSP array to generate an FRM filter matched to the current working bandwidth.
In this embodiment of the application, since the configuration ends of the first shift register, the first DSP array, the second DSP array, and the third DSP array are all connected to the output end of the storage array, after the target parameter is obtained, the second delay parameter, the first shielding parameter, and the second shielding parameter included in the target parameter are respectively transmitted to the first shift register, the second DSP array, and the third DSP array through the configuration ends of the first shift register, the second DSP array, and the third DSP array, so that the first shift register, the second DSP array, and the third DSP array respectively adjust the internal parameters according to the respective parameters to generate the FRM filter matched with the current working bandwidth, and further, the generated FRM filter processes the signal input to the system at the signal input end to generate the processed signal.
According to the FRM filter generation method provided by the embodiment of the application, the target parameters corresponding to each working bandwidth are stored through the storage array, the target parameters corresponding to the current working bandwidth are called from the storage array through the controller and are sent to the FRM filter component, so that the FRM filter component generates the FRM filter matched with the current working bandwidth according to the target parameters; and the FRM filter component is designed through the complementary filter and the shielding filter, the DSP is multiplexed through the symmetrical parameters, and then a memory in the memory array is used for storing the parameters corresponding to the DSP, so that the FRM filter link multiplexing of the multi-bandwidth cell is realized, the resource occupation amount is reduced, the number of the DSPs is further reduced, the hardware complexity of the FRM filter is reduced, and the data reading speed is improved.
It should be noted that, the method provided in the embodiment of the present application can achieve all the functions achieved by the system embodiment and achieve the same technical effects, and detailed descriptions of the same parts and beneficial effects as the system embodiment in the embodiment are omitted here.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer-executable instructions. These computer-executable instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These processor-executable instructions may also be stored in a processor-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the processor-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These processor-executable instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.

Claims (11)

1. A frequency response masking filter system, comprising: a controller, a memory array and a frequency response mask FRM filter component;
one end of the controller is connected with the signal input end, and the other end of the controller is connected with the control end of the storage array;
the configuration end of the FRM filter component is connected with the output end of the storage array, the input end of the FRM filter component is connected with the signal input end, and the output end of the FRM filter component is used for outputting signals processed by FRM;
the controller configured to retrieve a target parameter corresponding to a current operating bandwidth from within the storage array to cause the storage array to send the target parameter to the FRM filter component;
the FRM filter component configured to generate a FRM filter that matches the current operating bandwidth according to the target parameters.
2. The system of claim 1 wherein the FRM filter component comprises: the digital signal processing device comprises a first shift register, a first Digital Signal Processor (DSP) array, a second DSP array, a third DSP array, an adder and a subtracter;
the configuration end of the first shift register, the configuration end of the first DSP array, the configuration end of the second DSP array and the configuration end of the third DSP array are respectively connected with the output ends of the storage array;
the input end of the first DSP array and the input end of the first shift register are connected with the signal input end, and the output end of the first DSP array is respectively connected with the input end of the second DSP array and the first input end of the subtracter;
the output end of the second DSP array is connected with the first input end of the adder;
the output end of the first shift register is connected with the second input end of the subtracter;
the output end of the subtracter is connected with the input end of the third DSP array;
the output end of the third DSP array is connected with the second input end of the adder;
the adder is configured to output the processed signal.
3. The system of claim 2,
the first DSP array comprises M1 first DSPs which are sequentially connected and are connected end to end, wherein M1 is a value obtained by rounding up N1/2;
the second DSP array comprises M2 second DSPs which are sequentially connected and are connected end to end, wherein M2 is a value obtained by rounding up N2/2;
the third DSP array comprises M3 sequentially connected third DSPs which are connected end to end, wherein M3 is a value obtained by rounding N3/2 upwards;
wherein N1 is the highest order of the interpolated prototype filter in each FRM filter corresponding to the system, N2 is the highest order of the first shielding filter in each FRM filter corresponding to the system, and N3 is the highest order of the second shielding filter in each FRM filter corresponding to the system.
4. The system of claim 3, further comprising: 2(M1-1) second shift registers connected in sequence;
the input end of the first second shift register is connected with the signal input end;
the configuration end of each second shift register is connected with the output end of a memory used for storing a first delay parameter in the memory array, and the output end of the ith second shift register and the output ends of the 2(M1-1) - (i-1) th second shift registers are respectively connected with one input end of the (i + 1) th first DSP, wherein i is a positive integer which is greater than 0 and less than or equal to M1-1.
5. The system of claim 4, wherein the storage array comprises K memories, wherein K is M1+ M2+ M3+2, and wherein M1 memories are respectively configured to store parameters corresponding to M1 first DSPs; m2 memories respectively configured to store parameters corresponding to the M2 second DSPs; m3 memories respectively configured to store parameters corresponding to M3 third DSPs, one memory configured to store second delay parameters corresponding to the first shift register, and the other memory configured to store first delay parameters corresponding to the M1-1 second shift register.
6. The system of claim 5, wherein said system is adapted to store L types of operating bandwidths, and wherein each of said memories has L types of parameters stored therein, said L types of parameters corresponding to said L types of operating bandwidths, respectively.
7. A method for generating a frequency response masking filter, comprising:
acquiring the current working bandwidth of the system;
reading a target parameter corresponding to the current working bandwidth from a storage array;
and sending the target parameters to an FRM filter component to generate an FRM filter matched with the current working bandwidth.
8. The method of claim 7, wherein reading the target parameter corresponding to the current operating bandwidth from the storage array comprises:
acquiring the corresponding relation between each parameter and the bandwidth in each memory of the memory array;
determining a target address corresponding to the current working bandwidth according to the corresponding relation between each parameter and the bandwidth and the position of each parameter in a memory;
and reading target parameters corresponding to the target address from the storage array.
9. The method of claim 8 wherein the interpolated prototype filter in the FRM filter corresponding to the current operating bandwidth has an order of N1, and wherein determining the target address corresponding to the current operating bandwidth based on the correspondence between the parameters and the bandwidth and the location of the parameters in the memory comprises:
determining M1 memories respectively corresponding to the interpolation prototype filter of the N1 order, wherein M1 is a value obtained by rounding up N1/2;
and determining M1 target addresses corresponding to the current working bandwidth according to the corresponding relation between each parameter and the bandwidth in each memory and the position of each parameter in the memory.
10. The method of claim 7 wherein the FRM filter component includes a first DSP array, a first shift register, a second DSP array, and a third DSP array, wherein the target parameters include a filter parameter, a second delay parameter, a first mask parameter, and a second mask parameter, and wherein sending the target parameters to the FRM filter component includes:
sending the filtering parameters to a first DSP array;
sending the second delay parameter to the first shift register;
sending the first mask parameter to the second DSP array;
and sending the second mask parameter to the third DSP array.
11. The method of claim 10 further comprising sequentially connected 2(M1-1) second shift registers in the FRM filter component, the target parameter further comprising a first delay parameter, the sending the target parameter to the FRM filter component comprising:
and respectively sending the first delay parameters to the 2(M1-1) second shift registers, wherein M1 is a value obtained by rounding up N1/2, and N1 is the highest order of an interpolated prototype filter in each FRM filter corresponding to the FRM filter component.
CN202011109562.1A 2020-10-16 2020-10-16 Frequency response masking filter system and method of generation Pending CN114389574A (en)

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