CN115267351A - Digital-analog hybrid synchronous detection method and related device for weak signals - Google Patents
Digital-analog hybrid synchronous detection method and related device for weak signals Download PDFInfo
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- CN115267351A CN115267351A CN202210924804.5A CN202210924804A CN115267351A CN 115267351 A CN115267351 A CN 115267351A CN 202210924804 A CN202210924804 A CN 202210924804A CN 115267351 A CN115267351 A CN 115267351A
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Abstract
The application discloses a digital-analog mixed synchronous detection method and a related device of weak signals, comprising the following steps: uniformly sampling the sinusoidal signals by a DDS (direct digital synthesis) technology and then re-synthesizing to obtain large-amplitude sinusoidal signals; inputting the large-amplitude sinusoidal signal into a voltage division module which comprises a 1M resistor and a 10K adjustable resistor connected in series for modulation, and obtaining a small-amplitude sinusoidal signal which comprises noise and is small in amplitude as a signal to be detected; phase-shifting and comparing the large-amplitude sinusoidal signals to generate common-frequency square wave signals; inputting the common-frequency square wave signal and the small-amplitude sine signal into a single-board lock-in amplifier for demodulation, and performing low-pass filtering integration on the demodulated signal to obtain a low-frequency signal close to direct current. Therefore, the technical problem that detection failure is caused by the influence of background noise in the prior art is solved.
Description
Technical Field
The present application relates to the field of weak signal detection technologies, and in particular, to a digital-analog hybrid synchronous detection method for a weak signal and a related device.
Background
The weak signal detection technology is an important branch of the existing detection technology, and comprises information theory, electronics, physics and the like, and the weak signal submerged in noise is detected and recovered by analyzing the reason and the rule of noise generation and researching the characteristics of the detected signal. For weak signal detection technology, the research focuses on how to effectively extract useful signals from strong noise, and new methods are continuously explored and researched to gradually improve the signal-to-noise ratio of signals output by a weak signal detection system.
The current weak signal detection methods mainly comprise the following methods: 1) Scanning weak signals through a biochip;
2) Weak vibration signal harmonic wavelet frequency domain extraction method; 3) A weak signal detection method based on noise and chaotic oscillator; however, the above methods have certain limitations. The main manifestation is that the threshold value of the signal-to-noise ratio of the detected weak signal is higher. Meanwhile, the weak signal detection method mainly adopts a linear filtering method to extract signals. Such methods generally fail if there is a strong background noise effect.
Disclosure of Invention
The application provides a digital-analog mixed synchronous detection method and a related device for weak signals, which are used for solving the technical problem that detection is invalid due to the fact that the prior art is easily influenced by background noise.
In view of this, a first aspect of the present application provides a digital-analog hybrid synchronous detection method for a weak signal, where the method includes:
uniformly sampling the sinusoidal signals by a DDS (direct digital synthesis) technology and then re-synthesizing to obtain large-amplitude sinusoidal signals;
inputting the large-amplitude sinusoidal signal into a voltage division module which comprises a 1M resistor and a 10K adjustable resistor connected in series for modulation, and obtaining a small-amplitude sinusoidal signal which comprises noise and is small in amplitude as a signal to be detected;
phase-shifting and comparing the large-amplitude sinusoidal signals to generate common-frequency square wave signals;
and inputting the common-frequency square wave signal and the small-amplitude sinusoidal signal into a single-board lock-in amplifier for demodulation, and performing low-pass filtering integration on the demodulated signal to obtain a low-frequency signal close to direct current.
Optionally, the step of inputting the large-amplitude sinusoidal signal into a voltage division module including a 1M resistor and a 10K adjustable resistor connected in series for modulation to obtain a small-amplitude sinusoidal signal including noise and having a small amplitude as a signal to be measured, and then further includes:
and amplifying the small-amplitude sinusoidal signal and performing high-pass filtering to obtain a single-path input signal of the single-board lock-in amplifier.
Optionally, the single-board lock-in amplifier specifically includes: an analog multiplier AD630;
the analog multiplier AD630 includes: a signal channel, a reference channel, a phase sensitive detector, and a low pass filter.
Optionally, the inputting the common-frequency square wave signal and the small-amplitude sinusoidal signal into a single-board lock-in amplifier for demodulation specifically includes:
inputting the large-amplitude sinusoidal signal into a reference channel, and inputting the small-amplitude sinusoidal signal into a signal channel; after the analog multiplier AD630 shifts the frequency of the small-amplitude sinusoidal signal to both sides of the same-frequency square wave signal and performs frequency-selective amplification, the phase-sensitive detector shifts the frequency of the small-amplitude sinusoidal signal back.
The second aspect of the present application provides a digital-analog hybrid synchronous detection system for weak signals, the system includes:
the generating unit is used for re-synthesizing the sinusoidal signals after uniformly sampling the sinusoidal signals by a DDS technology to obtain large-amplitude sinusoidal signals;
the modulation unit is used for inputting the large-amplitude sinusoidal signal into a voltage division module which comprises a 1M resistor and a 10K adjustable resistor in series for modulation, so that a small-amplitude sinusoidal signal which contains noise and is small in amplitude is obtained and serves as a signal to be detected;
the phase shifting unit is used for generating a common-frequency square wave signal after performing phase shifting comparison on the large-amplitude sinusoidal signal;
and the demodulation unit is used for inputting the common-frequency square wave signal and the small-amplitude sinusoidal signal into the single-board lock-in amplifier for demodulation, and performing low-pass filtering integration on the demodulated signal to obtain a low-frequency signal close to direct current.
Optionally, the method further comprises: a pre-processing module;
the preprocessing module is configured to amplify and high-pass filter the small-amplitude sinusoidal signal, and then use the amplified small-amplitude sinusoidal signal as an input signal of the single-board lock-in amplifier.
Optionally, the single-board lock-in amplifier specifically includes: an analog multiplier AD630;
the analog multiplier AD630 includes: a signal channel, a reference channel, a phase sensitive detector, and a low pass filter.
Optionally, the demodulation unit is specifically configured to:
inputting the large-amplitude sinusoidal signal into a reference channel, and inputting the small-amplitude sinusoidal signal into a signal channel; after the analog multiplier AD630 transfers the frequency of the small-amplitude sinusoidal signal to two sides of the same-frequency square wave signal and performs frequency-selective amplification, the phase-sensitive detector transfers the frequency of the small-amplitude sinusoidal signal back, and the transferred small-amplitude sinusoidal signal is subjected to low-pass filtering integration to obtain a near-direct-current low-frequency signal.
A third aspect of the present application provides a digital-analog hybrid synchronous detection device for weak signals, where the device includes a processor and a memory:
the memory is used for storing program codes and transmitting the program codes to the processor;
the processor is configured to execute the steps of the digital-analog hybrid synchronous detection method for weak signals according to the first aspect, according to instructions in the program code.
A fourth aspect of the present application provides a computer-readable storage medium, where the computer-readable storage medium is used to store a program code, and the program code is used to execute the digital-analog hybrid synchronous detection method for weak signals according to the first aspect.
According to the technical scheme, the method has the following advantages:
the application provides a digital-analog hybrid synchronous detection method of a weak signal, which comprises the following steps: uniformly sampling the sinusoidal signals by a DDS (direct digital synthesis) technology and then re-synthesizing to obtain large-amplitude sinusoidal signals; inputting the large-amplitude sinusoidal signal into a voltage division module which comprises a 1M resistor and a 10K adjustable resistor connected in series for modulation, and obtaining a small-amplitude sinusoidal signal which comprises noise and is small in amplitude as a signal to be detected; phase-shifting and comparing the large-amplitude sinusoidal signals to generate common-frequency square wave signals; inputting the common-frequency square wave signal and the small-amplitude sine signal into a single-board lock-in amplifier for demodulation, and performing low-pass filtering integration on the demodulated signal to obtain a low-frequency signal close to direct current.
Compared with the prior art, the method and the device firstly utilize the DDS technology to generate the sine wave; modulating the low-frequency weak signal, namely the signal to be detected, to obtain a noisy sinusoidal signal with small amplitude (the modulated low-frequency weak signal is also replaced by the voltage division of a sinusoidal wave generated by the singlechip DDS on an adjustable resistor in a series circuit of a 1M resistor and a 10K adjustable resistor); then the input sinusoidal signal is subjected to phase-shifting comparison to generate a common-frequency square wave signal; then the square wave signal and the small-amplitude sine signal obtained by voltage division are demodulated through an analog multiplier AD630, so that adverse effects such as 1/f noise, direct current drift and the like are suppressed; finally, the demodulated signal is finally output after selective integration of low-pass filtering. And then solved prior art and received background noise influence easily and lead to detecting the technical problem that became invalid.
Drawings
Fig. 1 is a schematic flowchart of an embodiment of a digital-analog hybrid synchronous detection method for a weak signal provided in an embodiment of the present application;
fig. 2 is a schematic structural diagram of an embodiment of a digital-analog hybrid synchronous detection system for a weak signal provided in an embodiment of the present application;
fig. 3 is a system block diagram of a single-board lock-in amplifier provided in an embodiment of the present application.
Detailed Description
In order to make the technical solutions of the present application better understood, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without making any creative effort belong to the protection scope of the present application.
Interpretation of terms:
weak signal detection: the weak signal detection technology is an important branch of the existing detection technology, and comprises information theory, electronics, physics and the like, and the weak signal submerged in noise is detected and recovered by analyzing the reason and the rule of noise generation and researching the characteristics of the detected signal. For weak signal detection technology, the research focuses on how to effectively extract useful signals from strong noise, and new methods are continuously explored and researched to gradually improve the signal-to-noise ratio of signals output by a weak signal detection system.
Referring to fig. 1, a digital-analog hybrid synchronous detection method for weak signals provided in an embodiment of the present application includes:
it should be noted that DDS (direct digital synthesis) can be understood as synthesizing signals of the same waveform and different frequencies after sampling from the original signal. This technique, which can be used to synthesize signals of arbitrary waveform frequencies by decimating from a variety of different waveforms, has been widely used in recent years. In essence, DDS is a method that uses digital techniques to generate a signal waveform. This method is based on sampling. The original signal waveform is sampled first, and then the sampled data is stored in a memory as a data table of the target signal waveform. When the waveform of the signal is output, the system reads out data from the data table in sequence to generate a digital signal, the digital signal is fitted into an analog signal through a DAC, and the frequency of the waveform can be adjusted through setting of a trigger clock. The complete digital frequency synthesizer is composed of a phase accumulator, an adder, a memory, a D/A converter, a low-pass filter and the like.
The chip of the invention is ad9834, and the C language programming is used.
And combining the requirement of generating the sine signal, uniformly sampling the sine signal through the DDS, and re-synthesizing to obtain the target signal. The frequency of the target signal is adjusted by controlling the time interval (i.e., the frequency control word) between every two adjacent samples. The data table stored in the memory contains the amplitude-phase information for one period of the signal to be generated, i.e. the sinusoidal signal. Each time a clock is triggered, the phase accumulator output is incremented by one step of phase increment, the size of which is determined by the frequency control word. Then, the amplitude value corresponding to the phase signal value output from the phase accumulator is read out from the data table, and the data is converted into an analog signal by the DAC and output. The phase accumulator now simultaneously performs the phase accumulation. This accumulation is linear. When the sum is accumulated to the limit, overflow occurs once, and finally the overflow rate is the frequency of the output signal. The accumulation of the phase accumulator is also cyclic, so that the output signal is a continuous signal.
Output frequency of DDS:
reference frequency f c N is the number of bits of the address of the quantized value in the waveform table, which is the clock frequency of the system. K is the sampling interval. In C language programming, the output frequency f can be adjusted by controlling k and n 0 . In the embodiment, a large-amplitude sinusoidal signal with a half-peak value of 5V, a frequency of 30KHz and a direct current bias of 0 is generated by the singlechip.
102, inputting the large-amplitude sinusoidal signal into a voltage division module containing a 1M resistor and a 10K adjustable resistor which are connected in series for modulation, and obtaining a small-amplitude sinusoidal signal which contains noise and is small in amplitude as a signal to be detected;
it should be noted that the large-amplitude sinusoidal signal obtained in step 101 is loaded to two ends of a series circuit of a 1M resistor and a 10K adjustable resistor for modulation, so as to obtain a small-amplitude sinusoidal signal which contains noise and has a small amplitude, and the small-amplitude sinusoidal signal is used as a signal to be measured.
103, amplifying the small-amplitude sinusoidal signal and performing high-pass filtering to obtain a single-path input signal of the single-board lock-in amplifier;
then, the small-amplitude sinusoidal signal obtained in step 102 is amplified and high-pass filtered to be used as one input signal of the single-board lock-in amplifier (the signal channel input to the single-board lock-in amplifier is shown in fig. 3).
It should be noted that the single-board lock-in amplifier of this embodiment is an analog multiplier AD630; the analog multiplier AD630 includes: a signal path, a reference path, a phase sensitive detector, and a low pass filter.
And 104, performing phase shift comparison on the large-amplitude sinusoidal signals to generate the same-frequency square wave signals.
Then, the large-amplitude sinusoidal signal is input into a reference channel of a single-board lock-in amplifier, and the large-amplitude sinusoidal signal forms a common-frequency square wave signal after phase-shifting comparison.
And 105, inputting the common-frequency square wave signal and the small-amplitude sine signal into a single-board lock-in amplifier for demodulation, and performing low-pass filtering integration on the demodulated signal to obtain a low-frequency signal close to direct current.
Referring to fig. 3, the principle of square wave demodulation is as follows: the lock-in amplifier first multiplies the low frequency signal by the frequency w 1 By shifting its frequency to the modulation frequency w 1 On both sides, frequency selective amplification is then performed, where 1/f noise and dc drift are suppressed. Then the frequency is shifted back to the vicinity of direct current by a phase sensitive detector, and finally an amplified signal with high signal-to-noise ratio is obtained by a narrow-band low-pass filter. The principle that the modulation amplifier uses alternating current amplification is embodied, and 1/f noise is suppressed. The basic structure of the lock-in amplifier is shown in fig. 3, and includes a signal channel, a reference channel, a Phase Sensitive Detector (PSD), a Low Pass Filter (LPF), and the like. The signal channel is internally used for carrying out alternating current amplification on the input of the modulation signal, amplifying the weak signal to the working range of the phase sensitive detector, and simultaneously filtering partial interference and noise. Since different sensors are used for different measurement objects, the output impedances of the sensors are different from each other. For optimum noise characteristics, the input impedance of the signal path is matched to the corresponding sensor output impedance.
The PSD takes the reference signal r (t) as a benchmark to carry out phase-sensitive detection on the signal x (t) to be detected, thereby realizing secondary migration of the frequency spectrum. The frequency spectrum of x (t) is formed by w o The position is shifted to 0, and noise is filtered by a low-pass filter.
The lock-in amplifier detection principle has 3 basic points: (1) The modulator shifts the frequency spectrum of the DC or slowly varying signal to a modulation frequency omega 0 And amplifying again to suppress the adverse effect of 1/f noise.(2) The demodulation process of the modulated signal is realized by using a phase sensitive detector, and the frequency omega can be simultaneously used 0 And the phase angle theta is detected, and the probability that the noise and the signal have the same frequency and phase is very low. And (3) suppressing broadband noise by using a low-pass filter. The band of the low-pass filter can be made narrow and its bandwidth is not affected by the modulation frequency.
The signal x (t) to be measured is a sine wave containing noise, and the embodiment obtains the synchronous square wave signal r (t) through phase shift comparison to demodulate the x (t) signal.
The signal to be measured can be expressed as:
x(t)＝V s cos(ω 0 t+θ)+n(t)
in the formula, n (t) is noise. The reference signal r (t) can be expressed as:
substituting, the output of the analog multiplier is:
finally, the sum frequency term of the signal represented by the second term of the above expression and the reference is filtered out by an LPF (low pass filter). The third case is more complex, but as long as the LPF equivalent noise bandwidth is sufficiently narrow, a satisfactory signal-to-noise ratio can be obtained.
The digital-analog mixed synchronous detection method for the weak signal in the embodiment is based on the digital-analog mixed synchronous detection of the weak signal of the single chip microcomputer, and utilizes the sinusoidal signal generated by the single chip microcomputer DDS, the 10K adjustable resistor and the 1M large resistor to be connected in series for voltage division to adjust and form the weak sinusoidal input signal, so that the final digital-analog mixed synchronous detection is realized on the single-board phase-locked amplifier. After entering the single-board phase-locked amplifier, the weak sinusoidal signal is pre-amplified, and simultaneously the sinusoidal signals generated by the single-chip DDS at the two ends of the large resistor and the adjustable resistor are simulated and compared in a phase-shifting manner to generate a common-frequency square wave signal. The analog carrier signal is demodulated with a square wave signal using the AD630 through lock-in amplification techniques. And then a low-frequency signal related to the weak signal is obtained through a low-pass filter.
The foregoing is a digital-analog hybrid synchronous detection method for a weak signal provided in this embodiment, and the following is a digital-analog hybrid synchronous detection system for a weak signal provided in this embodiment.
Referring to fig. 2, in an embodiment of the present application, a digital-analog hybrid synchronous detection method for weak signals includes:
the generating unit 201 is configured to perform uniform sampling on the sinusoidal signal through a DDS technique and then re-synthesize the sinusoidal signal to obtain a large-amplitude sinusoidal signal;
the modulation unit 202 is configured to input the large-amplitude sinusoidal signal into a voltage division module including a 1M resistor and a 10K adjustable resistor connected in series for modulation, so as to obtain a small-amplitude sinusoidal signal which includes noise and has a small amplitude, and serve as a signal to be measured;
the preprocessing module 203 is configured to amplify and high-pass filter the small-amplitude sinusoidal signal, and then use the amplified small-amplitude sinusoidal signal as an input signal of the single-board lock-in amplifier;
the phase shifting unit 204 is used for performing phase shifting comparison on the large sinusoidal signals and then generating the same-frequency square wave signals;
the demodulation unit 205 is configured to input the common-frequency square wave signal and the small-amplitude sine signal to the single-board lock-in amplifier for demodulation, and perform low-pass filtering and integration on the demodulated signal to obtain a low-frequency near-dc signal.
Further, in this embodiment, the apparatus for digital-analog hybrid synchronous detection of a weak signal includes a processor and a memory:
the memory is used for storing program codes and transmitting the program codes to the processor;
the processor is configured to execute the digital-analog hybrid synchronous detection method for the weak signal according to the instruction in the program code.
Further, in an embodiment of the present application, a computer-readable storage medium is provided, where the computer-readable storage medium is used to store a program code, and the program code is used to execute the digital-analog hybrid synchronous detection method for weak signals according to the foregoing method embodiment.
It can be clearly understood by those skilled in the art that, for convenience and simplicity of description, the specific working processes of the above-described systems and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
The terms "first," "second," "third," "fourth," and the like (if any) in the description of the present application and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged under appropriate circumstances such that the embodiments of the application described herein may be implemented, for example, in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
It should be understood that in the present application, "at least one" means one or more, "a plurality" means two or more. "and/or" is used to describe the association relationship of the associated object, indicating that there may be three relationships, for example, "a and/or B" may indicate: only A, only B and both A and B are present, wherein A and B may be singular or plural. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. "at least one of the following" or similar expressions refer to any combination of these items, including any combination of the singular or plural items. For example, at least one (one) of a, b, or c, may represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", wherein a, b and c may be single or plural.
In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other manners. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one type of logical functional division, and other divisions may be realized in practice, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application, which are essential or part of the technical solutions contributing to the prior art, or all or part of the technical solutions, may be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.
The above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions in the embodiments of the present application.
Claims (10)
1. A digital-analog mixed synchronous detection method of weak signals is characterized by comprising the following steps:
uniformly sampling the sinusoidal signals by a DDS (direct digital synthesis) technology and then re-synthesizing to obtain large-amplitude sinusoidal signals;
inputting the large-amplitude sinusoidal signal into a voltage division module which comprises a 1M resistor and a 10K adjustable resistor connected in series for modulation, and obtaining a small-amplitude sinusoidal signal which comprises noise and is small in amplitude as a signal to be detected;
phase-shifting and comparing the large-amplitude sinusoidal signals to generate common-frequency square wave signals;
and inputting the common-frequency square wave signal and the small-amplitude sinusoidal signal into a single-board lock-in amplifier for demodulation, and performing low-pass filtering integration on the demodulated signal to obtain a low-frequency signal close to direct current.
2. The digital-analog hybrid synchronous detection method of the weak signal according to claim 1, wherein the large-amplitude sinusoidal signal is input into a voltage division module comprising a 1M resistor and a 10K adjustable resistor connected in series for modulation, so as to obtain a small-amplitude sinusoidal signal with low noise and small amplitude as a signal to be detected, and then the method further comprises:
and amplifying the small-amplitude sinusoidal signal and performing high-pass filtering to obtain a single-path input signal of the single-board lock-in amplifier.
3. The digital-analog hybrid synchronous detection method of the weak signal according to claim 1, wherein the single-board lock-in amplifier specifically comprises: an analog multiplier AD630;
the analog multiplier AD630 includes: a signal channel, a reference channel, a phase sensitive detector, and a low pass filter.
4. The digital-analog hybrid synchronous detection method of the weak signal according to claim 3, wherein the inputting the common-frequency square wave signal and the small-amplitude sinusoidal signal into a single-board lock-in amplifier for demodulation specifically comprises:
inputting the large-amplitude sinusoidal signal into a reference channel, and inputting the small-amplitude sinusoidal signal into a signal channel; and after the analog multiplier AD630 transfers the frequency of the small-amplitude sinusoidal signal to two sides of the same-frequency square wave signal and performs frequency-selective amplification, the phase-sensitive detector transfers the frequency of the small-amplitude sinusoidal signal back.
5. A digital-analog hybrid synchronous detection system for weak signals is characterized by comprising:
the generating unit is used for re-synthesizing the sine signals after uniformly sampling the sine signals through a DDS technology to obtain large-amplitude sine signals;
the modulation unit is used for inputting the large-amplitude sinusoidal signal into a voltage division module which comprises a 1M resistor and a 10K adjustable resistor in series for modulation, so that a small-amplitude sinusoidal signal which contains noise and is small in amplitude is obtained and serves as a signal to be detected;
the phase shifting unit is used for performing phase shifting comparison on the large sinusoidal signals and then generating common-frequency square wave signals;
and the demodulation unit is used for inputting the common-frequency square wave signal and the small-amplitude sinusoidal signal into the single-board lock-in amplifier for demodulation, and performing low-pass filtering integration on the demodulated signal to obtain a low-frequency signal close to direct current.
6. The weak signal digital-analog hybrid synchronous detection system according to claim 5, further comprising: a preprocessing module;
the preprocessing module is configured to amplify and high-pass filter the small-amplitude sinusoidal signal, and then use the amplified small-amplitude sinusoidal signal as an input signal of the single-board lock-in amplifier.
7. The digital-analog hybrid synchronous detection system of the weak signal according to claim 5, wherein the single-board lock-in amplifier specifically comprises: an analog multiplier AD630;
the analog multiplier AD630 includes: a signal channel, a reference channel, a phase sensitive detector, and a low pass filter.
8. The digital-analog hybrid synchronous detection system of the weak signal according to claim 5, wherein the demodulation unit is specifically configured to:
inputting the large-amplitude sinusoidal signal into a reference channel, and inputting the small-amplitude sinusoidal signal into a signal channel; after the analog multiplier AD630 transfers the frequency of the small-amplitude sinusoidal signal to two sides of the same-frequency square wave signal and performs frequency-selective amplification, the phase-sensitive detector transfers the frequency of the small-amplitude sinusoidal signal back, and the transferred small-amplitude sinusoidal signal is subjected to low-pass filtering integration to obtain a low-frequency signal close to direct current.
9. A weak signal digital-analog hybrid synchronous detection device, comprising a processor and a memory:
the memory is used for storing program codes and transmitting the program codes to the processor;
the processor is configured to execute the digital-analog hybrid synchronous detection method for weak signals according to any one of claims 1 to 4 according to instructions in the program code.
10. A computer-readable storage medium, characterized in that the computer-readable storage medium is used for storing program codes for performing the digital-analog hybrid synchronous detection method of weak signals according to any one of claims 1 to 4.
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| CN116248050A (en) * | 2023-05-08 | 2023-06-09 | 国仪量子(合肥)技术有限公司 | Phase-locked amplifier, signal device detection method and signal processing method |
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| CN116248050A (en) * | 2023-05-08 | 2023-06-09 | 国仪量子(合肥)技术有限公司 | Phase-locked amplifier, signal device detection method and signal processing method |
| CN116248050B (en) * | 2023-05-08 | 2023-07-11 | 国仪量子(合肥)技术有限公司 | Phase-locked amplifier, signal device detection method and signal processing method |
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