CA2865133C - Flux modulation scheme for squid signal processing circuitry - Google Patents

Abstract

A signal processing circuitry for a SQUID comprising: a signal processing module coupled to receive a SQUID output signal, the signal processing module comprising a modulator and a phase tracking component; an integrator coupled to an output of the signal processing module; a feedback circuit arranged to provide a feedback signal to the SQUID in a FLL arrangement, the feedback signal including an integrator output signal, wherein the integrator output signal is modulated by a quadrature modulation from the modulator; the phase tracking module is configured to demodulate and unwrap a phase angle of the output of the SQUID and provide the unwrapped phase angle to the integrator.

Description

FLUX MODULATION SCHEME FOR SQUID SIGNAL PROCESSING
CIRCUITRY
Described embodiments relate generally to signal processing circuitry and methods for superconducting quantum interference devices (SQUIDs) that employ a flux modulation scheme. Some embodiments relate to sensor systems comprising such circuitry and/or configured to perform such methods. Particular embodiments may use Back2round Superconducting quantum interference devices (SQUIDs) can be used for high sensitivity magnetic field detection. Sensor systems that incorporate SQUIDs can be used in ground and air based geo-magnetic surveying techniques, including time SQUID readout electronics that are currently available generally fall into two distinct Existing FLL readout electronics use a SQUID to sense magnetic flux but because the SQUID' s transfer function is non-linear and periodic, an integrator is used to feed back the accumulated signal to a coil that balances the flux at the SQUID. This balancing closed. The current in the feedback coil is linear and directly proportional to the field surrounding the SQUID and coil. As long as the rate of change of the measured flux is low enough, the FLL will remain balanced and the SQUID will see a constant flux. As the flux's slew rate increases, the error in the loop increases and the SQUID
sees more and more flux. The increasing flux moves the SQUID along its periodic transfer function until a peak is reached, at which point the loop loses lock and the original reference point is lost, invalidating further measurements.
It is desired to address or ameliorate one or more shortcomings or disadvantages associated with prior SQUID signal processing techniques, or to at least provide a useful alternative thereto.
Throughout this specification the word "comprise", or variations such as "comprises" or "comprising", will be understood to imply the inclusion of a stated element, integer or step, or group of elements, integers or steps, but not the exclusion of any other element, integer or step, or group of elements, integers or steps.
Any discussion of documents, acts, materials, devices, articles or the like which has been included in the present specification is not to be taken as an admission that any or all of these matters foul' part of the prior art base or were common general knowledge in the field relevant to the present disclosure as it existed before the priority date of each claim of this application.
Summary Described embodiments generally employ a flux modulation scheme to allow high slew rates in flux-locked-loop SQUID sensor systems. Described embodiments use a flux modulation and signal processing scheme that effectively linearizes the SQUID' s periodic transfer function.
Signal processing circuitry for a super-conducting quantum interference device (SQUID), the circuitry comprising:

a signal processing module coupled to receive a SQUID output signal, the signal processing module comprising a modulator and a phase tracking component;
an integrator coupled to an output of the signal processing module to integrate a signal processing module output;
a feedback circuit coupled to an output of the integrator and arranged to provide a feedback signal to the SQUID in a flux locked loop (FLL) arrangement, the feedback signal including an integrator output signal from the integrator, wherein the integrator output signal is modulated by a quadrature modulation signal from the modulator;
wherein the phase tracking module is configured to demodulate and unwrap a phase angle of the output of the SQUID and provide the unwrapped phase angle to the integrator.
The signal processing module may be implemented in a field-programmable gate array (FPGA). The circuitry may further comprise an analogue-to-digital converter (ADC) to receive an output signal of the SQUID and convert the output signal to a digitised SQUID signal. The circuitry may further comprise a digital-to-analogue converter (DAC) coupled to an output of the signal processing module to provide the unwrapped phase angle to the integrator.
The phase tracking module may comprise a pair of demodulators to demodulate the SQUID output signal and output in-phase and quadrature signal components, the demodulators receiving synchronisation signals from the modulator. The phase tracking module may further comprise a phase detection module to receive the in-phase and quadrature signal components and determine a phase of the SQUID output signal based on the in-phase and quadrature signal components and to output a phase signal.
The circuitry may further comprise a phase unwrapping module to receive the phase signal and to unwrap the phase of the SQUID output signal based on the received phase signal.
The circuitry may have a digital circuitry section and an analogue circuitry section, wherein the analogue circuitry section is arranged to have a differential signalling architecture to minimise the effect of signal crosstalk in the analogue section. The signal processing module may be part of the digital circuitry section and the integrator and the feedback circuit may be part of the analogue circuitry section.

Some embodiments relate to a housing comprising the circuitry described above, wherein the housing further comprises signal isolation structure to isolate the SQUID, the integrator and the feedback circuit from radio-frequency interference generated by the signal processing module. The signal isolation structure may comprise conductive isolation walls positioned to define compartments between which minimal radio frequency noise passes.
Some embodiments relate to a signal processing method for a SQUID in a flux locked loop arrangement, the method comprising:
converting an amplified analogue output signal of the SQUID to a digital signal, wherein the analogue output of the SQUID comprises a quadrature modulation signal component;
processing the digital signal to demodulate and unwrap a phase angle of the SQUID output signal;
integrating the unwrapped phase angle to generate a feedback signal to the SQUID;
modulating the feedback signal with a quadrature modulation signal.
The method may further comprise converting the unwrapped phase angle to an analogue signal version, wherein the integrating uses the analogue signal version of the unwrapped phase angle. The quadrature modulation signal may vary cyclically in four steps or comprise another suitable cyclic signal that can be used to extract quadrature phase information from the SQUID output signal.
The processing may comprise demodulating the SQUID output signal into in-phase and quadrature signal components, detemiining the phase of the SQUID output signal based on the in-phase and quadrature signal components and generating the unwrapped phase angle based on the detected phase.
The detecting may comprise performing a Cartesian-to-polar signal conversion of the in-phase and quadrature signal components to determine the phase.
Some embodiments relate to a sensor system, comprising:
a superconducting quantum interference device (SQUID);
signal processing circuitry coupled to receive an output of the SQUID;
an integrator arranged to receive an output of the signal processing circuitry; and a feedback section coupled to an output of the integrator and the SQUID in a flux locked loop (FFL) arrangement;
wherein the signal processing circuitry is arranged to modulate the output of the integrator with a quadrature modulation signal so that the output of the SQUID
includes 5 the quadrature modulation signal as one signal component of the SQUID
output; and wherein the signal processing circuitry is further arranged to demodulate the SQUID output, to unwrap a phase angle of the output of the SQUID and to provide the unwrapped phase angle to the integrator.
The signal processing circuitry may be implemented in digital circuitry and the integrator and the feedback section may be implemented in analogue circuitry.
The signal processing circuitry may be arranged to generate a phase-shifted version of the SQUID output to map the SQUID output and the phase-shifted version to polar coordinates and to unwrap the phase angle based on the polar coordinates.
The output of the integrator is provided as an output of the sensor system.
The signal processing circuitry may comprise a field-programmable gate array (FPGA) configured to comprise a modulation generator to generate the modulation signal and a phase unwrapping component to unwrap the phase angle.
Brief Description of the Drawin2s Embodiments are described in further detail below by way of example and with reference to the accompanying drawings, in which:
Figure 1 is a block diagram of a SQUID sensor system including SQUID signal processing circuitry according to described embodiments;
Figure 2 is an example schematic diagram of a model of the system of Figure 1, showing some parts of the system in further detail;
Figure 3A is an example unmodulated SQUID response signal;
Figure 3B is an example flux modulation signal;

Figure 3C is an example modulated SQUID response signal resulting from the phase shifting action of the signal shown in Figure 3B when applied to the signal shown in Figure 3A;
Figure 4 is an example schematic logic diagram for a modulator in the signal processing circuitry;
Figures 5A, 5B, 5C, 5D, 5E. 5F and 5G are signal plots showing a modulated SQUID
signal with an offset, together with demodulated in-phase and quadrature signals derived from the modulated SQUID signal;
Figure 6 is an example logic diagram of a demodulation function perfoinied by each of two demodulators;
Figure 7 is an example schematic logic diagram of a sample memory used in each of the demodulators;
Figures 8A, 8B, 8C and 8D are signal plots illustrating Cartesian to polar conversion of the in-phase and quadrature signals;
Figures 9A, 9B and 9C are signal plots showing the demodulated in-phase and quadrature SQUID signals as input to a phase detector module, with the resulting detected phase angle of the SQUID signal shown in Figure 9C;
Figure 10 is an example schematic logic diagram of a phase detector module;
Figures 11A, 11B and 11C are phase angle plots showing the output of the phase detector, the accumulated phase steps and the output of the phase un-wrapping module, respectively.
Figure 12 is an example schematic logic diagram of the phase un-wrapping module;

Figures 13A and 13B are signal plots illustrating the net effect of the flux linearization process performed by the digital processing circuitry; and Figure 14 is a flowchart of a method of SQUID signal processing using a quadrature modulation signal.
Detailed Description Described embodiments relate generally to signal processing circuitry and methods for SQUIDS that employ a flux modulation scheme within a flux locked loop (FLL) arrangement. Some embodiments relate to sensor systems comprising such circuitry or configured to perform such methods. Particular embodiments use a quadrature flux modulation scheme. The quadrature flux modulation scheme described herein significantly increases the maximum slew rate available from a FLL SQUID system while maintaining its high dynamic range and excellent noise perfoimance.
In general tetins, described embodiments use a flux modulation and signal processing scheme that effectively linearizes the SQUID' s periodic (e.g. sinusoidal) transfer function prior to the integrator and feedback coil to implement a sensor system that can handle a very high slew rate and that does not compromise noise performance.
The modulation and processing scheme can be implemented on a Field Programmable Gate Array (FPGA) or other digital processing platform including a Digital Signal Processing (DSP) chip. While the modulation and signal processing section operates in the digital domain, the other sections of the system (including the integrator) operate in the analogue domain. This arrangement of digital signal processing with analogue integration and feedback is significant since it is the analogue integrator being driven by the digital signal processor that gives the system its large dynamic range and low noise.
While a conventional FLL loses lock if the slew rate pushes the SQUID more than 1/4 of a cycle away from the lock point, the described modulation and processing scheme, along with analogue integration and feedback, allows the system to track much higher slew rates by remaining in lock over many cycles of the SQUID' s transfer function.
In contrast, a flux quanta counting system exposes the SQUID to the full variation of the measured field, which can increase the SQUID' s intrinsic noise because of flux creep into the device. Compared to a flux quanta counting system, the described embodiments keep the SQUID in a field that is very close to the field seen at the time of loop closure and hence does not degrade the SQUID's noise performance.
The SQUID' s transfer function is linearized using the following method. As in a normal modulated FLL system, a repetitive flux modulation signal 41), along with the flux feedback signal A, are presented to the SQUID using a coil, where they are summed with the flux to be measured (0). In the described embodiments, however, the modulation signal is a repetition of four steps that shift the SQUID' s output response back and forth through one complete cycle at intervals of 0, 90, 180 and 270 degrees.
The output of the SQUID (at an appropriate bias level) can be simplistically described as COS(0 + 41) + A). By sampling and storing the SQUID' s response at each of the modulation steps and taking the previously measured residual field (CI ¨ A) into account, the SQUID' s cyclic transfer function can be unwrapped to give a linear measurement of residual flux.
To calculate the residual flux, the modulated SQUID signal is synchronously demodulated using the modulation signal as a reference. The signal is demodulated into the complex domain with the in-phase and quadrature components being transformed from rectangular (Cartesian) to polar co-ordinates. The polar angle of the signal will rotate clock-wise or anti clock-wise through 360 degrees for every flux quantum increase or decrease that the SQUID sees. Using the assumption that the flux has not changed by more than 180 degrees since the last sample, the phase angle can be unwrapped into a linear representation of the residual flux seen by the SQUID.
The un-wrapped phase angle represents the residual field independently of the signal amplitude.

The modulated output signal received from the SQUID is split and sent to two separate demodulators, where alternate 180 phases of the signal are subtracted from each other and either held constant or fed live to the rectangular to polar conversion unit. The magnitude component may be discarded and the phase angle component is then unwrapped into a linear measurement of the flux locked loop error signal. The linear error signal is then fed to the integrator to produce feedback signal. In some embodiments, the magnitude component could be used to provide further information about the SQUID signal.
In a conventional FLL, the slew rate is limited by the reduction of loop gain as the loop moves further away from its equilibrium point due to the slewing field and the periodic nature of the SQUID transfer function. Using the linearized SQUID signal removes the loop gain reduction problem and at the same time allows more sophisticated feedback techniques like pole/zero compensation or state space control to be used in the loop design, resulting in significant improvement in system slew rates.
Referring to Figure 1, there is shown a schematic diagram of a sensor system incorporating a SQUID 102 as the sensing element. Sensor system 100 comprises a housing 103 to house analogue signal processing circuitry (described further below) and digital signal processing circuitry 115 to interface with the SQUID 102 in the FLL.
The SQUID 102 interfaces with the digital circuitry via an analogue-to-digital converter (ADC) 112 and the digital circuitry interfaces with other analogue circuitry via three digital-to-analogue converters (DAC) 122, 124 and 126.
Digital signal processing circuitry 115 may be implemented in one or more specially configured or programmed digital signal processors or it may be implemented in a field programmable gate array (FPGA). Digital signal processing circuitry 115 executes digital logic functions as configured to provide the functions of a modulation generator 140, a phase tracking module 130, a bias control module 128 and optionally an AC bias signal generator module 129 as described herein. The phase tracking module 130 also performs a demodulation function, as described in more detail below.
The analogue circuitry of system 100 includes a bias current driver 162 responsive to 5 the bias control module 128 (via DAC 122) to provide a suitable bias current to SQUID
102. The analogue circuitry of system 100 also includes an integrator 152 that receives an unwrapped phase signal from phase tracking module 130 via DAC 126. The integrator 152 provides its output to a feedback coil driver 154 to drive a feedback coil 192 that closes the flux locked loop. An output measurement driver 156 derives an 10 output measurement signal 170 from the output of the integrator 152 (optionally via the feedback coil driver 154). The analogue circuitry of system 100 also includes a modulation coil driver 164 responsive to the modulation generator 140 (via the DAC
124) to drive a modulation coil 194. The modulation coil 194 couples the quadrature modulation signal to the feedback signal supplied to the SQUID 102 from feedback coil 192 so that the quadrature modulation signal propagates to the SQUID output.
SQUIDs are generally intolerant of any radio-frequency interfering signals and care must be exercised in the design of the SQUID signal processing circuitry (also called readout electronics herein) to prevent the SQUID signal from being corrupted or even completely suppressed. The described SQUID readout electronics hardware platfoim utilises a compartmentalised structure, as shown in Figure 1, that effectively isolates the SQUID from the radio-frequency emissions generated by the digital signal processing section. This compartmentalised structure is provided by the housing 103, which keeps the RF emissions from the digital processing circuitry 115 and parts of the ADC 112 and DACs 122,124 and 126 shielded from the analogue circuits by grounded conductive divider walls of the housing 103. The conductive divider walls thus define a digital signal processing section 110, an analogue input section 105 (providing input to digital section 110 from the SQUID 102), an analogue output section 150 and a feedback and sensing section 104.

Although the SQUID 102 is shown as being in the housing 103, it may actually be in a separate external housing. The SQUID 102 is shown in Figure 1 as a part of the sensor system 100, but the analogue and digital signal processing circuitry of the sensor system 100 may be deployed in a separate unit (i.e. housing 103) from the SQUID 102, which requires a special cooling environment.
To minimise signal crosstalk and maximise the interference rejection capability of the analogue sections 104. 105 and 150 of the signal processing circuitry, a fully differential signalling architecture has been adopted in those sections of sensor system 100. Additionally, within the digital signal processing section 110, all high-speed signalling lines utilise a differential signalling architecture to minimise radiated interference.
The sensor system 100 achieves most of the described signal processing functions using a field programmable gate array (FPGA), which is surrounded by a high speed analogue to digital converter (ADC) 112 and several high-speed digital to analogue converters (DACs) 122, 124 and 126. The ADC 112 is connected to a very low noise preamplifier 108, which is used to measure the output voltage signal from the SQUID
102. The DACs 122, 124 and 126 have three primary functions: the first function (performed by DAC 126) is to drive the feedback integrator 152 with processed data from the SQUID 102 and hence close the flux locked loop; the second function (performed by DAC 124) is to provide the quadrature flux modulation signal to the SQUID 102 and the third function (performed by DAC 122) provides bias current for the SQUID device responsive to bias control module 128.
Optionally, the sensor system 100 may operate in an AC bias mode in order to reduce the intrinsic low frequency noise of the SQUID 102. For this purpose, an AC
bias signal generator module 129 may be employed in order to provide a plus one or minus one (+/- 1) multiplying factor to the bias control signal provided by bias control module 128 to DAC 122 and the input to the demodulator and phase tracking module 130.
The frequency of the AC bias signal thus provided by the AC bias signal generator module 129 and coupled synchronously to the output of ADC 112 and to the input of DAC

may be in the range of about 50kHz ¨ 1MHz for example. The AC bias signal generator 129 can be synchronised to the modulation generator 140 in order to reduce the impact of switching transients on the demodulated SQUID signal. The AC
bias signal generator module 129 may be implemented as finnware in the digital signal processing circuitry 115 (FPGA), for example, or may be implemented as hardware outside of the FPGA.
The ADC 112 and DACs 122, 124 and 126 may each have appropriate signal filtering circuitry associated therewith. For example, ADC 112 may have a high-pass and anti-alias filter 205 (Figure 2) positioned between the ADC input and the SQUID
output.
The DACs 122, 124 and 126 may have reconstruction filters (not shown) associated therewith.
The digital signal processing circuitry 115 comprises at least the following modules, which are described in further detail below.
= A modulation generator 140 that produces the quadrature modulation signal for the SQUID and also produces the synchronising signals for the detectors.
= A pair of demodulators 212, 214 that use synchronous detectors to demodulate the SQUID signal into in-phase and quadrature components.
= A phase detector module 220 that utilises a rectangular to polar coordinate transform that takes the in-phase and quadrature SQUID signal components and produces a phase angle signal.
= A phase un-wrapping module 230 that takes the SQUID phase signal and extends the phase representation beyond 360 to provide an unwrapped phase signal as output to the integrator 152.
Referring also to the logic diagram of Figure 2, the schematic elements on the left side of the input / output ports are generally representative of the SQUID 102, the external magnetic field 202 to be sensed and other components that operate in the analogue domain, as well as some control values needed by the digital logic. The schematic components on the right of the input / output ports are the digital logic elements that exist inside the FPGA and perform the digital signal processing of the SQUID
signal.
Figure 2 illustrates that the demodulators 212, 214, phase detector 220 and phase unwrapping module 230 fonn part of the phase tracking module 130. Modulator receives a modulation gain parameter 142 and modulation phase parameter 144 as input. These parameters may be set as configurable input constants. Analogue circuitry of the integrator 152 is also shown in Figure 2, although the integrator gain may be set at least in part by a digital gain circuit 152a that amplifies the phase output signal from the phase unwrapping module 230 by a configurable loop gain constant 252. The digital gain circuit 152a comprises a multiplier 240 that is used along with the analogue integrator' s gain to set the loop gain of the system. The loop gain determines both the maximum slew rate and the loop stability and so must be adjusted to optimise both.
To gather the in-phase and quadrature components of the SQUID signal, a flux modulation signal is needed. The modulation signal must shift the SQUID' s response back and forth by 90 and at a rate that is fast enough to capture the highest rate of change of the flux to be measured. By shifting the SQUID signal back and forth through 90 steps, the SQUID signal is effectively converted into a time division multiplexed signal containing both in-phase and quadrature signal components.
These signal components can be viewed as the Cartesian coordinates of the SQUID's current position within a circular transfer function, as described below in relation to Figures 8A
to 8D.
The modulation signal generated by the modulation generator 140 is a repetition of four steps that shift the SQUID' s output response back and forth through one complete cycle at intervals of 0, 90, 180 & 270 degrees. The four steps allow the unwanted DC

component of the SQUID signal to be subtracted from the signal during the demodulation process. The signal plots in Figures 3A, 3B and 3C illustrate the effect of the modulation flux on the SQUID signal over a period of two flux quanta, showing the unmodulated SQUID output signal (Figure 3A), the modulation signal (Figure 3B) and the modulated SQUID output signal (Figure 3C) as the result of phase shifting of the unmodulated SQUID output by the modulation signal.
The logic functions and components of the modulation generator 140 are shown in more detail in Figure 4. As indicated in the logic diagram in Figure 4, the modulation generator 140 may be implemented using a ROM-based lookup table. The relative levels of the modulation signal are stored in a read-only memory (ROM) 405, with each memory location corresponding to each of 200 clock cycles used to construct the modulation wavefolin. As the modulation generator 140 cycles through the lookup table in ROM 405, the output values from ROM 405 are multiplied by a modulation gain value 142 using a multiplier 410 selected to scale the signal so that the particular SQUID device being used is modulated with steps of exactly 90 .
Modulation generator 140 also contains circuitry to implement a logic block 420 that generates four synchronising output signals (Sync 0, Sync 1, Sync 2 and Sync 3) that are required by the demodulation modules 212, 214. The phase of the synchronising signals are adjustable (by selection of the value of the phase control input 144) to compensate for the propagation time of the modulation signal and SQUID signal through the various analogue circuits in the sensor system 100.
While one method for generating the modulation signal has been described, there are other ways to produce the stepped modulation waveform used in this implementation.
One example of an alternate generation scheme is a simple sequential state machine driven by a clock divider. The modulation waveform itself could be any suitable waveform that sweeps the SQUID response through at least 90 . Waveforms that could be used include sine waves, triangular waves or any other suitable repetitive waveform, for example, provided that an appropriate demodulation scheme can be designed.
The purpose of the demodulator modules 212, 214 is to reconstruct both the in-phase and quadrature components of the SQUID output signal from the time division multiplexed signal. One demodulator module 212 is responsible for reconstructing the in-phase signal component and the other demodulator module 214 is responsible for reconstructing the quadrature signal component.
Due to the time multiplexed nature of the signal, only one of the in-phase and 5 quadrature signal components is available at any instant in time.
However, both components are needed simultaneously for the later processing stages. If the modulation rate is sufficiently fast compared to the rate of change of the unmodulated SQUID signal, a reasonable estimate of the unavailable component can be obtained by simply substituting the average value of the previous block of data for that component.
10 Other embodiments may use different ways of estimating the unavailable in-phase or quadrature component, provided suitable accurate estimates are thus obtained.
Each demodulator' s task is to either pass the current SQUID signal directly through or output the stored average of the last block of direct data (or other estimate of the unavailable signal) at the appropriate instant in time.
A further extension of this principle allows removal of the unwanted DC
component of the SQUID signal by subtracting the signal produced when the modulation step is at 180 from the signal produced when the modulation step is at 0 . The application of the demodulation process on an example modulated SQUID output signal is illustrated by the waveform plots shown in Figures 5A to 5G.
The signals represented in Figures 5A to 5G are the modulated SQUID signal including an unwanted DC offset (Figure 5A), the demodulated in-phase 0 and 180 signals (Figures 5B, 5C) and quadrature 90 and 270 signals (Figures 5D, 5E) and the final output in-phase and quadrature signals (Figures 5F, 5G). The slight saw-toothed appearance of the wavefoims in Figures 5B to 5G exists because the demodulated signals consist of alternate sections of live data and the average of the previous live data. We also see that the DC offset has been removed by the subtraction process.
The logic functions and components of the demodulators 212, 214 are shown in Figures 6 and 7. Figure 6 shows that for each demodulator 212, 214 the incoming (amplified, filtered and digitised) signal from SQUID 102 is split into two paths that flow through identical sample memories 612, 614, the outputs of which are subtracted from each other to generate a demodulator signal output. Figure 7 illustrates example internal logic of the sample memory block.
For each sample memory 612, 614, the sample memory logic is controlled by the Phase_In signal, which corresponds to either the Phase_A or Phase_B
synchronisation signal from the modulator 140, and triggers a counter 710 which is in turn compared by comparators 722 and 724 to two configurable thresholds 712, 714 that determine the period over which the signal is averaged. The output of comparator 722 also directs an output multiplexer 740 to pass either the live input signal (Data_In) or the output of an averaging section 730. The averaging section 730 is based on an accumulator 735 that runs for the period set by the counter 710 and then has its output scaled down by a constant to provide the correct averaged value to the output multiplexer 740.
The demodulation method outlined above is specific to the particular modulation waveform used in this implementation. If an alternate modulation waveform is used, the demodulator section would need to be designed to extract the in-phase and quadrature components appropriately. For example, if a sinusoidal modulation waveform were used to sweep the SQUID response over 180 , the demodulator would need to re-map the SQUID signal into in-phase and quadrature components.
The phase detector module 220 is illustrated in further detail in Figure 10 and performs the first stage of the SQUID signal linearization process. The phase un-wrapping module 230 that follows the phase detector 220 completes the process. The phase detector 220 performs a co-ordinate transform from Cartesian to Polar co-ordinates and in so doing provides a linear measurement of the SQUID signal over the range of one complete flux quanta.
The demodulated in-phase and quadrature components of the SQUID signal can be viewed as representing the Cartesian co-ordinates of the SQUID' s output at any instant in time, as illustrated in Figures 8A and 8B. As the flux threading through the SQUID
changes, the SQUID' s demodulated output follows a circular path on a Cartesian plain and completes one cycle in exactly one flux quanta, as illustrated by Figure 8C. A
Cartesian to Polar transformation, as illustrated by Figures 8C and 8D allows the SQUID signal to be condensed into a linear representation of flux because the SQUID
transfer function is circular and it is only necessary to calculate the angle of the point on the circle at which the SQUID output is currently placed. The radius and origin of the circle are not necessary for the linearization process and may be ignored.
The plots in Figures 9A, 9B show the demodulated SQUID in-phase and quadrature signals that are input to the phase detector module 220 as the flux threading through the SQUID increases and Figure 9C shows the corresponding detected phase output of the phase detector module 220. From the SQUID phase plot in Figure 9C, it can be seen that the SQUID signal is now substantially linear over the range of one full cycle (or flux quantum) of the SQUID transfer function.
Figure 10 shows the logical implementation of the phase detector module 220 to the level of the Xilinx CORDIC function IP block. The CORDIC (Co-Ordinate Rotation Digital Computer) IP block implements a Cartesian to Polar transform by rotating the input co-ordinates until the quadrature component becomes zero and noting the angle through which the co-ordinates where rotated. The block implements the conversion function using an optimised hardware pipeline that has been designed by Xilinx to suit their FPGAs. The inputs to the CORDIC block are scaled by 1/2 to reduce the block's FPGA resource requirements. If other FPGAs or DSPs are used to implement the functions described herein, another phase detection module may be more appropriate than the Xilinx IP CORDIC.
In the described implementation, the phase detector's Cartesian to Polar conversion is based on a CORDIC translation function. However, the conversion process could as easily be based on other techniques, such as a two input look-up table, or use simple trigonometric mathematics. If a smooth modulation waveform is used instead of the stepped one in the described implementation, it may be possible to extract the phase of the SQUID signal directly, without the need for the Cartesian to Polar conversion.
Figure 12 shows an example logical implementation of the phase unwrapping module 230. The phase unwrapping module 230 takes the Phase_In output from the phase detector module 220 and completes the SQUID signal linearization process. The phase unwrapping module 230 detects the step (179.99 to -179.99'or vice versa) in the phase signal from the phase detector module 220 and adds or subtracts multiples of 180 as needed to remove the step. The phase unwrapping module 230 accumulates the correction steps, allowing it to track the phase signal over many cycles. In Figures 11A, 11B and 11C, the output of the phase detector module 220 is shown in the first plot (Figure 11A), the accumulated phase steps are shown in the second plot (Figure 11B) and the output of the phase un-wrapping module 230 is shown in the final plot (Figure 11C).
At each instant in time, the value of the incoming phase signal (Phase_In) is first subtracted from its previous value by subtractor 712 and is then compared to two configurable constant thresholds 714, 716 by respective comparators 724, 726.
The thresholds 714, 716 represent 90 phase shifts and outputs of comparators 724, 726 direct a multiplexer 730 to present the equivalent of either +180 or ¨ 180 to an accumulator 740. Whenever the difference exceeds 90 , the accumulator 740 then either increases or decreases its value by the equivalent of 180 . If the difference is less than 90 , the accumulator 740 is presented with 0 and so does not change value. The output of the accumulator 740 is added to the phase signal and emerges from the phase unwrapping module 230 as the linearized SQUID phase signal.
The signal plots in Figures 13A and 13B illustrate the net effect of the whole SQUID
signal linearization process. Without linearization (Figure 13A) the output of the SQUID is periodic and useful for feedback only over the range of 1/4 of a flux quantum (00). After the modulation, demodulation, phase detection and un-wrapping process, the SQUID signal becomes substantially linear and useful for feedback over tens or hundreds of flux quanta.
Referring also to Figure 14, a method 1400 of SQUID signal processing is described with reference to the components, steps and techniques described above. Method is performed continuously during operation of sensor system 100, so while it can be said that the method 1400 "starts" at step 1410, this is only a convenient way to express one step in the continuous process. The method 1400 could equally be said to start at 1420, 1430 or 1490.
At 1410, modulator 140 generates a quadrature modulation signal. At 1420, this quadrature modulation signal is applied to modulate the feedback signal provided to the SQUID 102 by the integrator 152 (via feedback coil driver 154 and feedback coil 192) as part of the FLL arrangement. At 1430, the SQUID signal, including any influence from the external magnetic field 202, is filtered, amplified and digitised by low noise amplifier 108 and ADC 112. This conditioned signal is then fed into demodulators 212, 214, where it is demodulated into in-phase and quadrature signal components at 1440.
The in-phase and quadrature signal components are used by phase detector 220 to detect the phase at 1450 and then the detected phase is used by the phase unwrapping module 230 to unwrap the phase angle at 1460. The unwrapped phase angle is then provided to the integrator 152 (via DAC 126) at 1470. The output of the integrator 152 is then used as measurement output 170 of the sensor system 100 at 1480 while the integrator output is simultaneously fed back to the SQUID 102 at 1490. The feedback signal delivered to the SQUID 102 has the quadrature modulation signal coupled (at 1420) to the integrator output, returning the signal processing method 1400 to the "start" described above.
Experiment In order to test the viability of the described new SQUID flux modulation architecture, the performance of a model of the new arrangement was compared to that of a model of a common FLL system.

As a baseline for comparison, an existing single integrator design was modeled as a simple flux locked loop with a bipolar flux modulation scheme. A loop delay of 1 las was added to encapsulate the analogue signal processing delays in the existing design, such as the preamplifier and band-pass filter group delays. The model also incorporates 5 1/f and flat noise sources representing the noise generated by a high temperature SQUID and low noise preamplifier. The level of the noise source was set at the equivalent of 10 11)0/A/Hz with a 1/f corner frequency of 1 kHz. To enable performance measurement, a sinusoidal signal source was added to simulate the magnetic source and an oscilloscope like signal capturing component was used to enable analysis of internal 10 signals. A reset circuit was been added to the integrator to enable initial conditions to be set prior to taking measurements.
To ensure the accuracy of the model, an input band pass filter as well as a low pass filter after the demodulator were added and the poles placed to accurately represent the 15 existing system. It should be noted that despite these enhancements, this comparison model is still quite simplistic and does not include many of the nonlinearities that will be present in the physical system. It is quite likely that this comparison model will slightly overestimate the slew rate achievable by a system of this type. The data was captured while the SQUID system was slewing at its maximum rate The maximum 20 slew rate achievable by this model is 97k 00/s. Comparison of this result with values obtained from a commercial single integrator system operating with a CSIRO
high Tc step edge 3mm SQUID lead us to believe that this model represents a reasonable baseline with which to compare the described invention.
The simulation model of described embodiments uses the same SQUID and amplifier chain with band limiting filter as the single integrator flux locked loop model, so that a direct comparison of the system noise performance and slew rate are possible.
The bipolar modulation generator of the single integrator system has been replaced with a quadrature modulation generator and the modulated signal from the SQUID is split and sent to 2 separate demodulators. The demodulated signals are low-pass filtered with the same cut-off as the single integrator system. The phase angle component is then calculated and unwrapped then fed to an integrator to produce the feedback signal.
The maximum slew rate of the new system is no longer limited by the SQUID
transfer function but instead by the maximum dynamic range of the integrator input signal and the sampling rate of the modulation / demodulation section. The dynamic range of the integrator signal is limited in a physical system by the electronics and the sampling rate is limited by the bandwidth of the SQUID signal path. As in the single integrator system, the modulation signal fundamental frequency was set at 500 kHz.
The maximum slew rate of the quadrature modulation system model was determined by increasing the amplitude of the external flux signal until the FLL lost lock then reducing the amplitude slightly to make the measurements. The maximum slew rate attained was 3.5M (1)0/s, which is more than 36 times faster than that of the modelled simple single integrator system. The spectral density of the model's output noise was compared between the two systems and found to be very similar. The modelled quadrature modulation system produces a slight increase in noise at frequencies beyond the system modulation frequency. The increase in noise is unlikely to be a problem in practice as a low-pass filter is normally used to suppress the residual modulation signal and prevent aliasing in data acquisition systems.
The performance of the sensor system according to described embodiments was tested using a purpose built hardware platform. The platform consisted of a low noise preamplifier connected to a 14 bit, high speed analogue to digital converter which in turn is connected to a Field Programmable Gate Array (FPGA). The FPGA performs most of the signal processing duties and then passes a control signal via a digital to analogue converter to an analogue integrator. The integrator signal then drives current into a feedback coil around the SQUID closing the loop. It is the analogue integrator that provides the large dynamic range of the FLL.
To confirm the validity of the single integrator model, a CSIRO high Tc 3 mm step edge SQUID was connected to a commercial DC SQUID electronics system and the maximum achievable slew rate was determined using a sinusoidal stimulus field.
The commercial system produced a maximum slew rate of 2.70 mT/s or, expressed in terms of (Do, 91.2 k(DO/s, which compares well with the value predicted by the model.
The quadrature modulation system was then connected to the same SQUID and again using a sinusoidal field wavefolin the new system achieved a maximum slew rate of 194 mT/s or, expressed in terms of (Do, 6.54 M(Do/s which is 86% higher than the system modelling suggested. Fig. 6 shows the new system's response to an external signal with a maximum slew rate of 3.47 M 0/s.
The new system was then connected to a CSIRO high Tc 8 mm step edge SQUID and the maximum measured slew rate equalled 70 mT/s or in teinis of flux quanta 8.63 M 0/s. It is believed that the increased slew rate over the modelled value is due to the actual SQUID noise level being lower than that used in the model.
The noise performance of the quadrature modulation system was measured with the CSIRO 8mm SQUID connected and placed inside several layers of Mu-metal screening. The system noise floor was found to reach a minimum of 70 fT/AiHz with a 1/f noise corner frequency of approximately 2 kHz. There was also found to be a considerable amount of 50 Hz interference present during the measurement, despite the use of the Mu-metal shields. The measurement setup did not include battery power for the high slew rate electronics.
A new SQUID modulation and demodulation scheme has been developed that dramatically increases the available slew rate of integrator based FLLs without sacrificing noise performance. Further the results of measurements of a purpose built hardware platform have exceeded those predicted by the system model and validated the approach.

Numerous variations and/or modifications may be made to the described embodiments without departing from the scope of the invention as broadly described. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive.
Any discussion of documents, acts, materials, devices, articles or the like which has been included in the present specification is not to be taken as an admission that any or all of these matters foul' part of the prior art base or were common general knowledge in the field relevant to the present disclosure as it existed before the priority date of each claim of this application.
Throughout this specification the word "comprise", or variations such as "comprises" or "comprising", will be understood to imply the inclusion of a stated element, integer or step, or group of elements, integers or steps, but not the exclusion of any other element, integer or step, or group of elements, integers or steps.

Claims (20)

CLAIMS:

1. Signal processing circuitry for a super-conducting quantum interference device (SQUID), the circuitry comprising:
a signal processing module coupled to receive a SQUID output signal, the signal processing module comprising a modulator and a phase tracking component;
an integrator coupled to an output of the signal processing module to integrate a signal processing module output;
a feedback circuit coupled to an output of the integrator and arranged to provide a feedback signal to the SQUID in a flux locked loop (FLL) arrangement, the feedback signal including an integrator output signal from the integrator, wherein the integrator output signal is modulated by a quadrature modulation signal from the modulator;
wherein the phase tracking module is configured to demodulate and unwrap a phase angle of the output of the SQUID and provide the unwrapped phase angle to the integrator.

2. The circuitry of claim 1, wherein the signal processing module is implemented in a field-programmable gate array (FPGA).

3. The circuitry of claim 1 or claim 2, further comprising an analogue-to-digital converter (ADC) to receive an output signal of the SQUID and convert the output signal to a digitised SQUID signal.

4. The circuitry of any one of claims 1 to 3, further comprising a digital-to-analogue converter (DAC) coupled to an output of the signal processing module to provide the unwrapped phase angle to the integrator.

5. The circuitry of any one of claims 1 to 4, wherein the phase tracking module comprises a pair of demodulators to demodulate the SQUID output signal and output in-phase and quadrature signal components of the SQUID output signal, the demodulators receiving synchronisation signals from the modulator to enable demodulation of the SQUID output signal.

6. The circuitry of claim 5, wherein the phase tracking module further comprises a phase detection module to receive the in-phase and quadrature signal components and determine a phase of the SQUID output signal based on the in-phase and quadrature signal components and to output a phase signal.

7. The circuitry of claim 6, further comprising a phase unwrapping module to receive the phase signal and to unwrap the phase of the SQUID output signal based on the received phase signal.

8. The circuitry of any one of claims 1 to 7, wherein the circuitry has a digital circuitry section and an analogue circuitry section, wherein the analogue circuitry section is arranged to have a differential signalling architecture to minimise the effect of signal crosstalk in the analogue section.

9. The circuitry of claim 8, wherein the signal processing module is part of the digital circuitry section and the integrator and the feedback circuit are part of the analogue circuitry section.

10. A housing comprising the circuitry of any one of claims 1 to 9, the housing further comprising signal isolation structure to isolate the SQUID, the integrator and the feedback circuit from radio-frequency interference generated by the signal processing module.

11. A signal processing method for a SQUID in a flux locked loop arrangement, the method comprising:
converting an amplified analogue output signal of the SQUID to a digital signal, wherein the analogue output of the SQUID comprises a quadrature modulation signal component;
processing the digital signal to demodulate and unwrap a phase angle of the SQUID output signal;
integrating the unwrapped phase angle to generate a feedback signal to the SQUID;
modulating the feedback signal with a quadrature modulation signal.

12. The method of claim 11, further comprising converting the unwrapped phase angle to an analogue signal version, wherein the integrating uses the analogue signal version of the unwrapped phase angle.

13. The method of claim 12, wherein the quadrature modulation signal varies cyclically in four steps.

14. The method of any one of claims 11 to 13, wherein the processing comprises demodulating the SQUID output signal into in-phase and quadrature signal components, determining the phase of the SQUID output signal based on the in-phase and quadrature signal components and generating the unwrapped phase angle based on the detected phase.

15. The method of claim 14, wherein the detecting comprises performing a Cartesian-to-polar signal conversion of the in-phase and quadrature signal components to determine the phase.

16. A sensor system, comprising:
a superconducting quantum interference device (SQUID);
signal processing circuitry coupled to receive an output of the SQUID;
an integrator arranged to receive an output of the signal processing circuitry; and a feedback section coupled to an output of the integrator and the SQUID in a flux locked loop (FFL) arrangement;
wherein the signal processing circuitry is arranged to modulate the output of the integrator with a quadrature modulation signal so that the output of the SQUID
includes the quadrature modulation signal as one signal component of the SQUID output;
and wherein the signal processing circuitry is further arranged to demodulate the SQUID output, to unwrap a phase angle of the output of the SQUID and to provide the unwrapped phase angle to the integrator.

17. The system of claim 16, wherein the signal processing circuitry is implemented in digital circuitry and the integrator and the feedback section are implemented in analogue circuitry.

18. The sensor system of claim 16 or claim 17, wherein the signal processing circuitry is arranged to generate a phase-shifted version of the SQUID output to map the SQUID output and the phase-shifted version to polar coordinates and to unwrap the phase angle based on the polar coordinates.

19. The sensor system of any one of claims 16 to 18, wherein the output of the integrator is provided as an output of the sensor system.

20. The sensor system of any one of claims 16 to 19, wherein the signal processing circuitry comprises a field-programmable gate array (FPGA) configured to comprise a modulation generator to generate the modulation signal and a phase unwrapping component to unwrap the phase angle.