CN115249684A - 芯片封装结构 - Google Patents
芯片封装结构 Download PDFInfo
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- CN115249684A CN115249684A CN202210579588.5A CN202210579588A CN115249684A CN 115249684 A CN115249684 A CN 115249684A CN 202210579588 A CN202210579588 A CN 202210579588A CN 115249684 A CN115249684 A CN 115249684A
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- 238000004806 packaging method and process Methods 0.000 title description 6
- 239000000463 material Substances 0.000 claims abstract description 188
- 150000001875 compounds Chemical class 0.000 claims abstract description 72
- 239000004065 semiconductor Substances 0.000 claims abstract description 68
- 238000000465 moulding Methods 0.000 claims abstract description 55
- 238000005520 cutting process Methods 0.000 abstract description 58
- 229910000679 solder Inorganic materials 0.000 abstract description 50
- 239000000758 substrate Substances 0.000 description 93
- 229910052751 metal Inorganic materials 0.000 description 59
- 239000002184 metal Substances 0.000 description 59
- 239000010410 layer Substances 0.000 description 53
- 238000000034 method Methods 0.000 description 29
- 239000012790 adhesive layer Substances 0.000 description 24
- 239000004593 Epoxy Substances 0.000 description 22
- 229920006336 epoxy molding compound Polymers 0.000 description 21
- 239000011159 matrix material Substances 0.000 description 15
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 13
- 229910052802 copper Inorganic materials 0.000 description 13
- 239000010949 copper Substances 0.000 description 13
- 238000006243 chemical reaction Methods 0.000 description 11
- 230000008569 process Effects 0.000 description 10
- 238000003801 milling Methods 0.000 description 9
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 8
- 230000002093 peripheral effect Effects 0.000 description 8
- 239000011800 void material Substances 0.000 description 7
- 239000000853 adhesive Substances 0.000 description 6
- 230000001070 adhesive effect Effects 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 6
- 239000007769 metal material Substances 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 230000035882 stress Effects 0.000 description 6
- 239000000945 filler Substances 0.000 description 5
- 238000000137 annealing Methods 0.000 description 4
- 230000001678 irradiating effect Effects 0.000 description 4
- 229910052759 nickel Inorganic materials 0.000 description 4
- 239000002344 surface layer Substances 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 239000012778 molding material Substances 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 230000000737 periodic effect Effects 0.000 description 3
- 238000007493 shaping process Methods 0.000 description 3
- 239000007787 solid Substances 0.000 description 3
- 230000003068 static effect Effects 0.000 description 3
- 230000008646 thermal stress Effects 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 239000000654 additive Substances 0.000 description 2
- 238000003491 array Methods 0.000 description 2
- 238000004380 ashing Methods 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 230000000977 initiatory effect Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000005272 metallurgy Methods 0.000 description 2
- 229920002577 polybenzoxazole Polymers 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000002861 polymer material Substances 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 230000000087 stabilizing effect Effects 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 239000012780 transparent material Substances 0.000 description 2
- 239000004820 Pressure-sensitive adhesive Substances 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- NIXOWILDQLNWCW-UHFFFAOYSA-N acrylic acid group Chemical group C(C=C)(=O)O NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000004848 polyfunctional curative Substances 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H—ELECTRICITY
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/293—Organic, e.g. plastic
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- H01L23/00—Details of semiconductor or other solid state devices
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
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- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
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- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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Abstract
一种芯片封装结构,包括附接到重分布结构的至少一个半导体裸片、位于重分布结构和至少一个半导体裸片之间且横向围绕焊料材料部分的第一底部填充材料部分、横向围绕至少一个半导体裸片的成型化合物,以及接触重分布结构的侧壁和成型化合物的侧壁且包括至少一切割区域的第二底部填充材料部分。第二底部填充材料部分包括具有均匀横向宽度的垂直延伸段部和具有均匀垂直厚度且在至少一个切割区域的每一者内邻接于垂直延伸段部的底端的横向延伸段部。
Description
技术领域
本公开涉及一种芯片封装结构,尤其涉及一种底部填充材料具有切割区域的芯片封装结构。
背景技术
扇出晶片级封装体(fan-out wafer level package;FOWLP)和成型化合物材料部分之间的界面在后续处理扇出晶片级封装体、底部填充材料部分和封装基底的组装(例如将封装基底附接到印刷电路板(printed circuit board;PCB))期间会承受机械应力。此外,扇出晶片级封装体(FOWLP)和底部填充材料部分之间的界面在计算装置内的使用期间会受到机械应力,例如当扇出晶片级封装体在使用期间变热且扇出晶片级封装体的元件的热膨胀不匹配时会产生热应力,或者当移动装置在使用期间意外掉落时会产生机械冲击。裂纹可能形成在底部填充材料中,且可能在半导体裸片、焊料材料部分、重分布结构及/或半导体裸片内或封装基底内的各种介电层中产生额外的裂纹。因此,需要抑制底部填充材料中裂纹的形成。
发明内容
本公开实施例提供一种芯片封装结构,包括:至少一个半导体裸片,通过焊料材料部分附接到重分布结构;第一底部填充材料部分,位于重分布结构和至少一个半导体裸片之间并横向围绕至少一个半导体裸片的一部分;成型化合物裸片框架横向围绕至少一个半导体裸片;以及第二底部填充材料部分接触重分布结构的侧壁和成型化合物裸片框架的侧壁,且可包括至少一个切割区域,其中第二底部填充材料部分可包括具有均匀横向宽度的垂直延伸段部,以及具有均匀垂直厚度且在至少一个切割区域中的每一者内邻接垂直延伸段部的底端的横向延伸段部。
本公开实施例提供一种芯片封装结构,包括:至少一个半导体裸片,附接到重分布结构;第一底部填充材料部分横向围绕至少一个半导体裸片的一部分;成型化合物裸片框架横向围绕至少一个半导体裸片;封装基底附接至重分布结构;以及第二底部填充材料部分,其包括:横向围绕重分布结构且在平面图中位于成型化合物的外周缘内的基底间底部填充部分,以及在平面图中位于成型化合物的外周缘之外且包括具有L形垂直截面形状的至少一个切割区域的外围底部填充部分,其中至少一个切割区域中的每一者包含具有均匀横向宽度的垂直延伸段部和横向延伸段部。
本公开实施例提供一种芯片封装结构的制造方法,其可包括:提供重分布结构;将至少一个半导体裸片附接到重分布结构;在重分布结构和至少一个半导体裸片之间形成第一底部填充材料部分;将封装基板附接到重分布结构;在重分布结构与封装基板之间并围绕重分布结构形成第二底部填充材料部分;以及通过切割第二底部填充材料部分的部分,在第二底部填充材料部分中形成至少一个切割区域。
附图说明
根据以下的详细说明并配合所附附图以更好地了解本公开实施例的概念。应注意的是,根据本产业的标准惯例,附图中的各种特征未必按照比例绘制。事实上,可能任意地放大或缩小各种特征的尺寸,以做清楚的说明。在通篇说明书及附图中以相似的标号标示相似的特征。
图1A是根据本公开实施例的包括第一载体基底和重分布结构的范例性结构的区域的垂直剖视图。
图1B是图1A的范例性结构的俯视图。
图2A是根据本公开实施例的在形成重分布侧金属垫结构和第一焊料材料部分之后的范例性结构的区域的垂直剖视图。
图2B是图2A的范例性结构的区域的俯视图。
图3A是根据本公开实施例的在附接半导体裸片之后的范例性结构的区域的垂直剖视图。
图3B是图3A的范例性结构的区域的俯视图。
图3C是高频宽存储器裸片的放大垂直剖视图。
图4是在形成第一底部填充材料部分之后的范例性结构的区域的垂直剖视图。
图5A是根据本公开实施例的在形成环氧成型化合物(epoxy molding compound;EMC)基质之后的范例性结构的区域的垂直剖视图。
图5B是图5A的范例性结构的区域的俯视图。
图6是根据本公开实施例的在附接第二载体基底和分离第一载体基底之后的范例性结构的区域的垂直剖视图。
图7是根据本公开实施例的形成扇出接合垫之后的范例性结构的区域的垂直剖视图。
图8是根据本公开实施例的在分离第二载体基底之后的范例性结构的区域的垂直剖视图。
图9是根据本公开的实施例的在切割重分布基底和环氧成型化合物基质期间范例性结构的区域的垂直剖视图。
图10A是根据本公开实施例的扇出封装体的垂直剖视图。
图10B是扇出封装体沿图10A的水平面B-B'的水平剖视图。
图11是根据本公开实施例的在将扇出封装体附接到封装基底之后的范例性结构的垂直剖视图。
图12A是根据本公开实施例的在形成第二底部填充材料部分之后的范例性结构的垂直剖视图。
图12B是图12A的范例性结构的俯视图。垂直平面A-A'是图12A的垂直剖视图的平面。
图13A是根据本公开实施例的在使用激光照射形成切割区域期间的范例性结构的垂直剖视图。
图13B是在使用根据本公开的实施例的铣削设备形成切割区域期间的范例性结构的垂直剖视图。
图13C是根据本公开实施例的在图13A或图13B的范例性结构形成切割区域之后的俯视图。
图14A是根据本公开实施例的范例性结构在形成切割区域之后的第一替代实施例的俯视图。
图14B是根据本公开实施例的范例性结构在形成切割区域之后的第二替代实施例的俯视图。
图15是根据本公开实施例的在将重分布结构附接到封装基底之后的范例性结构的垂直剖视图。
图16是根据本公开实施例的在将封装基底附接到印刷电路板(PCB)之后的范例性结构的垂直剖视图。
图17是根据本公开实施例的示出用于形成范例性结构的步骤的流程图。
附图标记如下:
100:印刷电路板
110:印刷电路板基底
180:印刷电路板接合垫
190:焊点
192:底部填充材料部分
200:封装基底
210:芯基底
212:介电衬垫
214:穿芯通孔结构
240:板侧表面层状电路
242:板侧绝缘层
244:板侧内连线
248:板侧接合垫
260:芯片侧表面层状电路
262:芯片侧绝缘层
264:芯片侧内连线
268:芯片侧垫
290:第二焊料材料部分
292:第二底部填充材料部分
294:稳定结构
300:第一载体基底
301:第一粘着层
400:第二载体基底
401:第二粘着层
600:激光装置
610:激光束
620:铣削设备
700:半导体裸片(芯片上系统裸片)
780:芯片上系统金属垫结构
800:半导体裸片(存储器裸片)
810:高频宽存储器裸片
811,812,813,814,815:随机存取存储器裸片对
816:环氧成型材料外框
820:微凸块
822:高频宽存储器底部填充材料部分
880:存储器裸片金属垫结构
900:扇出封装体
900W:重组晶片
910:成型化合物裸片框架
910M:环氧成型化合物基质
920:重分布结构
922:重分布介电层
924:重分布内连线
928:扇出接合垫
938:重分布侧金属垫结构
940:第一焊料材料部分
950:第一底部填充材料部分
1710,1720,1730,1740,1750,1760:步骤
A-A’:垂直平面
B-B’:水平面
CR:切割区域
hd1:第一水平方向
hd2:第二水平方向
L1:第一长度
L2:第二长度
S1:第一间距
S2:第二间距
TR:锥形区域
UA:单位区域
Vd1:第一垂直距离
Vd2:第二垂直距离
W1:第一宽度
W2:第二宽度
具体实施方式
以下的公开内容提供许多不同的实施例或范例以实施本公开实施例的不同特征。在本公开所述的各种范例中可重复使用参考标号及/或字母。这些重复是为了简洁及清楚的目的,本身并不表示所公开的各种实施例及/或配置之间有任何关系。此外,以下叙述构件及配置的特定范例,以简化本公开实施例的说明。当然,这些特定的范例仅为示范并非用以限定本公开实施例。举例而言,在以下的叙述中提及第一特征形成于第二特征上或上方,即表示其可包括第一特征与第二特征是直接接触的实施例,亦可包括有附加特征形成于第一特征与第二特征之间,而使第一特征与第二特征可能未直接接触的实施例。此外,本公开可以在各种范例中重复标号及/或字母。这种重复是为了简单和清楚的目的,且其本身并不限定所述的各种实施例及/或配置之间的关系。
此外,在此可使用与空间相关用词。例如“底下”、“下方”、“较低的”、“上方”、“较高的”及类似的用词,以便于描述附图中示出的一个元件或特征与另一个(些)元件或特征之间的关系。除了在附图中示出的方位外,这些空间相关用词意欲包括使用中或操作中的装置的不同方位。装置可能被转向不同方位(旋转90度或其他方位),且在此使用的空间相关词也可依此做同样的解释。除非另有明确说明,否则假定具有相同标号的每个元件具有相同的材料组成且具有相同厚度范围内的厚度。
本公开针对半导体装置,特别是用于半导体裸片封装中的底部填充剂裂纹抑制的裸片角移除。一般而言,本公开的方法和结构可用于提供芯片封装结构,例如扇出晶片级封装体(FOWLP)和扇出面板级封装体(fan-out panel level package;FOPLP)。虽然使用扇出晶片级封装体配置来说明本公开,但是本公开的方法和结构可以在扇出面板级封装体配置或任何其他扇出封装配置中实现。各种实施例的芯片封装结构可以具有加强对于横向围绕扇出封装体的底部填充材料部分中产生裂纹的抵抗力。
一般而言,异质整合用于整合大型中介层(例如基底上晶片上芯片(Chip-on-Wafer-on-Substrate;CoWoS)中介层或有机中介层)和高电性能基底(如多层芯或多层基底(其可包括12层或更多层),以用于高性能芯片。这种结构的有效热膨胀系数可能是硅的热膨胀系数的四倍以上。基底和中介层上的半导体裸片之间的热膨胀系数如此大的不匹配导致扇出模块角落处形成成型裂纹。因此,成型的大型扇出模块在角落处形成裂纹的风险很高。
根据本公开的一方面,可通过执行切角工艺从底部填充材料部分的外围区域移除底部填充材料的至少一个圆角。切角可以减少底部填充材料部分和至少一个半导体裸片所附接的基底(例如重分布结构)之间的机械耦合。可通过在例如晶片上芯片(Chip-on-Wafer;CoW)配置的各种芯片封装配置中形成切角来降低成型应力。因此,本公开的实施例扇出封装体可在热应力下更能抵抗裂纹产生及/或裂纹扩张。现在参照附图说明本公开的方法和结构的各个方面和实施例。各种公开的实施例提供了一种结构,可提高可靠性且减少成型上的应力,亦提高整体封装体的可靠性。现在参照附图说明本公开的方法和结构的各个方面和实施例。
参照图1A和图1B,根据本公开实施例的范例性结构包括第一载体基底300和形成在第一载体基底300的正面上的重分布结构920。第一载体基底300可以包括光学透明基底,例如为玻璃基底或蓝宝石基底。第一载体基底300的直径可介于约150mm到约290mm的范围内,但是亦可以使用更小和更大的直径。此外,第一载体基底300的厚度可介于约500微米到约2,000微米的范围内,但也可以使用更小和更大的厚度。或者,第一载体基底300可用矩形面板的形式来提供。
可以将第一粘着层301施加到第一载体基底300的正面。在一实施例中,第一粘着层301可以是光热转换(light-to-heat conversion;LTHC)层。光热转换层可以是使用旋涂法施加的基于溶剂的涂层。光热转换层可以将紫外光转化为热量,这可能导致光热转换层的材料失去粘着性。举例而言,光热转换层可以包括能从The 3M 购买取得的光热转换释放涂层(Light-To-Heat Conversion Release Coating;LTHC)inkTM。或者,第一粘着层301可以包括热分解粘着材料。举例而言,第一粘着层301可以包括会在升高的温度下分解的丙烯酸压敏粘着剂。热分解粘着剂材料的分解温度可介于约150摄氏度到约200摄氏度的范围内。
重分布结构920可以形成在第一粘着层301上方。更具体而言,重分布结构920可以形成在每个单位区域UA内,此单位区域UA是在第一粘着层301上以二维阵列重复的重复单元的区域。每个重分布结构920可以包括重分布介电层922和重分布内连线924。重分布介电层922包括相应的介电聚合物材料,例如聚酰亚胺(polyimide;PI)、苯并环丁烯(benzocyclobutene;BCB)或聚苯并恶唑(polybenzobisoxazole;PBO)。其他适合的材料亦可在本公开的考虑范围内。每个重分布介电层922可以通过各自介电聚合物材料的旋涂和干燥来形成。每个重分布介电层922的厚度可介于约2微米到约40微米的范围内,例如约4微米到约20微米。每个重分布介电层922可被图案化,例如通过在其上方施加和图案化相应的光刻胶层,以及通过使用例如各向异性蚀刻工艺的蚀刻工艺将光刻胶层中的图案转移到重分布介电层922中。随后可以例如通过灰化来移除光刻胶层。
每个重分布内连线924可以通过以下方式形成:溅射沉积金属种子层,在金属种子层上施加且图案化光刻胶层以形成穿过光刻胶层的开口图案,电镀金属填充物材料(例如铜、镍或铜和镍的叠层),移除光刻胶层(例如通过灰化),以及蚀刻位于电镀金属填充材料部分之间的金属种子层的部分。金属种子层可以包括例如钛阻挡层和铜种子层的叠层。钛阻挡层的厚度可介于约50nm到约400nm的范围内,铜种子层的厚度可介于约100nm到约500nm的范围内。用于重分布内连线924的金属填充材料可以包括铜、镍或铜和镍两者。其他适合的金属填充材料亦在本公开的考虑范围内。为每个重分布内连线924沉积的金属填充材料的厚度可介于约2微米到约40微米的范围内,例如约4微米到约10微米,但也可以使用更小或更大的厚度。每个重分布结构920中布线的总层数(即重分布内连线924的层数)可介于1到10的范围内。重分布结构920的周期性二维阵列(例如矩形阵列)可以形成在第一载体基底300上方。每个重分布结构920可以形成在单位面积UA内,单位面积UA是重分布结构920的二维阵列的重复单位。包括所有重分布结构920的层在此被称为重分布结构层。重分布结构层包括重分布结构920的二维阵列。在一个实施例中,重分布结构920的二维阵列可以是具有矩形周期性的重分布结构920的二维阵列,其具有沿第一水平方向hd1的第一周期性以及沿垂直于第一水平方向hd1的第二水平方向hd2具有第二周期性。在一些实施例中,重分布内连线924可以包括交替堆叠的布线部分和通孔结构。
参照图2A和图2B,至少一种金属材料和第一材料可依序沉积在重分布结构920的正面上。至少一种金属材料包括可以用于金属垫的材料,例如铜。至少一种金属材料的厚度可介于约5微米到约60微米的范围内,例如介于约10微米到约30微米,但是也可以使用更小和更大的厚度。第一材料可包括适合于C2接合(即用于微凸块接合)的第一材料。第一材料的厚度可介于约2微米到约30微米的范围内,例如介于约4微米到约15微米,但也可以使用更小和更大的厚度。
第一材料和至少一种金属材料可以被图案化为第一焊料材料部分940的离散阵列和金属垫结构的阵列,其在本公开中被称为重分布侧金属垫结构938的阵列。重分布侧金属垫结构938的每个阵列形成在相应的单位区域UA内。每个第一焊料材料部分940的阵列形成在相应的单位区域UA内。每个第一焊料材料部分940可以具有与下方的重分布侧金属垫结构938相同的水平截面形状。
在一实施例中,重分布侧金属垫结构938可包括及/或可基本上由铜或含铜合金组成。其他适合的材料亦在本公开的考虑范围内。重分布侧金属垫结构938的厚度可介于约5微米到约60微米的范围内,但是也可以使用更小或更大的厚度。重分布侧金属垫结构938可具有矩形、圆角矩形、圆形、正多边形、不规则多边形或任何其他具有封闭周缘的二维曲线形状的水平截面形状。在一实施例中,重分布侧金属垫结构938可被配置用于微凸块接合(即C2接合),且可具有介于约10微米到约30微米范围内的厚度,但也可以使用更小或更大的厚度。在此实施例中,重分布侧金属垫结构938的每个阵列,例如铜柱或凸块下金属层(under bump metallurgies;UBM),可以是横向尺寸介于约10微米到约25微米范围内的微凸块阵列的部分,且其间距介于约20微米到约50微米之间。
参照图3A和图3B,可将一组至少一个半导体裸片(700、800)结合到每个重分布结构920。在一个实施例中,重分布结构920可配置为二维周期性阵列,且可将多组至少一个半导体裸片(700、800)结合到重分布结构920,以作为至少一个半导体裸片(700、800)的多组的二维周期性矩形阵列。每组至少一个半导体裸片(700、800)包括至少一个半导体裸片。每组至少一个半导体裸片(700、800)可以包括本技术领域已知的任何组的至少一个半导体裸片。在一个实施例中,每组至少一个半导体裸片(700、800)可以包括多个半导体裸片(700、800)。举例而言,每组至少一个半导体裸片(700、800)可以包括至少一个芯片上系统(system-on-chip;SoC)裸片700及/或至少一个存储器裸片800。每个芯片上系统裸片700可以包括应用处理器裸片、中央处理单元裸片或图形处理单元裸片。在一实施例中,至少一个存储器裸片800可包括高频宽存储器(high bandwidth memory;HBM)裸片,其包括静态随机存取存储器裸片的垂直堆叠。在一实施例中,至少一个半导体裸片(700、800)可以包括至少一个芯片上系统(SoC)裸片和包括通过微凸块相互连接且由环氧成型材料外框横向地包围的静态随机存取存储器(static random access memory;SRAM)裸片的垂直堆叠的高频宽存储器(HBM)裸片。
参照图3A和图3C,每个半导体裸片(700、800)可以包括裸片侧金属垫结构(780、880)的相应阵列。举例而言,每个芯片上系统裸片700可包括芯片上系统金属垫结构780的阵列,且每个存储器裸片800可以包括存储器裸片金属垫结构880的阵列。每个半导体裸片(700、800)可以定位在面朝下的位置使得裸片侧金属垫结构(780、880)面对第一焊料材料部分940。每组至少一个半导体裸片(700、800)可以放置在相应的单位区域UA内。半导体裸片(700、800)的放置可以使用拾取和放置设备来执行,使得裸片侧金属垫结构(780、880)中的每一者都被放置在第一焊料材料部分940中的相应一者的顶面上。
一般而言,可提供包括上方的重分布侧金属垫结构938的重分布结构920,以及提供包括相应的一组裸片侧金属垫结构(780、880)的至少一个半导体裸片(700、800)。至少一个半导体裸片(700、800)可以使用接合到相应的重分布侧金属垫结构938和裸片侧金属垫结构(780、880)中的相应一者的第一焊料材料部分940来接合到重分布结构920。通常,可以形成金属接头结构的第一阵列。每个金属接头结构可包括第一金属垫结构(例如重分布侧金属垫结构938)、第二金属垫结构(例如裸片侧金属垫结构(780、880))和凸块材料部分(例如第一焊料材料部分940)。
参照图3C,示出高频宽存储器(HBM)裸片810,其可作为图3A和图3B的范例性结构内的存储器裸片800。高频宽存储器裸片810包括静态随机存取存储器裸片(811、812、813、814、815)的垂直堆叠,这些裸片通过微凸块820相互连接,并由环氧成型材料外框816横向地围绕。垂直相邻的随机存取存储器裸片对(811、812、813、814、815)之间的间隙可填充横向围绕相应的一组微凸块820的高频宽存储器底部填充材料部分822。高频宽存储器裸片810可以包括存储器阵列-裸片金属垫结构880被配置为接合到单位面积UA内的重分布侧金属垫结构938的阵列的子集。高频宽存储器裸片810可以被配置为提供JEDEC标准(即由JEDEC固态技术协会定义的标准)下定义的高频宽。
参照图4,可将第一底部填充材料施加到重分布结构920和结合到重分布结构920的多组至少一个半导体裸片(700、800)之间的每个间隙中。第一底部填充材料可以包括本技术领域中任何已知的底部填充材料。第一底部填充材料部分950可以形成每个单位区域UA内的重分布结构920和至少一个半导体裸片(700、800)的上覆组之间。第一底部填充材料部分950可以通过在相应的单位区域UA中的第一焊料材料部分940的相应阵列周围注入第一底部填充材料来形成。可以使用任何已知的底部填充材料施加方法,例如可以是毛细管底部填充方法、成型底部填充方法或印刷底部填充方法。
在每个单位区域UA内,第一底部填充材料部分950可以横向围绕并接触单位区域UA内的每个第一焊料材料部分940。第一底部填充材料部分950可以形成在单元区域UA中的第一焊料材料部分940、重分布侧金属垫结构938和裸片侧金属垫结构(780、880)周围且与第一焊料材料部分940、重分布侧金属垫结构938和裸片侧金属垫结构(780、880)周围接触。
单位面积UA中的每个重分布结构920包括重分布侧金属垫结构938。包括相应组裸片侧金属垫结构(780、880)的至少一个半导体裸片(700、800)通过每个单元区域UA内的相应的一组第一焊料部分940附接到重分布侧金属垫结构938。在每个单位区域UA内,第一底部填充材料部分950横向围绕至少一个半导体裸片(700、800)的重分布侧金属垫结构938和裸片侧金属垫结构(780、880)。
参照图5A和图5B,环氧成型化合物(epoxy molding compound;EMC)可以施加到相应的一组半导体裸片(700、800)的连续组件和第一底部填充材料部分950之间的间隙。
环氧成型化合物可包括可硬化(即固化)以提供具有足够刚性和机械强度的介电材料部分的含环氧树脂化合物。环氧成型化合物可能包括环氧树脂、硬化剂、二氧化硅(作为填充材料)和其他添加剂。环氧成型化合物可以根据粘度和流动性以液态形式或固态形式提供。液态环氧成型化合物提供较好的处理、良好的流动性、较少的空隙、较佳的填充和较少的流痕。固态环氧成型化合物提供较少的固化收缩、较佳的隔离性和较少的裸片偏移。环氧成型化合物中的高填料含量(例如85%重量)可以缩短在模具中的时间,降低模具收缩率,且减少模具翘曲。环氧成型化合物中均匀的填料尺寸分布可减少流痕,且可增强流动性。如果粘着层包括热释放材料,则环氧成型化合物的固化温度可以低于第一粘着层301的释放(剥离)温度。举例而言,环氧成型化合物的固化温度可介于约125℃至约150℃的范围内。
环氧成型化合物可以在固化温度下固化以形成环氧成型化合物基质910M,环氧成型化合物基质910M横向围绕并嵌设一组半导体裸片(700、800)和第一底部填充材料部分950的每个组件。环氧成型化合物基质910M包括可横向相邻的多个环氧成型化合物(EMC)裸片框架。每个环氧成型化合物裸片框架是位于相应单位区域UA内的环氧成型化合物基质910M的一部分。因此,每个环氧成型化合物裸片框架横向围绕并嵌设相应的一组半导体裸片(700、800)和相应的第一底部填充材料部分950。纯环氧树脂的杨氏模量约为3.35GPa,而环氧成型化合物的杨氏模量可比加入添加剂的纯环氧树脂的杨氏模量更高。环氧成型化合物的杨氏模量可大于3.5GPa。
环氧成型化合物基质910M的覆盖水平面(包括半导体裸片(700、800)的顶面)的部分可通过平坦化工艺来移除。举例而言,环氧成型化合物基质910M的覆盖水平面的部分可以使用化学机械平面化来移除。环氧成型化合物基质910M的剩余部分、半导体裸片(700、800)、第一底部填充材料部分950和重分布结构920的二维阵列的组合包括重组晶片900W。位于单位区域UA内的环氧成型化合物基质910M的每个部分构成环氧成型化合物裸片框架。
参照图6,可将第二粘着层401施加到重组晶片900W物理暴露的平坦表面,即环氧成型化合物基质910M、半导体裸片(700、800)和第一底部填充材料部分950的物理暴露表面。在一实施例中,第二粘着层401可以包括与第一粘着层301的材料相同的材料,或者可以包括不同的材料。如果第一粘着层301包括热分解粘着材料,则第二粘着层401包括在更高温度下分解的另一种热分解粘着材料,或者可以包括光热转换材料。
第二载体基底400可以附接到第二粘着层401。第二载体基底400可以附接到重组晶片900W的相对于第一载体基底300的相对侧。通常而言,第二载体基底400可包括可用于第一载体基底300的任何材料。第二载体基底400的厚度可介于约500微米到约2,000微米的范围内,但也可以使用更小和更大的厚度。
第一粘着层301可通过紫外线辐射或通过在剥离温度下的热退火来分解。在第一载体基底300包括光学透明材料且第一粘着层301包括光热转换层的实施例中,第一粘着层301可由通过透明载体基底照射紫外光来分解。光热转换层可吸收紫外线辐射且产生热量,这会分解光热转换层的材料且导致透明的第一载体基底300与重组晶片900W分离。在第一粘着层301包括热分解粘着材料的实施例中,可进行在剥离温度下的热退火工艺以将第一载体基底300从重组晶片900W分离。
参照图7,可通过沉积和图案化至少一种可以用作接合垫的金属材料来形成扇出接合垫928。用于扇出接合垫928的金属填充材料可以包括铜。其他适合的材料亦在本公开的考虑范围内。扇出接合垫928的厚度可介于约5微米到约100微米的范围内,但是也可以使用更小或更大的厚度。扇出接合垫928可以具有矩形、圆角矩形或圆形的水平截面形状。其他适合的形状亦在本公开的考虑范围内。在扇出接合垫928形成为可控塌陷芯片连接(controlled collapse chip connection;C4)垫的实施例中,扇出接合垫928的厚度可介于约5微米到约50微米的范围内,但也可以使用更小或更大的厚度。替代地,扇出接合垫928可以被配置用于微凸块接合(即C2接合),且可以具有介于约30微米到约100微米范围内的厚度,但也可以使用更小或更大的厚度。在此实施例中,扇出接合垫928可以形成为微垫(例如铜柱或凸块下金属层)阵列,具有介于约10微米到约25微米的范围内的横向尺寸,且具有介于约20微米到50微米的范围内的间距。
扇出接合垫928可以相对于重分布结构层形成在环氧成型化合物基质910M和半导体裸片组(700、800)的二维阵列的相对侧上。重分布结构层包括重分布结构920的二维阵列。每个重分布结构920可以位于相应的单位区域UA内。每个重分布结构920可包括重分布介电层922、嵌入在重分布介电层922中的重分布内连线924和扇出接合垫928。扇出接合垫928可位于重分布侧金属垫结构938相对于重分布介电层922的相反侧,且电性连接到重分布侧金属垫结构938中的相应一者。
参照图8,第二粘着层401可以通过紫外线辐射或通过在剥离温度下的热退火来分解。在第二载体基底400包括光学透明材料且第二粘着层401包括光热转换层的实施例中,第二粘着层401可由通过透明载体基底照射紫外光来分解。在第二粘着层401包括热分解粘着材料的实施例中,可进行在剥离温度下的热退火工艺以将第二载体基底400从重组晶片900W分离。
参照图9,包括扇出接合垫928的重组晶片900W可随后通过进行切割工艺沿着切割通道来切割。切割通道对应于相邻对裸片区域DA之间的边界。来自重组晶片900W的每个切割单元包括扇出封装体900。换言之,半导体裸片组(700、800)的二维阵列组件的每个切割部分,第一的二维阵列底部填充材料部分950、环氧成型化合物基质910M和重分布结构920的二维阵列构成扇出封装体900。环氧成型化合物基质910M的每个切割部分构成成型化合物裸片框架910。重分布结构层的每个切割部分(其包括重分布结构920的二维阵列)构成重分布结构920。
参照图10A和图10B,示出通过在图9的工艺步骤中切割范例性结构所获得的扇出封装体900。扇出封装体900包括重分布结构920、至少一个半导体裸片(700、800)以及第一底部填充材料部分950。重分布结构920包括重分布侧金属垫结构938,至少一个半导体裸片(700、800)包括通过相应组的第一焊料材料部分940附接至重分布侧金属垫结构938的相应组的裸片侧金属垫结构(780、880),第一底部填充材料部分950横向围绕重分布侧金属垫结构938和裸片侧金属垫结构(780、880)。
扇出封装体900可包括成型化合物裸片框架910,此成型化合物裸片框架910横向围绕至少一个半导体裸片(700、800)且包括成型化合物材料。在一实施例中,成型化合物裸片框架910包括与重分布结构920的侧壁垂直重合的侧壁(亦即位于与重分布结构920的侧壁相同的垂直平面内)。一般而言,成型化合物裸片框架910可在每个扇出封装体900内形成第一底部填充材料部分950之后形成于至少一个半导体裸片(700、800)周围。成型化合物材料接触重分布结构920的平坦表面的外围部分。
参照图11,第二焊料材料部分290可以附接到扇出接合垫928。封装基底200可通过第二焊料材料部分290接合到扇出封装体900。封装基底200可以是包括芯基底210的有芯封装基底,或不包括封装芯的无芯封装基底。或者,封装基底200可包括整合封装体上系统基底(system-on-integrated package substrate;SoIS),其包括重分布层及/或介电中间层、至少一个嵌入式中介层(例如硅中介层)。这种整合封装体上系统基底可包括使用接合材料部分的层间内连线、底部填充材料部分(例如成型底部填充材料部分)及/或可选的粘着层(未图示)。虽然使用范例性基底封装体来说明本公开,但应理解的是本公开的范围不受任何特定类型的基底封装体的限制,且可包括整合封装体上系统。芯基底210可以包括玻璃环氧树脂板,其包括通板孔阵列。可以在通板孔中提供包括金属材料的穿芯通孔结构214的阵列。每个穿芯通孔结构214可以或可以不包括其中的圆柱形空心。可选地,介电衬垫212可用于将穿芯通孔结构214与芯基底210电性隔离。
封装基底200可以包括板侧表面层状电路(surface laminar circuit;SLC)240和芯片侧表面层状电路(SLC)260。板侧表面层状电路可以包括嵌设板侧内连线244的板侧绝缘层242。芯片侧表面层状电路260可以包括嵌设芯片侧内连线264的芯片侧绝缘层262。板侧绝缘层242和芯片侧绝缘层262可以包括可光刻图案化且随后固化的光敏环氧树脂材料。板侧内连线244和芯片侧内连线264可包括可通过电镀沉积在板侧绝缘层242或芯片侧绝缘层262中的图案内的铜。
在一实施例中,封装基底200包括芯片侧表面层状电路260和板侧表面层状电路240。芯片侧表面层状电路260包括芯片侧内连线264,芯片侧内连线264连接到芯片侧接合垫268的阵列,芯片侧接合垫268的阵列可接合到第二焊料材料部分290的阵列。板侧表面层状电路240包括连接到板侧接合垫248的阵列的板侧内连线244。板侧接合垫248的阵列可被配置为允许通过焊球进行接合。芯片侧接合垫268的阵列可被配置为允许通过可控塌陷芯片连接(C4)焊球接合。通常而言,可使用任何类型的封装基底200。尽管使用封装基底200包括芯片侧表面层状电路260和板侧表面层状电路240的实施例来说明本公开,但是本公开亦明确考虑到芯片侧表面层状电路260和板侧表面层状电路240的其中一者被省略的实施例,或者被例如微凸块的接合结构阵列所取代。在说明性范例中,芯片侧表面层状电路260可用微凸块阵列或任何其他接合结构阵列来取代。
附接到扇出封装体900的扇出接合垫928的第二焊料材料部分290可以设置在封装基底200的芯片侧接合垫268的阵列上。可进行回流工艺以回流第二焊料部分290,进而使扇出封装体900和封装基底200之间接合。在一实施例中,第二焊料材料部分290可包括可控塌陷芯片连接焊球,且扇出封装体900可以使用可控塌陷芯片连接焊球阵列将其连接到封装基底200。通常来说,可形成金属接头结构的第二阵列。每个金属接头结构可包括第一金属垫结构(例如芯片侧垫268)、第二金属垫结构(例如扇出接合垫928)以及凸块材料部分(例如第二焊料材料部分290)。
参照图12A和图12B,可通过施加和成形第二底部填充材料以在第二焊料材料部分290周围形成第二底部填充材料部分292。第二底部填充材料部分292可通过施加和成形第二底部填充材料而形成在第二焊料材料部分290周围。第二底部填充材料部分292可通过在第二焊料材料部分290回流之后围绕第二焊料材料部分290的阵列注入第二底部填充材料来形成。可使用任何已知的底部填充材料施加方法,例如可以是毛细管底部填充方法、成型底部填充方法或印刷底部填充方法。
第二底部填充材料部分292可以形成在重分布结构920和封装基底200之间。根据本公开的一方面,第二底部填充材料部分292可以直接形成在成型化合物裸片框架910的每个侧壁上。
第二底部填充材料部分292可以接触每个第二焊料材料部分290(其可以是可控塌陷芯片连接焊球或微凸块焊帽),且可接触扇出封装体900的垂直侧壁。第二底部填充材料部分形成在重分布结构920和封装基底200之间。第二底部填充材料部分横向围绕并接触第二焊料材料部分290的阵列和扇出封装体900。
在一实施例中,第二底部填充材料部分292可以包括锥形侧壁,锥形侧壁从成型化合物裸片框架910的相应侧壁连续地延伸到封装基底200的平坦表面(例如顶面)。锥形侧壁的锥形角度可介于约10度到约80度的范围内,例如约30度到约60度,但是也可以使用更小和更大的锥形角。锥形角可能是一致的,也可能并非一致。在一实施例中,锥形侧壁可以始终具有相同的锥形角(从垂直方向测量)。
参照图13A至图13C,可通过切割第二底部填充材料部分292的部分在第二底部填充材料部分292中形成至少一个切割区域CR。图13A示出一实施例,其中第二底部填充材料部分292的移除部分可通过使用铣削设备620铣削第二底部填充材料部分的移除部分来切割。移除部分中的第二底部填充材料部分292的材料可由铣削装置来铣削。图13B示出可通过将激光束610照射到第二底部填充材料部分292的每个切割区域CR来切割第二底部填充材料部分292的移除部分的实施例。第二底部填充材料部分292的材料可通过由激光装置600所发射的激光束610进行激光照射来削磨。
在一实施例中,第二底部填充材料部分292的部分可被切割以在每个切割区域CR内提供至少一个垂直延伸表面和水平延伸表面。相互邻接的多个垂直延伸表面可以形成在一或多个切割区域CR内。在此实施例中,第二底部填充材料部分292的至少一个切割区域CR中的每一者可包括具有均匀横向宽度的垂直延伸段部以及具有均匀垂直厚度且邻接至垂直延伸段部的底端的横向延伸段部。
在一实施例中,第二底部填充材料部分292中的至少一个部分可以不被形成至少一个切割区域CR的铣削工艺及/或激光照射工艺所移除。在此实施例中,第二底部填充材料部分292包括至少一个锥形区域TR,此锥形区域TR在形成至少一个切割区域CR之后具有相应的锥形侧壁。在图13C所示的范例中,四个切割区域CR可以形成在第二底部填充材料部分292的角落区域中,且四个锥形区域TR可以形成在成型化合物裸片框架910的侧壁上。在此实施例中,相应的锥形侧壁包括相应的上部边缘,其接触成型化合物裸片框架910的相应侧壁的其中一者。
在一实施例中,至少一个锥形区域TR中的每一者在平面图中可位于由成型化合物裸片框架910的侧壁所界定的区域之外,且具有三角形的水平截面形状。在一实施例中,至少一个切割区域CR中的每一者可横向邻接至至少一个锥形区域TR中的相应一者。在一实施例中,第二底部填充材料部分292的三角形侧壁可以位于至少一个切割区域CR中的相应一者与至少一个锥形区域TR中的相应一者之间的每个边界处。
通常而言,第二底部填充材料部分292包括位于包括扇出封装体900的侧壁的垂直平面内部的部分和位于包括扇出封装体900的侧壁的垂直平面外部的部分。位于包括扇出封装体900的侧壁的垂直平面内的第二底部填充材料部分292在本公开中被称为基底间底部填充部分。基底间底部填充部分横向围绕第二焊料材料部分290,且在平面图中(即沿垂直于第一底部填充材料部分950和重分布结构920之间的界面的垂直方向的视图中),可位于成型化合物裸片框架910的周缘内。位于包括扇出封装体900的侧壁的垂直平面之外的第二底部填充材料部分292的部分在本公开中被称为外围底部填充部分。外围底部填充部分在平面图中位于成型化合物裸片框架910的外周缘之外,且包括至少一个切割区域CR。在至少一个切割区域CR中的每一者内,定位具有均匀横向宽度的垂直延伸段部和具有均匀垂直厚度且邻接垂直延伸段部的底端的横向延伸段部。
参照图13B,在一实施例中,至少一个切割区域CR中的每一者内的垂直延伸段部可在垂直平面内具有最大垂直范围,此垂直平面包括与成型化合物裸片框架910的相应侧壁的界面。最大垂直范围在此称为第一垂直距离vd1。在一实施例中,至少一个切割区域CR中的每一者内的横向延伸段部具有均匀的垂直厚度,其在本公开中被称为第二垂直距离vd2。均匀垂直厚度(即第二垂直距离vd2)与最大垂直范围(即第一垂直距离vd1)的比值可介于约0.01到约0.1的范围内。在一实施例中,第一垂直距离vd1可介于约200微米到约2毫米的范围内,例如约400微米到约1毫米,但也可以使用更小和更大的垂直距离。在一实施例中,第二垂直距离可介于约10微米到约200微米的范围内,例如约20微米到约100微米,及/或约40微米到约70微米,但也可以使用更小和更大的垂直距离。
参照图13C、图14A和图14B,在各种实施例中,至少一个切割区域CR中的每一者内的横向延伸段部在接触封装基底200的水平面处具有最大横向范围。最大横向范围可以是横向延伸段部的底部边缘和包括与成型化合物裸片框架910的相应侧壁的界面的垂直平面之间的横向距离。最大横向范围在本公开中被称为第一间距S1。垂直延伸段部的均匀横向宽度在本公开中被称为第二间距S2。在一实施例中,均匀横向宽度(即第二间距S2)与最大横向范围(即第一间距S1)的比值可介于约0.01到约0.1的范围内。在一实施例中,第一间距S1可介于约200微米到约2毫米的范围内,例如约400微米到约1毫米,但也可以使用更小和更大的垂直距离。在一个实施例中,第二间距S2可介于约10微米到约200微米的范围内,例如约20微米到约100微米,及/或约40微米到约70微米,但也可以使用更小和更大的垂直距离。
在一实施例中,成型化合物裸片框架910在平面图中可以具有矩形外周缘,且至少一个切割区域CR包括四个切割区域CR,位于矩形外周缘的四个角之外且靠近矩形的四个角落。
在一实施例中,成型化合物裸片框架910包括一对沿第一水平方向hd1横向延伸的纵向侧壁和一对沿第二水平方向hd2横向延伸的横向侧壁。至少一个切割区域CR包括四个切割区域CR,位于该对纵向侧壁与该对横向侧壁邻接的四个角落的外侧,且靠近这四个角落。在一实施例中,沿第一水平方向hd1的四个切割区域CR之间的最大横向间距可以小于沿第一水平方向hd1的该对纵向侧壁的长度。在一实施例中,四个切割区CR沿第二水平方向hd2的最大横向间距小于该对横向侧壁沿第二水平方向hd2的长度。
在一实施例中,成型化合物裸片框架910可以具有矩形外周缘,其具有沿纵向方向(例如第一水平方向hd1)的第一长度Ll和沿横向方向(例如第二水平方向hd2)的第一宽度Wl。在一实施例中,一或多个切割区域CR可以具有呈L形水平截面形状的空隙,空隙包括沿第一水平方向hd1横向延伸的部分和沿第二水平方向hd2横向延伸的部分。切割区域CR的空隙部分沿第一水平方向hd1延伸的横向距离是在包括成型化合物模具框架910的近端横向侧壁的垂直平面和包括与沿第一水平方向hd1横向延伸的锥形区域TR邻接的空隙的端部的垂直平面之间沿第一水平方向hd1来测量。此横向距离在本公开中被称为纵向切割距离或第二长度L2。切割区域CR的空隙部分沿第二水平方向hd2测量的横向距离是在包括成型化合物模具框架910的近端纵向侧壁的垂直平面和包括与沿第二水平方向hd2横向延伸的锥形区域TR邻接的空隙的端部的垂直平面之间沿第二水平方向hd2来测量。此横向距离在本公开中被称为横向切割距离或第二宽度W2。
第一长度Ll可介于约0.5mm到约30mm的范围内,例如约1mm到约15mm。第一宽度W1可介于约0.5mm到约30mm的范围内,例如约1mm到约15mm。第二长度L2与第一长度L1的比值在四个切割区域CR中的每一者中可彼此相同,或者可在四个切割区域CR之间不同。第二长度L2与第一长度L1的比值可介于约0.005到约0.9999的范围内,例如约0.01到约0.4。举例而言,第二长度L2可介于约100μm到约1mm的范围内。第二宽度W2与第一宽度W1的比值在四个切割区域CR中的每一者中可彼此相同,或者可在四个切割区域CR之间不同。第二宽度W2与第一宽度W1的比率可介于约0.005到约0.9999的范围内,例如约0.01到约0.4。举例而言,第二宽度W2可介于约100μm到约1mm的范围内。
在一实施例中,外围底部填充部分邻接基底间底部填充部分的周缘,接触重分布结构920的侧壁和成型化合物裸片框架910的侧壁,且接触封装基底200的平坦表面。第二底部填充材料部分292包括至少一个锥形区域TR,其具有从成型化合物裸片框架910的相应侧壁连续地延伸到封装基底200的平坦表面的相应锥形侧壁。在一实施例中,至少一个锥形区域TR的每一者包括接触成型化合物裸片框架910的相应侧壁的垂直侧壁以及接触封装基底200的平坦表面的水平表面。
参照图14A,示出范例性结构的第一替代配置,其可由图13A至图13C的范例性结构衍生出,形成少于四个切割区域CR。切割区域CR的总数可以是1、2或3。至少一个切割区域CR中的每一者可以形成在成型化合物裸片框架910的相应角落附近。切割区域CR中的每一者可参照图13A至图13C的范例性结构所述的任何配置来形成。
参照图14B,示出范例性结构的第二替代配置,其可由图13A至图13C的范例性结构衍生出,增加第二长度L2和第二宽度W2直到角落区域CR中的所有空隙合并,以形成横向围绕成型化合物裸片框架910的整个侧壁组的连续空隙。在此实施例中,在至少一个切割区域DR包括且由环绕成型化合物裸片框架910的单个连续切割区域CR组成。
参照图15,稳定结构294(例如帽结构或环结构)可附接到扇出封装体900和封装基底200的组件,以减少在后续工艺步骤及/或组件使用期间的变形。
参照图16,可提供包括印刷电路板(printed circuit board;PCB)基底110和印刷电路板接合垫180的印刷电路板100。印刷电路板100包括印刷电路(未图示),至少位在印刷电路板基底110的一侧。可形成焊点阵列190以将板侧接合垫248的阵列接合到印刷电路板接合垫180的阵列。可通过将焊球阵列设置在板侧垫阵列248和印刷电路板垫阵列180之间且对焊球阵列进行回流来形成焊点190。底部填充材料部分192可通过施加和成形底部填充材料而形成在焊点190周围。封装基底200通过焊点阵列190附接到印刷电路板100。
参照图17,流程图示出用于形成根据本公开实施例的范例性结构的步骤。
参照步骤1710和图1A、图1B、图2A和图2B,可提供重分布结构920。
参照步骤1720和图3A至图3C,至少一个半导体裸片(700、800)可以使用第一焊料部分940附接到重分布结构920。
参照步骤1730和图4,第一底部填充材料部分950可形成在第一焊料材料部分940周围。
参照步骤1740和图5A至图11,可使用第二焊料部分290将封装基底200附接到重分布结构920。
参照步骤1750和图12A、图12B,第二底部填充材料部分292可形成在第二焊料材料部分290周围和重分布结构920周围。
参照步骤1760和图13A至图16,通过切割第二底部填充材料部分292的至少一部分,可在第二底部填充材料部分292中形成至少一个切割区域CR。
参照所有附图且根据本公开的各个实施例,提供了一种芯片封装结构,其可包括:至少一个半导体裸片(700、800),通过焊料材料部分940附接到重分布结构920;第一底部填充材料部分950,位于重分布结构920和至少一个半导体裸片(700、800)之间并横向围绕至少一个半导体裸片(700、800)的一部分;成型化合物裸片框架910横向围绕至少一个半导体裸片(700、800);以及第二底部填充材料部分292接触重分布结构920的侧壁和成型化合物裸片框架910的侧壁,且可包括至少一个切割区域CR,其中第二底部填充材料部分292可包括具有均匀横向宽度(例如第二间距S2)的垂直延伸段部,以及具有均匀垂直厚度(例如第二垂直距离vd2)且在至少一个切割区域CR中的每一者内邻接垂直延伸段部的底端的横向延伸段部。
在一实施例中,第二底部填充材料部分292可包括具有相应锥形侧壁的至少一个锥形区域TR。在一实施例中,相应的锥形侧壁可以包括与成型化合物裸片框架910的相应一侧壁接触的相应上边缘。在一实施例中,至少一个锥形区域TR中的每一者位于由成型化合物裸片框架910的侧壁所界定的区域之外,且在平面图中具有三角形的水平截面形状。
在一实施例中,至少一个切割区域CR中的每一者可横向邻接至至少一个锥形区域TR中的相应一者。在一实施例中,第二底部填充材料部分292的三角形侧壁可位于至少一个切割区域CR中的相应一者与至少一个锥形区域TR中的相应一者之间的每个边界处。
在一个实施例中,至少一个切割区域CR中的每一者内的垂直延伸段部在包括成型化合物裸片框架910的相应侧壁的界面的垂直平面内具有最大垂直范围(例如第一垂直距离vdl)。至少一个切割区域CR中的每一者内的横向延伸段部在接触封装基底200的水平面处具有最大横向范围(例如第一间距S1)。最大横向范围可以是横向延伸段部的底部边缘与包括与成型化合物裸片框架910的相应侧壁的界面的垂直平面之间的距离。均匀横向宽度(例如第二间距S2)与最大横向范围的比率(例如第一间距S1)可介于0.01到0.1的范围内。均匀垂直厚度(例如第二垂直距离vd2)与最大垂直范围(例如第一垂直距离vd1)的比值介于0.01到0.1的范围内。
在一实施例中,成型化合物模具框架910在平面图中具有矩形外周缘,且至少一个切割区域CR可包括四个切割区域CR,位于矩形外周缘的四个角落的外侧且靠近四个角落。
在一实施例中,成型化合物裸片框架910可包括沿第一水平方向hdl横向延伸的一对纵向侧壁以及沿第二水平方向hd2横向延伸的一对横向侧壁。在一实施例中,至少一个切割区域CR可包括四个切割区域CR,位于该对纵向侧壁与该对横向侧壁邻接的四个角落的外侧且靠近四个角落。在一实施例中,四个切割区域CR沿第一水平方向hd1的最大横向间距小于该对纵向侧壁沿第一水平方向hd1的长度。在一个实施例中,沿第二水平方向hd2的四个切割区域CR之间的最大横向间距可小于该对横向侧壁沿第二水平方向hd2的长度。
在一实施例中,至少一个切割区域CR可包括单一个连续切割区域CR,其围绕成型化合物裸片框架910。
根据本公开的另一方面,提供了一种芯片封装结构,其可包括:至少一个半导体裸片(700、800),附接到重分布结构920;第一底部填充材料部分950横向围绕至少一个半导体裸片(700、800)的一部分;成型化合物裸片框架910横向围绕至少一个半导体裸片(700、800);封装基底200附接至重分布结构920;以及第二底部填充材料部分292,其可包括:横向围绕重分布结构920且在平面图中位于成型化合物910的外周缘内的基底间底部填充部分,以及在平面图中位于成型化合物910的外周缘之外且包括具有L形垂直截面形状的至少一个切割区域的外围底部填充部分,其中至少一个切割区域CR中的每一者包含具有均匀横向宽度的垂直延伸段部(例如第二间距S2)和横向延伸段部。在一实施例中,在至少一个切割区域CR的每一者中存在具有均匀横向宽度(例如第二间距S2)的垂直延伸段部及/或具有均匀垂直厚度(例如第二垂直距离vd2)且邻接垂直延伸段部的底端的横向延伸段部。
在一实施例中,外围底部填充部分可邻接基底间底部填充部分的周缘,接触重分布结构920的侧壁和成型化合物裸片框架910的侧壁,且接触封装基底200的平坦表面。
在一实施例中,第二底部填充材料部分292可包括至少一个锥形区域TR,具有从成型化合物裸片框架910的相应侧壁连续延伸到封装基底200的平坦表面的相应锥形侧壁。
在一实施例中,至少一个锥形区域TR中的每一者可包括接触成型化合物裸片框架910的相应侧壁的垂直侧壁以及接触封装基底200的平坦表面的水平表面。
在一实施例中,至少一个切割区域CR可包括单一个连续切割区域CR,其围绕成型化合物裸片框架910。
根据本公开的另一方面,提供了一种芯片封装结构的制造方法,其可包括:提供重分布结构;将至少一个半导体裸片附接到重分布结构;在重分布结构和至少一个半导体裸片之间形成第一底部填充材料部分;将封装基板附接到重分布结构;在重分布结构与封装基板之间并围绕重分布结构形成第二底部填充材料部分;以及通过切割第二底部填充材料部分的部分,在第二底部填充材料部分中形成至少一个切割区域。
在一实施例中,切割第二底部填充材料部分的部分以在每个切割区域内提供至少一个垂直延伸表面和水平延伸表面。
在一实施例中,此方法包括在第一底部填充材料部分和至少一个半导体裸片周围形成成型化合物;第二底部填充材料部分包括在形成至少一个切割区域之前从成型化合物的相应侧壁连续延伸到封装基底的平坦表面的锥形侧壁;以及第二底部填充材料部分的至少一个切割区域中的每一者包括具有均匀横向宽度的垂直延伸段部以及具有均匀垂直厚度并邻接于垂直延伸段部的底端的横向延伸段部。
在一实施例中,通过将激光束照射到第二底部填充材料部分的每个切割区域来切割第二底部填充材料部分的部分,由此通过由激光束所照射的激光来削磨第二底部填充材料部分的材料。
在一实施例中,通过使用铣削设备铣削第二底部填充材料部分的部分来切割第二底部填充材料部分的部分,由此铣削设备铣削第二底部填充材料部分的材料。
本公开的各种结构和方法可用于提供包括扇出封装体900的芯片封装结构,扇出封装体900包括至少一个切割区域CR,这减少了扇出封装体900和封装基底200之间的机械耦合,且减少扇出封装体900在机械及/或热应力下的变形。本公开的芯片封装结构提供了避免形成应力集中点的配置,在处理芯片封装结构期间或在使用包括芯片封装结构的装置期间,成型化合物材料部分可能在机械应力下从应力集中点开始形成裂纹。本公开的各种方法和结构可用于减少扇出封装体900的变形并增加扇出封装体900的可靠性。
以上概述了许多实施例的特征,使本公开所属技术领域中技术人员可以更加理解本公开的各实施例。本公开所属技术领域中技术人员应可理解,可以本公开实施例为基础轻易地设计或改变其他工艺及结构,以实现与在此介绍的实施例相同的目的及/或达到与在此介绍的实施例相同的优点。本公开所属技术领域中技术人员也应了解,这些相等的结构并未背离本公开的精神与范围。在不背离随附权利要求的精神与范围的前提下,可对本公开实施例进行各种改变、置换及变动。
Claims (1)
1.一种芯片封装结构,包括:
至少一半导体裸片,附接至一重分布结构:
一第一底部填充材料部分,位于该重分布结构和该至少一半导体裸片之间,且横向地围绕该至少一半导体裸片的一部分;
一成型化合物,横向地围绕该至少一半导体裸片;以及
一第二底部填充材料部分,接触该重分布结构的多个侧壁和该成型化合物的多个侧壁,且包括至少一切割区域,其中该第二底部填充材料部分包括一垂直延伸段部和一横向延伸段部,该垂直延伸段部具有一均匀横向宽度,该横向延伸段部具有一均匀垂直厚度,且在该至少一切割区域的每一者内邻接于该垂直延伸段部的一底端。
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US17/523,955 US11908757B2 (en) | 2021-06-18 | 2021-11-11 | Die corner removal for molding compound crack suppression in semiconductor die packaging and methods for forming the same |
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US9524945B2 (en) * | 2010-05-18 | 2016-12-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cu pillar bump with L-shaped non-metal sidewall protection structure |
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US8993380B2 (en) * | 2013-03-08 | 2015-03-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for 3D IC package |
US9659907B2 (en) * | 2015-04-07 | 2017-05-23 | Apple Inc. | Double side mounting memory integration in thin low warpage fanout package |
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US10037974B2 (en) * | 2016-03-08 | 2018-07-31 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package and method of manufacturing the same |
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