CN115242226A

CN115242226A - Comparator, analog-to-digital converter and method for controlling comparator

Info

Publication number: CN115242226A
Application number: CN202210763945.3A
Authority: CN
Inventors: 李博; 曹军涛; 李晴
Original assignee: Wuhu Research Institute of Xidian University
Current assignee: Wuhu Research Institute of Xidian University
Priority date: 2022-06-29
Filing date: 2022-06-29
Publication date: 2022-10-25

Abstract

The invention discloses a comparator, an analog-to-digital converter and a method for controlling the comparator, wherein the comparator comprises: the pre-amplification circuit comprises at least two cascaded operational amplifiers and is used for amplifying an input signal; the latch circuit is connected with the pre-amplifying circuit and used for determining the output result of the comparator according to the output voltage of the pre-amplifying circuit; the operational amplifiers all comprise tail current sources and tail current source switches connected with the high-level output end of the driving power supply, the operational amplifiers are all provided with tail current source switches which are conducted, the comparator of the operational amplifiers for continuously amplifying input signals is in a first state of a static comparator, the tail current source switches are controlled by periodic switch signals, and the comparator is in a second state of a dynamic comparator. The comparator in the invention can achieve the effects of high speed, high precision and low power consumption.

Description

Comparator, analog-to-digital converter and method for controlling comparator

Technical Field

The present invention relates to the field of analog integrated circuit technology, and in particular, to a comparator, an analog-to-digital converter, and a method for controlling a comparator.

Background

A comparator is a module that compares an input signal with a reference signal and then generates a logic output level, which is widely used in the conversion of an analog signal into a digital signal, and is a key module in the design of a mixed-signal circuit. In the conversion of analog signals to digital signals, the speed of the comparator is a limiting factor in the overall conversion speed. At present, a comparator is generally divided into a static comparator and a dynamic comparator, wherein the static comparator can continuously compare two input signals without any clock signal to control a time sequence or enable, the precision is higher, but the comparator also has the defects of high power consumption and relatively low speed; the dynamic comparator switches the working state according to clock turnover, so that the power consumption is low, but the dynamic comparator has the defects of large offset voltage and relatively low precision.

Therefore, it is an urgent need to provide a high-precision low-power comparator.

Disclosure of Invention

Therefore, in order to solve the above problems occurring in the prior art, the present application provides a comparator with high precision and low power consumption, a control method thereof, and a corresponding analog-to-digital converter.

To this end, according to a first aspect, the invention provides a comparator comprising:

the pre-amplification circuit comprises at least two cascaded operational amplifiers and is used for amplifying an input signal;

the latch circuit is connected with the pre-amplifying circuit and used for determining the output result of the comparator according to the output voltage of the pre-amplifying circuit;

the operational amplifiers comprise tail current sources and tail current source switches connected with a high-level output end of the driving power supply, the operational amplifiers are all provided with tail current source switches which are conducted, a comparator for continuously amplifying input signals of the operational amplifiers is in a first state of a static comparator, the tail current source switches are controlled by periodic switch signals, and the comparator is in a second state of a dynamic comparator.

Further, offset elimination capacitors are connected in series between adjacent operational amplifiers;

two input ends of a first-stage operational amplifier in the pre-amplification circuit are respectively connected with a pair of first switches, and the other ends of the first switches are connected with the output end of the common-mode voltage;

two output ends of a first-stage operational amplifier in the pre-amplification circuit are respectively connected with a pair of second switches, and the other ends of the second switches are connected with the output end of the common-mode voltage;

a pair of third switches are respectively connected between the positive phase input end and the negative phase output end of other operational amplifiers in the pre-amplifying circuit, and between the negative phase input end and the positive phase output end;

the maladjustment elimination of the comparator is carried out by switching off the second switch after the first switch and the second switch are switched on and the voltage between the two input ends of the comparator is stabilized to the common-mode voltage.

Further, the pre-amplifying circuit includes three stages of operational amplifiers, which are a first amplifier, a second amplifier and a third amplifier, respectively, the first amplifier and the second amplifier have the same structure, and the first amplifier includes:

a PMOS tube QP1, the drain of which is connected with the high-level output end VDD of the driving power supply, and the gate of which is connected with the output end Bias1 of the first Bias voltage;

a drain electrode of the PMOS tube QP2 is connected with a source electrode of the PMOS tube QP1, and a grid electrode of the PMOS tube QP2 is connected with an enable switch signal enable;

the drain electrodes of the PMOS tube QP3 and the PMOS tube QP4 are connected with the source electrode of the PMOS tube QP2, the grid electrode of the PMOS tube QP3 is connected to the positive phase input end Vip, and the grid electrode of the PMOS tube QP4 is connected to the negative phase input end Vin;

the grid electrodes of the PMOS tube QP5 and the PMOS tube QP6 are connected with the output end Bias2 of the second Bias voltage; the drain electrode of the PMOS tube QP5 is connected with the source electrode of the PMOS tube QP3, and the source electrode of the PMOS tube QP5 is connected with the inverted output end Von; the drain electrode of the PMOS pipe QP6 is connected with the source electrode of the PMOS pipe QP4, and the source electrode of the PMOS pipe QP6 is connected with the positive phase output end Vop;

the NMOS transistor QN1 and the NMOS transistor QN2 are respectively connected with the low-level output end VSS of the driving power supply by the source electrodes, the grid electrode and the drain electrode of the NMOS transistor QN1 and the drain electrode of the NMOS transistor QN2 are respectively connected with the inverted output end Von, and the grid electrode of the NMOS transistor QN2 is connected with the positive phase output end Vop;

the source electrodes of the NMOS tube QN3 and the NMOS tube QN4 are connected with a low-level output end VSS of the driving power supply, the grid electrode and the drain electrode of the NMOS tube QN3 and the drain electrode of the NMOS tube QN4 are connected with a positive phase output end Vop, and the grid electrode of the NMOS tube QN4 is connected with a reverse phase output end Von.

Further, gm values of the NMOS transistors QN1 and QN2 are greater than gm values of the NMOS transistors QN3 and QN 4.

Further, the first amplifier further comprises:

the drain of the NMOS transistor QN5 is connected to the positive phase output terminal Vop, the source thereof is connected to the negative phase output terminal Von, and the gate thereof is connected to the pulse control signal RST.

Further, the third amplifier includes:

a PMOS transistor QP7, the drain of which is connected with the high level output end VDD of the driving power supply, and the gate of which is connected with the output end Bias1 of the first Bias voltage;

a drain electrode of the PMOS tube QP8 is connected with a source electrode of the PMOS tube QP7, and a grid electrode of the PMOS tube QP8 is connected with an enable switch signal enable;

the drain electrodes of the PMOS tube QP9 and the PMOS tube QP10 are connected with the source electrode of the PMOS tube QP8, the grid electrode of the PMOS tube QP9 is connected to the positive phase input end Vip, and the grid electrode of the PMOS tube QP10 is connected to the negative phase input end Vin;

the NMOS transistor QN6 and the NMOS transistor QN7 are connected, the source electrodes of the NMOS transistor QN6 and the NMOS transistor QN7 are connected with a low-level output end VSS of the driving power supply, the grid electrode and the drain electrode of the NMOS transistor QN6 and the drain electrode of the NMOS transistor QN7 are connected with a reverse phase output end Von, and the grid electrode of the NMOS transistor QN7 is connected with a normal phase output end Vop;

the source electrodes of the NMOS tube QN8 and the NMOS tube QN9 are connected with a low-level output end VSS of the driving power supply, the grid electrode and the drain electrode of the NMOS tube QN8 and the drain electrode of the NMOS tube QN9 are connected with a positive phase output end Vop, and the grid electrode of the NMOS tube QN9 is connected with a reverse phase output end Von.

Further, the third amplifier further comprises

The drain of the NMOS transistor QN10 is connected to the positive phase output terminal Vop, the source thereof is connected to the negative phase output terminal Von, and the gate thereof is connected to the pulse control signal RST.

According to a second aspect, the present invention provides an analog to digital converter comprising:

a capacitor array;

the comparator in the first aspect described above;

successive approximation logic.

According to a third aspect, the present invention provides a method of controlling the comparator of the first aspect, comprising:

when the comparator carries out offset elimination and sampling, a first preset voltage is applied to the tail current source switch so as to enable the tail current source switch to be conducted;

when the comparator carries out successive progressive comparison and the latch circuit is in a reset state, applying a first preset voltage on the tail current source switch to enable the tail current source switch to be conducted;

and when the comparator performs successive progressive comparison and the latch circuit is in a set state, applying a second preset voltage to the tail current source switch to turn off the tail current source switch.

The technical scheme provided by the invention has the following advantages:

1. the comparator provided by the invention firstly meets the basic precision requirement of the comparator by arranging the pre-amplifying circuit comprising at least two cascaded operational amplifiers; meanwhile, the operational amplifier comprises a tail current source and a tail current source switch which are connected with a high-level output end of the driving power supply, so that the comparator has a static mode that the tail current source switch is conducted and the operational amplifier continuously amplifies input signals, and a dynamic mode that the tail current source switch is controlled by a periodic switch signal (the periodic switch signal is a working state signal of a latch circuit, when the latch circuit is in a reset state, the tail current source switch is conducted, and when the latch circuit is in a set state, the tail current source switch is turned off), namely the working state of the comparator can be configured, and then the comparator can be configured in the static mode in a step-out elimination stage and a sampling stage to ensure comparison accuracy, and configured in the dynamic mode in a successive step-by-step comparison stage to reduce the power consumption of the comparator and achieve the effects of high speed, high accuracy and low power consumption.

2. The comparator provided by the invention has the advantages that the offset circuit structure is set to be the offset elimination capacitor connected in series between the adjacent operational amplifiers, two input ends of the first-stage operational amplifier are respectively connected with the pair of first switches, the other end of each first switch is connected with the output end of the common-mode voltage, two output ends of the first-stage operational amplifier are respectively connected with the pair of second switches, the other end of each second switch is connected with the output end of the common-mode voltage, the positive phase input end and the negative phase output end of other operational amplifiers in the pre-amplification circuit are connected with the positive phase input end and the positive phase output end respectively, and the situation that the noise of input signals is increased and the precision of the comparator is influenced due to the fact that the switches are arranged between the input ends of the first-stage operational amplifier and the input signals can be avoided; meanwhile, before offset cancellation, the first switch is controlled to be turned on until the voltage between the two input ends of the comparator is stabilized to the common-mode voltage, the influence of the turning-on of the first switch (namely, the connection of a normal phase input signal and a reverse phase input signal) on the input signal is eliminated, the second switch is kept turned on in the process, and the influence of voltage jump between the input ends of the first-stage operational amplifier on offset storage of the first-stage operational amplifier is prevented, so that the offset cancellation can be fully and effectively performed afterwards, and the precision of the comparator is further improved.

3. According to the comparator provided by the invention, the PMOS tube QP5 is arranged between the positive phase input end Vip and the negative phase output end Von in the first amplifier and the second amplifier, and the PMOS tube QP6 is arranged between the negative phase input end Vin and the positive phase output end Vop, so that the input and the output are isolated, the influence of feedback on the input can be reduced, and the precision of the comparator is further improved.

4. According to the comparator provided by the invention, the NMOS tube QN5 is arranged between the input end and the output end, and the grid electrode of the NMOS tube QN5 is connected with the pulse control signal RST, so that the NMOS tube QN5 can be arranged to be controlled by the pulse control signal RST to be conducted at the rising edge of each comparison period when the comparator is in a successive and gradual comparison stage, the memory effect of the operational amplifier is eliminated, the operational amplifier can be quickly reset, and the speed of the comparator is improved.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.

Fig. 1 is a schematic structural diagram of a comparator according to an embodiment of the present invention;

FIG. 2 is a timing diagram illustrating operation of a comparator according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of another comparator according to an embodiment of the present invention;

fig. 4 is an equivalent circuit diagram of a first amplifier according to an embodiment of the present invention;

fig. 5 is an equivalent circuit diagram of a third amplifier according to an embodiment of the present invention;

FIG. 6 is an equivalent circuit diagram of another first amplifier according to an embodiment of the present invention;

fig. 7 is an equivalent circuit diagram of another third amplifier according to an embodiment of the present invention;

fig. 8 is an equivalent circuit diagram of a latch circuit according to an embodiment of the present invention;

fig. 9 is a flowchart of a method for controlling a comparator according to an embodiment of the present invention.

Detailed Description

The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it is to be understood that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In the description of the present invention, it should be noted that the terms "upper", "lower", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, which are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and operate, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

Example 1

Fig. 1 shows a schematic structural diagram of a comparator according to an embodiment of the present invention. As shown in fig. 1, the comparator includes a pre-amplifying circuit and a latch circuit.

The pre-amplifying circuit comprises at least two cascaded operational amplifiers (OP 1 \8230; OPn, n ≧ 2 in figure 1) for amplifying an input signal.

The latch circuit is connected with the pre-amplifying circuit and used for determining the output result of the comparator according to the output voltage of the pre-amplifying circuit.

The operational amplifiers each include a tail current source and a tail current source switch connected to a high level output (VDD) of the driving power supply, the operational amplifiers each have a tail current source switch conductive, the comparator of the operational amplifier continuously amplifying the input signal is in a first state of a static comparator, and the tail current source switch is controlled by a periodic switch signal, the comparator is in a second state of a dynamic comparator.

Fig. 2 shows an operation timing diagram of the comparator, wherein clk is the timing of the system clock signal, and enable is the timing of the enable switch signal of the tail current source switch. As shown in fig. 2, when the comparator is in the offset canceling phase and the sampling phase, a first predetermined voltage (shown as a low level in fig. 2) is applied to the tail current source switch to turn on the tail current source switch; when the comparator is in the successive progressive comparison stage, a pulse voltage (i.e., a periodic switching signal) which is formed by alternating a first predetermined voltage (shown by a low level in fig. 2) and a second predetermined voltage (shown by a high level in fig. 2) is applied to the tail current source switch, specifically, the enable signal is a clock inversion signal, when the clock signal is at a high level, the latch circuit is in a reset state, and the enable signal is at a low level (the comparator operates); when the clock signal is at a low level, the latch circuit is in a set state, and the enable signal is at a high level (the comparator does not operate).

Therefore, the comparator in the embodiment meets the basic precision requirement of the comparator by arranging the pre-amplifying circuit to comprise at least two cascaded operational amplifiers; meanwhile, the operational amplifiers are arranged to respectively comprise a tail current source and a tail current source switch which are connected with a high-level output end of the driving power supply, so that the comparator has a static mode that the tail current source switch is conducted, the operational amplifiers continuously amplify input signals and a dynamic mode that the tail current source switch is controlled by periodic switch signals, namely, the working state of the comparator can be configured, and then the comparator can be configured to be in the static mode in a disorder elimination stage and a sampling stage, so that the comparison precision is ensured, and the comparator is configured to be in the dynamic mode in a successive progressive comparison stage, so that the power consumption of the comparator is reduced, and the effects of high speed, high precision and low power consumption are achieved.

Fig. 3 shows a schematic structural diagram of a comparator according to another embodiment of the present embodiment. As shown in fig. 3, in addition to the pre-amplification circuit and the latch circuit, offset cancellation capacitors are connected in series between adjacent operational amplifiers in the large circuit (in fig. 3, the pre-amplification circuit includes three operational amplifiers, which are, in turn, a first amplifier OP1, a second amplifier OP2, and a third amplifier OP3, for example, an offset cancellation capacitor is connected in series between the first amplifier OP1 and the second amplifier OP2, and an offset cancellation capacitor is connected in series between the second amplifier OP2 and the third amplifier OP 3); two input ends of a first-stage operational amplifier (OP 1) in the pre-amplification circuit are respectively connected with a pair of first switches (offset _ Vcm), and the other ends of the first switches are connected with the output end of a common-mode voltage (Vcm); two output ends of a first-stage operational amplifier (OP 1) in the pre-amplification circuit are respectively connected with a pair of second switches (offset _ clk), and the other ends of the second switches are connected with the output end of a common-mode voltage (Vcm); a pair of third switches (offset 2 for the second amplifier OP2 and offset3 for the third amplifier) are respectively connected between the non-inverting input terminal and the inverting output terminal, and between the inverting input terminal and the non-inverting output terminal of the other operational amplifiers in the pre-amplification circuit.

The circuit structure in this embodiment is used to eliminate the offset that is present in the prevention large circuit, specifically, the offset elimination is performed in a state where the first switch offset _ Vcm is turned on and the input terminal of the first amplifier OP1 is short-circuited; meanwhile, considering that the common mode voltage Vcm is applied to the first switch offset _ Vcm, which may affect the input voltage of the comparator (especially, when the comparator is applied to an analog-to-digital converter, and the input end of the comparator is connected to a capacitor array, the common mode voltage Vcm may generate a charging and discharging process to the capacitor array, and the input voltage jumps), the offset cancellation is performed after the first switch offset _ Vcm is turned on and the voltage between the two input ends of the comparator is stabilized to the common mode voltage Vcm; in addition, in order to prevent the voltage jump between the input terminals of the first amplifier OP1 from affecting the first amplifier OP1, the second switch offset _ clk is kept on during the voltage stabilization process, and is turned off after the voltage between the two input terminals of the comparator is stabilized to the common mode voltage Vcm, so as to start the offset cancellation.

Fig. 2 also shows a timing chart of the offset canceling stage of the comparator in this embodiment mode. As shown in fig. 2, in the offset cancellation stage, the first switch offset _ Vcm and the second switch offset _ clk are first kept on at a high level until the voltage at the input end of the comparator is stabilized to the common mode voltage Vcm, and the second switch offset _ clk is turned off (turned off at a low level); during the offset cancellation process, the third switches offset2 and offset3 are both turned on. In addition, in order to sufficiently cancel the offset of the second amplifier OP2, as shown in fig. 2, the off time of offset2 may be set slightly earlier than offset3.

Thus, the comparator in the present embodiment can perform sufficiently effective offset cancellation, and has high accuracy.

Fig. 4 shows an equivalent circuit diagram of the first-stage operational amplifier (i.e., the first amplifier OP 1) according to an embodiment of the present invention. As shown in fig. 4, it includes:

the drain of the PMOS transistor QP1 is connected to the high level output terminal VDD of the driving power supply, and the gate thereof is connected to the output terminal Bias1 of the first Bias voltage. The PMOS transistor QP1 is the tail current source in the above embodiment.

And the drain electrode of the PMOS tube QP2 is connected with the source electrode of the PMOS tube QP1, and the grid electrode of the PMOS tube QP2 is connected with the enable switch signal enable. The PMOS transistor QP2 is the tail current source switch described in the above embodiment, and the enable switch signal enable is the periodic switch signal described in the above embodiment. Fig. 2 also shows an operation timing diagram of the enable switch signal enable, which is shown in fig. 2 and is at a low level when the comparator is in the offset cancellation phase and the sampling phase, and the PMOS transistor QP2 is turned on; it is corresponding to the working state signal of the latch circuit (i.e. the system clock signal clk) when the comparator is in the successive comparison stage: when the latch circuit is in a reset state (the system clock signal clk is at a high level), the enable switch signal enable is at a low level, the PMOS transistor QP2 is turned on, the comparator operates (amplifies the input signal), when the latch circuit is in a set state (the system clock signal clk is at a low level), the enable switch signal enable is at a high level, the PMOS transistor QP2 is turned off, and the comparator does not operate (the pre-amplification circuit latches the amplified input signal).

The drain electrodes of the PMOS tube QP3 and the PMOS tube QP4 are connected with the source electrode of the PMOS tube QP2, the grid electrode of the PMOS tube QP3 is connected to the positive phase input end Vip, and the grid electrode of the PMOS tube QP4 is connected to the negative phase input end Vin.

The grid electrodes of the PMOS tube QP5 and the PMOS tube QP6 are connected with the output end Bias2 of the second Bias voltage; the drain electrode of the PMOS tube QP5 is connected with the source electrode of the PMOS tube QP3, and the source electrode of the PMOS tube QP5 is connected with the inverted output end Von; the drain electrode of the PMOS pipe QP6 is connected with the source electrode of the PMOS pipe QP4, and the source electrode of the PMOS pipe QP6 is connected with the positive phase output end Vop. The PMOS pipe QP5 and the PMOS pipe QP6 isolate input and output, the influence of feedback on the input can be reduced, and the precision of the comparator is further improved.

The source electrodes of the NMOS tube QN1 and the NMOS tube QN2 are connected with a low-level output end VSS of the driving power supply, the grid electrode and the drain electrode of the NMOS tube QN1 and the drain electrode of the NMOS tube QN2 are connected with an inverted output end Von, and the grid electrode of the NMOS tube QN2 is connected with a positive output end Vop. The gain of the first amplifier OP1 in this embodiment can be controlled by the sizes of the NMOS transistor QN1 and the NMOS transistor QN2, and when the transconductance difference between the NMOS transistor QN1 and the NMOS transistor QN2 decreases, the gain of the first amplifier OP1 increases.

The NMOS transistor QN3 and the NMOS transistor QN4 have source electrodes connected to a low level output terminal VSS of the driving power supply, a gate electrode and a drain electrode of the NMOS transistor QN3 and a drain electrode of the NMOS transistor QN4 are connected to a positive phase output terminal Vop, and a gate electrode of the NMOS transistor QN4 is connected to a negative phase output terminal Von. In this embodiment, gm values of the NMOS tubes QN1 and QN2 are greater than gm values of the NMOS tubes QN3 and QN4, so that negative feedback of the first amplifier OP1 is greater than positive feedback.

If the pre-amplifying circuit is a three-stage operational amplifier including the first amplifier OP1, the second amplifier OP2 and the third amplifier OP3 as described in the above embodiments, the circuit structure of the second amplifier OP2 may be the same as that of the first amplifier OP1, and the third amplifier OP3 is not a main source of noise, so that the PMOS transistor QP5 and the PMOS transistor QP6 may not be required to be disposed relative to the circuit structure of the first amplifier OP 1. Fig. 5 shows an equivalent circuit diagram of the third amplifier OP3 in the present embodiment, which includes, as shown in fig. 5:

the drain of the PMOS transistor QP7 is connected to the high level output terminal VDD of the driving power supply, and the gate thereof is connected to the output terminal Bias1 of the first Bias voltage.

And the drain electrode of the PMOS pipe QP8 is connected with the source electrode of the PMOS pipe QP7, and the grid electrode of the PMOS pipe QP8 is connected with the enable switch signal enable.

The drain electrodes of the PMOS tube QP9 and the PMOS tube QP10 are both connected with the source electrode of the PMOS tube QP8, the grid electrode of the PMOS tube QP9 is connected to the positive phase input end Vip, and the grid electrode of the PMOS tube QP10 is connected to the negative phase input end Vin.

The NMOS transistor QN6 and the NMOS transistor QN7 have source electrodes connected to a low level output terminal VSS of the driving power supply, a gate electrode and a drain electrode of the NMOS transistor QN6 and a drain electrode of the NMOS transistor QN7 are connected to a reverse phase output terminal Von, and a gate electrode of the NMOS transistor QN7 is connected to a normal phase output terminal Vop.

Fig. 6 shows an equivalent circuit diagram of the first-stage operational amplifier (i.e., the first amplifier OP 1) according to another embodiment of the present invention. As shown in fig. 6, in addition to the circuit configuration included in the first amplifier OP1 (shown in fig. 4) in the above embodiment, it further includes:

the drain of the NMOS transistor QN5 is connected to the positive phase output terminal Vop, the source thereof is connected to the negative phase output terminal Von, and the gate thereof is connected to the pulse control signal RST. Fig. 2 also shows an operation timing diagram of the pulse control signal RST, and as shown in fig. 2, the pulse control signal RST rises to a high level at a rising edge of each successive comparison period (i.e., each system clock clk period), so as to control the NMOS transistor QN5 to be turned on, and eliminate the memory effect of the first amplifier OP1, so that the first amplifier OP1 can be reset quickly, and the operation rate of the comparator is increased.

Fig. 7 shows an equivalent circuit diagram of the corresponding third amplifier OP3, which further includes, as shown in fig. 7, with respect to the third amplifier OP3 (shown in fig. 5) in the above embodiment:

Fig. 8 shows an equivalent circuit diagram of the latch circuit of one embodiment in this embodiment. As shown in fig. 8, it includes:

the drain electrodes of the PMOS tube QP11 and the PMOS tube QP12 are connected with a high-level output end VDD of the driving power supply, the grid electrode of the PMOS tube QP11 is connected with an inverted signal clk _ D of the clock signal clk, the source electrode of the PMOS tube QP11 and the source electrode of the PMOS tube QP12 are connected with an inverted output end Von, and the grid electrode of the PMOS tube QP12 is connected with a non-inverted output end Vop.

Drain electrodes of the PMOS transistor QP13 and the PMOS transistor QP14 are connected to a high-level output end VDD of the driving power supply, a gate electrode of the PMOS transistor QP13 is connected to an inverted signal clk _ D of the clock signal clk, a source electrode of the PMOS transistor QP13 and a source electrode of the PMOS transistor QP14 are connected to a non-inverted output end Vop, and a gate electrode of the PMOS transistor QP14 is connected to an inverted output end Von.

The gates of the NMOS transistor QN11 and the NMOS transistor QN12 are both connected to the inverted signal clk _ D of the clock signal clk, the drain of the NMOS transistor QN11 is connected to the inverted output terminal Von, and the drain of the NMOS transistor QN12 is connected to the non-inverted output terminal Vop.

The source electrodes of the NMOS tube QN13, the NMOS tube QN14, the NMOS tube QN15 and the NMOS tube QN16 are connected with a low-level output end VSS of a driving power supply, the grid electrode of the NMOS tube QN13 is connected with a positive phase input end Vip, the grid electrode of the NMOS tube QN15 is connected with a negative phase input end Vin, the drain electrode of the NMOS tube QN13, the drain electrode of the NMOS tube QN14 and the grid electrode of the NMOS tube QN16 are connected with the source electrode of the NMOS tube QN11, and the grid electrode of the NMOS tube QN14, the drain electrode of the NMOS tube QN15 and the drain electrode of the NMOS tube QN16 are connected with the source electrode of the NMOS tube QN 12.

Fig. 9 shows a flow chart of a method of controlling the comparator shown in fig. 1-8 in the present embodiment. As shown in fig. 9, the method may include:

step S100: when the comparator performs offset cancellation and sampling, a first predetermined voltage is applied to the tail current source switch to turn on the tail current source switch.

Step S200: when the comparator performs successive progressive comparison and the latch circuit is in a reset state, a first predetermined voltage is applied to the tail current source switch to turn on the tail current source switch.

Step S300: and when the comparator performs successive progressive comparison and the latch circuit is in a set state, applying a second preset voltage to the tail current source switch to turn off the tail current source switch.

Example 2

The embodiment discloses an analog-to-digital converter, which comprises: a capacitor array, a comparator as described in any of the embodiments 1 above, and a successive approximation logic circuit.

It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications therefrom are intended to be within the scope of the invention.

Claims

1. A comparator, comprising:

the operational amplifier comprises a tail current source and a tail current source switch which are connected with a high-level output end of the driving power supply, the operational amplifier is provided with the tail current source switch which is conducted, the operational amplifier continuously amplifies an input signal, the comparator is in a first state of a static comparator, the tail current source switch is controlled by a periodic switch signal, and the comparator is in a second state of a dynamic comparator.

2. The comparator according to claim 1,

offset elimination capacitors are connected in series between adjacent operational amplifiers;

two input ends of a first-stage operational amplifier in the pre-amplification circuit are respectively connected with a pair of first switches, and the other ends of the first switches are connected with an output end of a common-mode voltage;

two output ends of the first-stage operational amplifier in the pre-amplification circuit are respectively connected with a pair of second switches, and the other ends of the second switches are connected with the output end of the common-mode voltage;

a pair of third switches is respectively connected between the positive phase input end and the negative phase output end of other operational amplifiers in the pre-amplifying circuit, and between the negative phase input end and the positive phase output end;

the offset elimination of the comparator is carried out by switching off the second switch after the first switch and the second switch are switched on and the voltage between the two input ends of the comparator is stabilized to the common-mode voltage.

3. The comparator according to claim 1 or 2, wherein the pre-amplifying circuit comprises three stages of operational amplifiers, namely a first amplifier, a second amplifier and a third amplifier, the first amplifier and the second amplifier are identical in structure, and the first amplifier comprises:

a drain electrode of the PMOS tube QP1 is connected with a high-level output end VDD of the driving power supply, and a grid electrode of the PMOS tube QP1 is connected with an output end Bias1 of a first Bias voltage;

drain electrodes of the PMOS tube QP3 and the PMOS tube QP4 are connected with a source electrode of the PMOS tube QP2, a grid electrode of the PMOS tube QP3 is connected to the positive phase input end Vip, and a grid electrode of the PMOS tube QP4 is connected to the negative phase input end Vin;

the grid electrodes of the PMOS tube QP5 and the PMOS tube QP6 are connected with the output end Bias2 of the second Bias voltage; the drain electrode of the PMOS tube QP5 is connected with the source electrode of the PMOS tube QP3, and the source electrode of the PMOS tube QP5 is connected with the inverted output end Von; the drain electrode of the PMOS tube QP6 is connected with the source electrode of the PMOS tube QP4, and the source electrode of the PMOS tube QP6 is connected with the positive phase output end Vop;

the source electrodes of the NMOS tube QN1 and the NMOS tube QN2 are connected with a low-level output end VSS of the driving power supply, the grid electrode and the drain electrode of the NMOS tube QN1 and the drain electrode of the NMOS tube QN2 are connected with the inverted output end Von, and the grid electrode of the NMOS tube QN2 is connected with the positive output end Vop;

the source electrodes of the NMOS tube QN3 and the NMOS tube QN4 are connected with the low-level output end VSS of the driving power supply, the grid electrode and the drain electrode of the NMOS tube QN3 and the drain electrode of the NMOS tube QN4 are connected with the positive phase output end Vop, and the grid electrode of the NMOS tube QN4 is connected with the negative phase output end Von.

4. The comparator as claimed in claim 3, wherein gm values of the NMOS transistors QN1 and QN2 are greater than gm values of the NMOS transistors QN3 and QN 4.

5. The comparator of claim 3, wherein the first amplifier further comprises:

and the drain electrode of the NMOS tube QN5 is connected with the positive phase output end Vop, the source electrode of the NMOS tube QN is connected with the negative phase output end Von, and the grid electrode of the NMOS tube QN is connected with a pulse control signal RST.

6. The comparator of claim 3, wherein the third amplifier comprises:

a PMOS tube QP7, the drain of which is connected with the high-level output end VDD of the driving power supply, and the gate of which is connected with the output end Bias1 of the first Bias voltage;

drain electrodes of the PMOS tube QP9 and the PMOS tube QP10 are connected with a source electrode of the PMOS tube QP8, a grid electrode of the PMOS tube QP9 is connected to the positive phase input end Vip, and a grid electrode of the PMOS tube QP10 is connected to the negative phase input end Vin;

the source electrodes of the NMOS tube QN6 and the NMOS tube QN7 are connected with the low-level output end VSS of the driving power supply, the grid electrode and the drain electrode of the NMOS tube QN6 and the drain electrode of the NMOS tube QN7 are connected with the reverse phase output end Von, and the grid electrode of the NMOS tube QN7 is connected with the normal phase output end Vop;

the source electrodes of the NMOS tube QN8 and the NMOS tube QN9 are connected with a low-level output end VSS of the driving power supply, the grid electrode and the drain electrode of the NMOS tube QN8 and the drain electrode of the NMOS tube QN9 are connected with the positive phase output end Vop, and the grid electrode of the NMOS tube QN9 is connected with the negative phase output end Von.

7. The comparator of claim 6 wherein the third amplifier further comprises

And the drain electrode of the NMOS tube QN10 is connected with the positive phase output end Vop, the source electrode is connected with the negative phase output end Von, and the grid electrode is connected with a pulse control signal RST.

8. An analog-to-digital converter, comprising:

a capacitor array;

a comparator as claimed in any one of claims 1 to 7;

successive approximation logic.

9. A method of controlling the comparator of any one of claims 1-7, comprising:

when the comparator carries out offset cancellation and sampling, a first preset voltage is applied to the tail current source switch so as to enable the tail current source switch to be conducted;

when the comparator carries out successive progressive comparison and the latch circuit is in a reset state, the first preset voltage is applied to the tail current source switch so as to enable the tail current source switch to be conducted;

and when the comparator carries out successive progressive comparison and the latch circuit is in a set state, applying a second preset voltage on the tail current source switch to turn off the tail current source switch.