CN115241179A - Chip packaging structure - Google Patents

Chip packaging structure Download PDF

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Publication number
CN115241179A
CN115241179A CN202210931101.5A CN202210931101A CN115241179A CN 115241179 A CN115241179 A CN 115241179A CN 202210931101 A CN202210931101 A CN 202210931101A CN 115241179 A CN115241179 A CN 115241179A
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China
Prior art keywords
chip
connection side
flip
package structure
bonded
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Pending
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CN202210931101.5A
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Chinese (zh)
Inventor
雷永庆
冯军
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Mestar Microelectronics Shenzhen Co ltd
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Mestar Microelectronics Shenzhen Co ltd
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Priority to CN202210931101.5A priority Critical patent/CN115241179A/en
Publication of CN115241179A publication Critical patent/CN115241179A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H01L2021/60007—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process
    • H01L2021/60022—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process using bump connectors, e.g. for flip chip mounting
    • H01L2021/60037—Right-up bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

The application discloses chip packaging structure, it includes: a substrate having a connection side and a conductive side for electrically connecting the chip package structure with an external circuit; at least one chip set, the chip set including a control chip and a device chip; wherein the control chip and the device chip are flip-chip bonded, and the control chip or the device chip is flip-chip bonded to the connection side; or the control chip and the device chip are in flip-chip bonding with the connecting side without using wire bonding in the prior art, so that the whole thickness of the chip packaging structure is only determined by the thicknesses of the substrate, the control chip and the device chip, and the whole thickness of the chip packaging structure is reduced.

Description

Chip packaging structure
Technical Field
The application relates to the field of chip packaging, in particular to a chip packaging structure.
Background
In the conventional chip package structure, a chip is bonded to a lead frame. Both the chip and the lead frame have a large number of conductive contacts. The conductive contacts on the chip are in lead bonding with the corresponding conductive contacts on the lead frame, and then the conductive contacts are transmitted to the outer side of the chip packaging body through a preset electric signal transmission path on the lead frame, so that the direct electric signal transmission from the outer side of the chip packaging body to the crystal grains in the chip packaging body is completed.
Wire bonding is the use of gold wire (or copper wire, aluminum wire) to connect the conductive contacts of the chip to the lead frame. During wire bonding, a gold ball is formed on the bottom of the gold wire. The gold ball is then pressed onto the chip contacts and then soldered to the contacts by applying pressure or changing temperature, which forms a dot on the contact, and the gold wire is then pulled up and moved over the lead frame to complete the bonding.
Because the gold thread is the state setting of buckling between chip and lead frame to buckle in the chip top, thereby cause the thickness of the back chip architecture of encapsulation to be the distance between bottom surface and the gold thread peak of lead frame, so lead to the chip thickness of the back of encapsulation thick, be unfavorable for the frivolousization of chip.
Disclosure of Invention
The technical problem to be solved in the application is to provide a chip packaging structure, which can make the thickness of a packaged chip smaller.
In order to solve the technical problem, the technical scheme adopted by the application is as follows:
a chip package structure, comprising:
a substrate having a connection side and a conductive side for electrically connecting the chip package structure with an external circuit;
at least one chipset comprising a control chip and a device chip;
wherein the control chip and the device chip are flip-chip bonded, and the control chip or the device chip is flip-chip bonded to the connection side;
or the control chip and the device chip are in flip-chip bonding with the connecting side.
According to an embodiment of the present application, the connection side protrusion is provided with a stopper protrusion adjacent to the chip set.
According to an embodiment of the present application, the stop protrusions are symmetrically disposed at the connection side, the chip set is disposed between the stop protrusions, and a gap is formed between the stop protrusions and the chip set.
According to an embodiment of the present application; the stop protrusion is configured as a bezel surrounding the chip set.
According to an embodiment of the present application, the substrate further includes a side end surface connected to the connection side, and the stopper protrusion is flush with the side end surface at an outer side surface away from the chip group.
According to an embodiment of the present application, the thickness of the stop protrusion is not less than half of the minimum thickness of the chip set.
According to an embodiment of the present application, the substrate is further provided with a hole portion configured as a blind hole opened to the connection side, or a through hole penetrating the connection side and the conductive side.
According to an embodiment of the present application, the control chip or the device chip facing the connection side in each of the chip groups is accommodated in the hole portion.
According to an embodiment of the present application, the control chip is flip-chip bonded to the connection side, the device chip is flip-chip bonded to a side of the control chip facing the connection side, and the device chip is accommodated in the hole portion.
According to an embodiment of the present application, the control chip is flip-chip bonded to the connection side, and the device chip is flip-chip bonded to a side of the control chip away from the connection side.
The beneficial effect of this application is: according to the chip packaging structure, the control chip and the device chip in the chip group are in flip-chip welding, and the control chip or the device chip and the connecting side are in flip-chip welding; or, the control chip and the device chip are both in flip-chip bonding with the connecting side without using the lead bonding in the prior art, so that the lead in the prior art can be eliminated, the whole thickness of the chip packaging structure is only determined by the thicknesses of the substrate, the control chip and the device chip, and the whole thickness of the chip packaging structure is compressed to conform to the development trend of chip lightening and thinning.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without inventive efforts, wherein:
fig. 1 is a schematic structural diagram of a first embodiment of a chip package structure provided in the present application;
fig. 2 is a schematic structural diagram of a second embodiment of a chip package structure provided in the present application;
fig. 3 is a schematic structural diagram of a third embodiment of a chip package structure provided in the present application;
fig. 4 is a schematic structural diagram of a fourth embodiment of a chip package structure provided in the present application;
fig. 5 is a schematic structural diagram of a fifth embodiment of a chip package structure provided in the present application;
fig. 6 is a bottom view of the chip package structure of fig. 5.
Detailed Description
The technical solutions in the embodiments of the present application will be described clearly and completely with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only some embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.
CMOS is an abbreviation for Complementary Metal Oxide Semiconductor (CMOS) and refers to a technology used to fabricate large scale integrated circuit chips or chips fabricated using such a technology.
MEMS is an abbreviation for Micro-Electro-Mechanical systems (MEMS), also known as Micro-Electro-Mechanical systems, microsystems, micromachines, and the like.
Referring to fig. 1 to 4, fig. 1 is a schematic structural diagram of a chip package structure according to a first embodiment of the present disclosure; fig. 2 to fig. 4 are specific embodiments of the chip package structure provided in the present application. In an aspect of the present application, a chip package structure 100 is provided, where the chip package structure 100 includes a substrate 10 and at least one chip group 11 disposed on the substrate 10. The number of the chip sets 11 may be multiple, and may be selected according to actual requirements.
The substrate 10 has a connection side 10a and a conductive side 10b for electrically connecting the chip package 100 to an external circuit. Conductive side 10b and connecting side 10a are disposed opposite to each other with a gap therebetween, but conductive side 10b and connecting side 10a may be disposed adjacent to each other. The connection side 10a is used for connection to the chipset 11. It is understood that the substrate 10 may be used to carry the chip set 11, and may be a PCB or a silicon substrate, which is not limited herein.
The Chip set 11 includes a control Chip 12 (CMOS Chip) and a device Chip 13 (MEMS Chip), wherein the control Chip 12 and the device Chip 13 are Flip Chip bonded, and the control Chip 12 is Flip Chip bonded to the connection side 10 a.
In the chip package structure 100 provided in the present application, the device chip 13 may be flip-chip bonded to the connection side 10 a; alternatively, the control chip 12 and the device chip 13 are both flip-chip bonded to the connection side 10 a. While fig. 2 to fig. 6 only show some embodiments of the chip package structure 100 provided in the present application, specifically, only some embodiments of the control chip 12 flip-chip bonded to the connection side 10a, the purpose of which is to take the control chip 12 flip-chip bonded to the connection side 10a as an example, so as to intuitively teach the specific structure of the chip package structure 100 provided in the present application in this case. These drawings should not be taken as limiting the scope of protection of the present application.
It is understood that, when the chip set 11 includes a plurality of device chips 13 and a control chip 12, in one embodiment, the plurality of device chips 13 may be stacked and bonded to form an integrated device chip set; a plurality of control chips 12 are stacked and welded to form a control chip group; and then the outermost device chip 13 of the device chip group and the outermost control chip 12 of the control chip group are subjected to flip chip bonding. In another embodiment, a plurality of device chips 13 and control chips 12 may be tiled.
Thus, the control chip 12 and the device chip 13 in the chip package structure 100 of the present application are flip-chip bonded, and the device chip 13 and/or the control chip 12 and the substrate 10 are also flip-chip bonded, so that the device chip 13 and/or the control chip 12 are bonded on the connection side 10a and electrically connected to the substrate 10. Thus, the device chip 13 and/or the control chip 12 can be electrically connected to an external circuit by electrically connecting the conductive side 10b of the substrate 10 to the external circuit. Therefore, the device chip 13 and/or the control chip 12 and the substrate 10 in the chip package structure 100 of the present application only need to be flip-chip bonded, and no wire bonding in the prior art is used, so that the wire bonding in the prior art can be eliminated, the overall thickness of the chip package structure 100 is determined only by the thicknesses of the substrate 10, the control chip 12 and the device chip 13, and the overall thickness of the chip package structure 100 is reduced to comply with the development trend of chip thinning.
Referring to fig. 1, in the first embodiment, a chip package structure 100 includes a group of chip sets 11, where the chip sets 11 include a control chip 12 and a device chip 13. The control chip 12 is flip-chip bonded to the connection side 10a of the substrate 10. The device chip 13 is flip-chip bonded to the control chip 12 and bonded to a side remote from the connection side 10 a. Flip chip bonding can achieve electrical and mechanical connections between connectors through the solder joint 14 connections. The device chip 13 and the substrate 10 are respectively arranged on two sides of the control chip 12, so that various limitations imposed on the device chip 13 by the substrate 10 can be avoided, the difficulty in optimizing the size and the structure of the device chip 13 is reduced, and the optimization space of the device chip is improved.
The substrate 10 further includes a side end surface 10c connected to the connection side 10a, and the side end surface 10c is used to define the size of the connection side 10 a. In order to protect the chip better, when the chip set 11 is flip-chip bonded to the connection side 10a of the substrate 10, the side end of the chip set 11 does not exceed the space defined by the plane of the side end surface 10c, and the size of the chip packaging structure 100 can be further compressed transversely, so that the optimized space is increased.
It should be noted that the side end of the chipset 11 does not exceed the space defined by the plane where the side end face 10c is located, and the following conditions are mainly included:
the projection of the control chip 12 on the device chip 13 covers the device chip 13, and the projection of the control chip 12 on the connection side 10a is within the connection side 10 a. That is, the periphery of the control chip 12 is equal to or less than the periphery of the connection side 10a, and the periphery of the device chip 13 is equal to or less than the periphery of the device chip 13. For example, the periphery of the control chip 12 is wider than the device chip 13, and the control chip 12 is flush with the side end face 10c of the substrate 10.
The projection of the control chip 12 on the device chip 13 is within the device chip 13 and the projection of the device chip 13 on the connection side 10a is within the connection side 10 a. That is, the periphery of the device chip 13 is smaller than the periphery of the connection side 10a, and the periphery of the control chip 12 is smaller than the periphery of the control chip 12.
It is understood that in other embodiments, the present application provides the chip package structure 100 when the device chip 13 is flip-chip bonded to the connection side 10 a; or, when both the control chip 12 and the device chip 13 are flip-chip bonded to the connection side 10 a; there are also various dimensional relationships between the chip set 11 and the substrate 10 as described above.
Specifically, in some specific embodiments, as shown in fig. 1, the substrate 10 is further provided with a hole portion 10d, and more specifically, the hole portion 10d is a through hole, that is, the hole portion 10d penetrates not only the connection side 10a but also the conductive side 10b disposed opposite to the connection side 10 a. The hole 10d is configured as a through hole and serves the purpose of dissipating heat from the chip set 11.
In order to prevent the solder from leaking from the hole portion 10d to the conductive side 10b to cause a short circuit problem when the control chip 12 and/or the device chip 13 are soldered to the substrate 10, the hole portion 10d may also be configured as a blind hole, that is, the hole portion 10d penetrates the connection side 10a and extends to the conductive side 10b, but does not penetrate the conductive side 10b. Preferably, the hole 10d is provided at a position corresponding to the position of the device chip 13, and the provision of the hole 10d does not interfere with flip-chip bonding of the chip to the connection side 10 a.
It is understood that in other embodiments, the present application provides the chip package structure 100 when the device chip 13 is flip-chip bonded to the connection side 10 a; alternatively, both the control chip 12 and the device chip 13 are flip-chip bonded to the connection side 10 a; alternatively, when the plurality of chip groups 11 are flip-chip bonded on the connection side 10 a; the substrate 10 may be provided with the hole 10d having the same structure as described above so as to correspond to the chip for heat dissipation.
Referring to fig. 2, fig. 2 is a schematic structural diagram of a second embodiment of a chip package structure 100 provided in the present application. In order to further protect the chip set 11 flip-chip bonded on the connection side 10a of the substrate 10 from impact, the chip package structure 100 provided by the present application further includes other protection structures disposed on the substrate 10 in addition to the structure in the first embodiment described above in the second embodiment.
Specifically, the substrate 10 further includes a stopper projection 15 provided protrudingly on the connection side 10a, wherein in one configuration, the stopper projection 15 is provided along a symmetrical position on the connection side 10a and surrounds the chip group 11 therein. The stopper projection 15 has a clearance from the side end of the chip group 11 to facilitate connection of the chip group 11 to the connection side 10 a. The stopper projection 15 surrounding the chip group 11 prevents the chip from being hit by other components and prevents the harmful material from entering from the side. In addition, when flip-chip bonding the chip group 11 to the connection side 10a of the substrate 10, solder is deposited after encountering the stopper convex portion 15, so that the problem of cold joint can also be avoided.
Specifically, in some specific embodiments, the stopping protrusions 15 are disposed along symmetrical positions on the connecting side 10a, and may be a pair of symmetrical stopping protrusions 15, or a plurality of pairs of symmetrical stopping protrusions 15, where the plurality of pairs of stopping protrusions 15 surround the side of the connecting side 10 a. The pair of stop protrusions 15 and the plurality of pairs of stop protrusions 15 may be spaced apart to form a non-closed loop configuration.
In other embodiments, the stop protrusion 15 may form an end-to-end frame that surrounds the sides of the connecting side 10 a. The arrangement of the stop protrusion 15 can be selected according to actual conditions, and the frame can be rectangular, circular, oval, and the like, which is not limited in this respect.
In some more specific embodiments, the stop boss 15 is located on the same plane as the side end face 10c on the outer side facing away from the chip set 11 component. That is, the outer side surface of the stopper projection 15 is flush with the side end surface 10c of the base plate 10.
As shown in fig. 2, the control chip 12 is flip-chip bonded to the connection side 10a of the substrate 10. The device chip 13 is flip-chip bonded to the control chip 12 and bonded to a side away from the connection side 10 a. Flip chip bonding can achieve electrical and mechanical connections between connectors through the solder joint 14 connections. The stop projection 15 is configured as a rectangular frame, and the stop projection 15 is projected from the connection side 10a and surrounds the control chip 12. A gap is left between the outer side surface of the control chip 12 and the inner side surface of the stopper protrusion 15, so that the control chip 12 can radiate heat. The outer side surface of the stopper projection 15 is flush with the side end surface 10c of the substrate 10.
The stopper projection 15 protects the control chip 12, and prevents the harmful material from contacting the control chip 12 from the side or the harmful material from striking the control chip 12. In addition, when the control chip 12 is soldered to the connection side 10a of the substrate 10, solder is deposited after encountering the stopper convex portion 15, so that the problem of cold joint can be avoided.
It is understood that, in order to achieve better protection of the stopper projection 15, the stopper projection 15 needs to have a certain thickness in the projection direction, and specifically, for example, the thickness of the stopper projection 15 is not less than one-half of the minimum thickness in the chip group 11, or not less than one-half of the thickness of a chip flip-chip bonded to the connection side 10 a. For example, the chip set 11 includes a control chip 12 and a device chip 13 flip-chip bonded to each other, the control chip 12 is flip-chip bonded to the connection side 10a, and the thickness of the stopper projection 15 is preferably equal to the thickness of the control chip 12.
It is understood that in other embodiments, the present application provides the chip package structure 100 when the device chip 13 is flip-chip bonded to the connection side 10 a; alternatively, both the control chip 12 and the device chip 13 are flip-chip bonded to the connection side 10 a. At this time, the thickness of the stopper projection 15 in the projection direction is not less than one-half of the device chip 13, and is preferably equal to the thickness of the device chip 13; or the thickness of the stop projection 15 in the projection direction is at least not less than the average thickness of the tiled chips, preferably equal to the maximum thickness of the tiled chips. When the stopper projection 15 is provided on the connection side 10a, a certain gap is provided between the stopper projection 15 and the outer side surface of the chip directly flip-chip bonded to the connection side 10a, and the size of the stacked chips is related to the thickness of the stopper projection 15. For example, in fig. 2, the thickness of the stop protrusion 15 is equal to that of the control chip 12, and the periphery of the device chip 13 may be smaller than that of the control chip 12, or may be greater than or equal to that of the control chip 12.
Referring to fig. 3-5, in the third embodiment, the control chip 12 is flip-chip bonded to the connection side 10a, the device chip 13 is flip-chip bonded to the control chip 12, and the device chip 13 is flip-chip bonded to a side of the control chip 12 facing the substrate 10. I.e., the substrate 10 is co-located on the same side of the control chip 12 as the device chip 13. Otherwise, the chip package structure 100 in the third embodiment provided by the present application is the same as the chip package structure 100 in the first embodiment described above.
In order to further reduce the thickness of the chip package structure 100. In the third embodiment, the device chip 13 is accommodated in the hole portion 10 d. Specifically, the device chip 13 is placed in the hole portion 10d with a gap between the outer side surface of the device chip 13 and the inner side surface of the hole portion 10d, and the device chip 13 accommodated in the hole portion 10d does not exceed the plane defined by the conductive side 10b.
Thus, the overall thickness of the chip package structure 100 may be determined only by the thickness of the substrate 10 and the thickness of the control chip 12, that is, the overall thickness of the chip package structure 100 is the sum of the thickness of the substrate 10 and the thickness of the control chip 12, thereby further compressing the overall thickness of the chip package structure 100. In addition, because the substrate 10 and the device chip 13 are located on the same side of the control chip 12, the flip chip bonding can be performed on one side of the control chip 12, which can effectively reduce the difficulty of the processing technology of the control chip 12, avoid the complex technology of double-sided electrical conduction for the control chip 12, and reduce the manufacturing cost of the control chip 12.
It is understood that in other embodiments, the present application provides the chip package structure 100 when the device chip 13 is flip-chip bonded to the connection side 10 a; the control chip 12 can be accommodated in the hole portion 10 d; or each chip group 11 may receive a plurality of chips in the hole portion 10d according to the depth of the hole portion 10 d. That is, after the chip for connection in each chip group 11 is connected to the connection side 10a, the control chip 12 and/or the device chip 13 disposed at the side of the connection chip and facing the substrate 10 may be accommodated in the hole portion 10d, thereby further reducing the overall thickness of the chip package structure 100.
Referring to fig. 4 and 5, the fourth embodiment is different from the third embodiment in that a stop protrusion 15 is protruded on the connection side 10 a. Wherein the stop protrusion 15 is provided as in the second embodiment. Therefore, the protection of the chip in the chip set 11 by the stopping protrusion 15 can be realized, the accommodating function of the hole portion 10d can be achieved to further reduce the thickness of the chip packaging structure 100, and the heat dissipation can be performed by using the hole portion 10 d.
It is understood that in other embodiments, the present application provides the chip package structure 100 when the device chip 13 is flip-chip bonded to the connection side 10 a; alternatively, both the control chip 12 and the device chip 13 are flip-chip bonded to the connection side 10 a; alternatively, when the plurality of chip groups 11 are flip-chip bonded on the connection side 10 a; the substrate 10 may be provided with the same structure as described above corresponding to the chip, and the characteristics and advantages of the flip chip bonding, the stopper projection 15 and the hole 10d may be combined to improve the chip package structure 100.
Referring to fig. 5, in the fifth embodiment, the difference from the fourth embodiment is that the hole 10d may be configured as a blind hole opened on the connection side 10a, that is, the hole 10d penetrates through the connection side 10a and extends to the conductive side 10b, but does not penetrate through the conductive side 10b. Thus, the hole 10d and the conductive side 10b are isolated, and the problem of short circuit caused by solder leaking from the hole 10d to the conductive side 10b when the control chip 12 and/or the device chip 13 are soldered to the substrate 10 can be effectively avoided.
It is understood that in other embodiments, the present application provides the chip package structure 100 when the device chip 13 is flip-chip bonded to the connection side 10 a; alternatively, both the control chip 12 and the device chip 13 are flip-chip bonded to the connection side 10 a; alternatively, when the plurality of chip groups 11 are flip-chip bonded on the connection side 10 a; the substrate 10 may be provided with the same structure as described above to correspond to a chip.
Referring to fig. 6, in some embodiments, substrate 10 is configured as a silicon substrate, and connection side 10a is provided with a first contact (not shown) electrically connected to chipset 11 via flip-chip bonded pad 14. The conductive side 10b is provided with a second contact portion 10e, and the second contact portion 10e is electrically connected to an external circuit. The first contact portion is electrically connected to the second contact portion 10 e.
The first contact and the second contact 10e are electrically connected, and may be implemented by a TSV (Through Silicon Via) method. Thus, the first contact portion and the second contact portion 10e are two connecting ends of the TSV respectively, so that the electrical connection path from the outer side of the substrate 10 to the chip set 11 is shortened, circuit characteristics such as extra parasitic capacitance and feedback resistance introduced by package electrical connection are reduced, and the difficulty in optimizing a circuit system is reduced.
It can be understood that the TSV structures may be correspondingly arranged in a plurality according to the requirements of the actual situation. As shown in fig. 6, 4 TSV structures are arranged in an array.
In some embodiments, the device chip 13 may have a MEMS resonator and a first electrode for receiving a resonator drive signal from the control chip 12 and a second electrode for outputting a resonator sense signal to the control chip 12. The resonator drive signal is used to drive the MEMS resonator for mechanical resonant motion, and the resonator sense signal is indicative of the mechanical resonant motion.
The control chip 12 described above may include circuitry for receiving resonator sense signals from the device chip 13 and generating resonator drive signals based on the resonator sense signals.
The control chip 12 may also include circuitry for generating a clock signal based on the resonator sense signal and compensating the clock signal according to the temperature sensitivity of the MEMS resonator. Wherein the circuit to compensate the clock signal according to the temperature sensitivity of the MEMS resonator comprises a temperature sensor.
In another aspect of the present application, an electronic product is provided, and the electronic product includes the chip package structure 100 according to any of the above embodiments, and details of the chip package structure 100 are not repeated herein.
The terms "first", "second" and "third" in the present application are used for descriptive purposes only and are not to be construed as indicating the number of indicated technical features. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of the feature. In the embodiment of the present application, all directional indicators (such as up, down, left, right, front, rear \8230;) are used only to explain the relative positional relationship between the components, the motion situation, etc. at a specific posture (as shown in the drawing), and if the specific posture is changed, the directional indicator is changed accordingly. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. A process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to the listed steps or elements but may alternatively include additional steps or elements not listed or inherent to such process, method, article, or apparatus.
The above description is only an example of the present application, and is not intended to limit the scope of the present application, and all equivalent structures or equivalent processes performed by the present application and the contents of the attached drawings, which are directly or indirectly applied to other related technical fields, are also included in the scope of the present application.

Claims (10)

1. A chip package structure, comprising:
a substrate having a connection side and a conductive side for electrically connecting the chip package structure with an external circuit;
at least one chipset comprising a control chip and a device chip;
wherein the control chip and the device chip are flip-chip bonded, and the control chip or the device chip is flip-chip bonded to the connection side;
or the control chip and the device chip are in flip chip bonding with the connecting side.
2. The chip package structure according to claim 1, wherein the connection side is provided with a stopper protrusion adjacent to the chip set.
3. The chip package structure according to claim 2, wherein the stop protrusions are symmetrically disposed on the connection side, the chip set is disposed between the stop protrusions, and a gap is formed between the stop protrusions and the chip set.
4. The chip packaging structure according to claim 2, wherein; the stop protrusion is configured as a bezel that surrounds the chip set.
5. The chip package structure according to claim 2, wherein the substrate further includes a side end surface connected to the connection side, and the stopper projection is flush with the side end surface at an outer side surface away from the chip group.
6. The chip package structure according to claim 2, wherein the thickness of the stop protrusion is not less than half of the minimum thickness of the chip set.
7. Chip package according to any one of claims 1 to 6, characterized in that the substrate is further provided with a hole portion configured as a blind hole opening at the connection side or as a through hole passing through the connection side and the electrically conductive side.
8. The chip package structure according to claim 7, wherein the control chip or the device chip facing the connection side in each of the chip groups is accommodated in the hole portion.
9. The chip package structure according to claim 7, wherein the control chip is flip-chip bonded to the connection side, the device chip is flip-chip bonded to a side of the control chip facing the connection side, and the device chip is received in the hole portion.
10. The chip package structure according to any one of claims 1 to 6, wherein the control chip is flip-chip bonded to the connection side, and the device chip is flip-chip bonded to a side of the control chip away from the connection side.
CN202210931101.5A 2022-08-03 2022-08-03 Chip packaging structure Pending CN115241179A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117303305A (en) * 2023-11-29 2023-12-29 麦斯塔微电子(深圳)有限公司 MEMS device packaging structure and preparation method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117303305A (en) * 2023-11-29 2023-12-29 麦斯塔微电子(深圳)有限公司 MEMS device packaging structure and preparation method thereof

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