CN115241122A - Hard mask structure for deep trench etching and process method - Google Patents
Hard mask structure for deep trench etching and process method Download PDFInfo
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- CN115241122A CN115241122A CN202210806630.2A CN202210806630A CN115241122A CN 115241122 A CN115241122 A CN 115241122A CN 202210806630 A CN202210806630 A CN 202210806630A CN 115241122 A CN115241122 A CN 115241122A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
Abstract
The invention discloses a hard mask structure for deep groove etching and a process method based on the structure, wherein the hard mask structure is positioned on a semiconductor substrate, and is used as a barrier layer for the deep groove etching when the deep groove etching is carried out on the semiconductor substrate; the hard mask structure is a composite structure and comprises two layers from the lowest layer covering the semiconductor substrate to the top: a silicon nitride layer at the lowest layer and a silicon oxide layer covering the silicon nitride layer. The structure eliminates the hidden danger that the thermal oxidation layer at the bottommost layer of the traditional ONO structure is corroded transversely, effectively relieves the fusion of monocrystalline silicon on the surface of a hard mask, and solves the problem of dislocation generated by N-type epitaxy to a certain extent.
Description
Technical Field
The invention relates to the field of design and manufacture of semiconductor devices, in particular to a hard mask structure for deep trench etching and a process method.
Background
In the application scenes of super junction devices or deep trench capacitor devices and the like, the etching of the deep trench is a critical or even decisive process. ONO (composite layer of silicon oxide-silicon nitride-silicon oxide) is generally used as a Hard Mask (Hard Mask) layer. In one fabrication scenario, the ONO layer over the N-type epitaxy, the thermal oxide layer of the lowermost layer serves as a stress buffer layer and a ground barrier layer for CMP, and has a thickness of about 1500 a, and the protective layer for the underlying thermal oxide layer has a thickness of about 400 a when the nitride layer of the intermediate layer is removed as an upper oxide layer and the sacrificial oxide layer is removed; the TEOS layer at the topmost layer is used as a mask layer for deep trench etching, and the thickness of the TEOS layer is larger and reaches about 22000A. After the deep trench etching is completed, the remaining Hard Mask needs to be removed by means of a wet etching process, which may cause a portion of the thermal oxide layer at the lowermost layer to be laterally etched (undercut), as shown by an arrow in fig. 1.
During the P-type epitaxial filling, monocrystalline silicon grows in the trench and on the surface of the trench at the same time at the position where no silicon oxide exists. The shorter the distance of the Thermal Oxide layer (Thermal Oxide), the more easily the monocrystalline silicon is fused and bonded together to generate stress, and N-type epitaxial dislocation is easily caused to cause electric leakage of the device. This situation is increasingly severe in small-sized products.
Disclosure of Invention
The invention aims to provide a hard mask structure for deep trench etching, which solves the problem of lateral corrosion of a thermal oxide layer in the traditional process.
Another technical problem to be solved by the present invention is to provide a method for performing a deep trench process by using the hard mask structure.
In order to solve the above problems, the hard mask structure for deep trench etching according to the present invention is located on a semiconductor substrate, and when deep trench etching is performed on the semiconductor substrate, the hard mask structure serves as a barrier layer for deep trench etching;
the hard mask structure is a multilayer structure, and comprises two layers from the lowest layer covering the semiconductor substrate to the top: a silicon nitride layer at the lowest layer and a silicon oxide layer covering the silicon nitride layer.
Furthermore, the silicon nitride layer covers the semiconductor substrate, and the thickness of the silicon nitride layer is 200-1100A.
Further, the thickness of the silicon nitride layer is 400A.
Furthermore, the silicon oxide layer is used as a main etching barrier layer when the deep trench is etched, and the thickness of the silicon oxide layer is 20000-24000A.
In order to solve the above problems, the present invention provides a process for etching a deep trench, the process comprising:
the method comprises the steps of firstly, providing a semiconductor substrate, and forming a silicon nitride layer on the semiconductor substrate;
secondly, depositing a silicon oxide layer on the formed silicon nitride layer, wherein the silicon oxide layer and the silicon nitride layer are used as hard mask layers for deep trench etching;
thirdly, coating photoresist on the silicon oxide layer, and forming a window area etched by the deep groove after developing;
fourthly, etching the hard mask layer under the definition of the photoresist until the semiconductor substrate is exposed, and transferring the pattern of the photoresist to the hard mask;
fifthly, removing the photoresist, taking the hard mask layer as a barrier layer, etching the semiconductor substrate, and forming a deep groove in the semiconductor substrate;
sixthly, etching to remove the silicon oxide layer on the upper layer in the hard mask layer;
seventhly, carrying out epitaxial filling in the deep groove to enable the deep groove formed by etching to be filled with the epitaxial filling, and covering a layer on the surface of the silicon nitride layer;
eighthly, removing the epitaxial layer on the silicon nitride surface;
and ninthly, etching to remove the silicon nitride layer.
Further, in the first step, the semiconductor substrate either comprises an epitaxy; before forming the silicon nitride layer, the method also comprises the step of removing the oxide layer on the surface of the semiconductor substrate.
Further, the thickness of the formed silicon nitride layer is 200-1100A.
Furthermore, the silicon oxide layer formed in the second step is used as a barrier layer during deep trench etching, the forming process comprises a wet oxygen oxidation process, and the thickness of the formed silicon oxide is 20000-24000A.
Further, in the third step, the thickness of the photoresist is determined according to the actual process requirements.
Further, in the fourth step, the hard mask layer is etched by adopting a dry etching process to complete the pattern transfer of the photoresist.
Further, in the fifth step, the deep trench etching adopts a dry etching process to etch the semiconductor substrate or the epitaxy to form the deep trench.
Further, in the sixth step, a wet etching process is used to remove the thicker silicon nitride layer on the upper layer in the hard mask layer, and after the wet etching, the silicon nitride layer on the lower layer in the hard mask layer still remains.
Further, 13. The process of deep trench etching as claimed in claim 5, wherein: and in the seventh step, the epitaxial layer filled in the deep groove by epitaxy has the conductivity type opposite to that of the semiconductor substrate or epitaxy, and selective epitaxy is filled in the deep groove.
Further, in the eighth step, the epitaxy of the silicon nitride surface is polished and removed by adopting a chemical mechanical polishing process, and the polishing is terminated on the surface of the silicon nitride layer.
Further, in the ninth step, the silicon nitride layer is completely removed by a wet etching process.
According to the hard mask structure etched by the deep groove, the original etched mask layer structure of the ONO is changed into the silicon nitride structure, so that the hidden danger that the thermal oxidation layer at the bottommost layer in the ONO structure is corroded transversely is eliminated. The silicon nitride structure which is not transversely corroded completely covers the epitaxial surface, so that the fusion and adhesion condition of the monocrystalline silicon on the surface of the hard mask structure can be effectively relieved, the problem of dislocation generated by epitaxy is solved to a certain extent, and the technological window of epitaxy is enlarged.
Drawings
FIG. 1 is a schematic diagram of lateral etching of the thermal oxide layer at the bottom layer after etching of a conventional ONO structure layer.
FIGS. 2-10 are schematic diagrams of the steps of the deep trench etching process based on the hard mask structure of the present invention.
FIG. 11 is a flow chart of the process steps of the present invention.
Description of the reference numerals
1 is a substrate or epitaxy, 2 is a silicon nitride layer, 3 is a silicon oxide layer, 4 is a photoresist, and 5 is a P-type epitaxy.
Detailed Description
The following detailed description of the present invention is provided with reference to the accompanying drawings, and the technical solutions in the present invention will be clearly and completely described, but the present invention is not limited to the following embodiments. It should be apparent that the described embodiments are only some of the embodiments of the present invention, and not all of them. Advantages and features of the present invention will become apparent from the following description and from the claims. It is noted that the drawings are in greatly simplified form and that non-precision ratios are used for convenience and clarity only to aid in the description of the embodiments of the invention. All other embodiments obtained by a person skilled in the art without making any inventive step are within the scope of protection of the present invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity, and the same reference numerals denote the same elements throughout. It will be understood that when an element or layer is referred to as being "on," "over," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
In order to make the technical means, the creation characteristics, the achievement purposes and the effects of the invention easy to understand, the invention is further explained by combining the specific drawings.
The hard mask structure etched by the deep groove is formed on a semiconductor substrate, such as a silicon substrate. And when deep trench etching is carried out on the semiconductor substrate, the hard mask structure is used as a barrier layer for the deep trench etching.
The hard mask structure is a double-layer structure, and comprises two layers from the lowest layer covering the semiconductor substrate to the top: a silicon nitride layer at the lowest layer and a silicon oxide layer covering the silicon nitride layer. The silicon nitride layer is 200-1100A thick, covers on the substrate, and the silicon oxide layer as the main force layer of the etching barrier layer is thicker and is generally more than 20000A.
In one embodiment, the present invention etches a deep trench in an N-type epitaxy and then fills a P-type epitaxy to fabricate a super junction structure, wherein the steps of the process method refer to and correspond to fig. 2 to 10, and the process method includes:
first, as shown in fig. 2, an N-type epitaxy is provided, and a silicon nitride layer is formed on the surface of the N-type epitaxy layer. And if the surface of the N-type epitaxial layer has the silicon oxide layer left by the previous process, removing the silicon oxide layer and then manufacturing the silicon nitride layer. The thickness of the formed silicon nitride layer is preferably 400 a in this embodiment.
And secondly, as shown in fig. 3, depositing a silicon oxide layer on the formed silicon nitride layer, wherein the silicon oxide layer and the silicon nitride layer are used as hard mask layers for deep trench etching. The silicon oxide layer plays a main role of a barrier layer during etching, the thickness of the silicon oxide layer is relatively thick, and the typical value of the embodiment is 22000A.
And thirdly, coating photoresist on the silicon oxide layer, wherein the thickness of the photoresist can be determined according to the requirement. And forming a deep groove etched window region after developing and photoetching.
And fourthly, as shown in fig. 5, etching the hard mask layer by using a dry etching process under the definition of the photoresist until the epitaxial layer is exposed, and transferring the pattern of the photoresist onto the hard mask. An etch window for the deep trench is opened on the hard mask layer.
And fifthly, removing the photoresist, taking the hard mask layer as a barrier layer, etching the N-type epitaxial layer by adopting a dry etching process, and forming a deep groove in the N-type epitaxial layer.
And sixthly, removing the thicker silicon oxide layer on the upper layer in the hard mask layer by adopting a wet etching process, wherein the silicon nitride layer on the lower layer in the hard mask still remains after the wet etching.
And seventhly, performing selective P-type epitaxial filling in the deep groove to fill the deep groove formed by etching with the P-type epitaxial filling, and covering a layer on the surface of the silicon nitride layer.
And eighthly, grinding and removing the epitaxy on the surface of the silicon nitride by adopting a chemical mechanical grinding process, wherein the grinding is ended on the surface of the silicon nitride layer. As shown in fig. 9.
And a ninth step, as shown in fig. 10, removing the silicon nitride layer by etching using a wet etching process, such as a hot phosphoric acid process. Because the formed silicon nitride layer is thin, the silicon nitride layer is removed after the previous CMP grinding step, and the whole surface can still keep a relatively flat surface. Therefore, the hard mask layer provided by the invention plays a role and is completely removed, the structure eliminates the hidden trouble that the thermal oxide layer at the bottommost layer of the traditional ONO structure is laterally corroded, the fusion of monocrystalline silicon on the surface of the hard mask is effectively relieved, and the problem of dislocation generated by N-type epitaxy is solved to a certain extent.
The above are merely preferred embodiments of the present invention, and are not intended to limit the present invention. Various modifications and alterations to this invention will become apparent to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (15)
1. A hard mask structure for deep trench etching is characterized in that: the hard mask structure is positioned on a semiconductor substrate, and is used as a barrier layer for deep trench etching when the deep trench etching is carried out on the semiconductor substrate;
the hard mask structure is a composite structure and comprises two layers from the lowest layer covering the semiconductor substrate to the top: a silicon nitride layer at the lowest layer and a silicon oxide layer covering the silicon nitride layer.
2. The deep trench etched hard mask structure of claim 1, wherein: the silicon nitride layer covers the semiconductor substrate, and the thickness of the silicon nitride layer is 200-1100A.
3. The deep trench etched hardmask structure according to claim 2, wherein: the thickness of the silicon nitride layer is 400A.
4. The deep trench etched hardmask structure according to claim 1, wherein: the silicon oxide layer is used as a main etching barrier layer when the deep trench is etched, and the thickness of the silicon oxide layer is 20000-24000A.
5. A deep groove etching process method is characterized by comprising the following steps: the process method comprises the following steps:
the method comprises the steps of firstly, providing a semiconductor substrate, and forming a silicon nitride layer on the semiconductor substrate;
secondly, depositing a silicon oxide layer on the formed silicon nitride layer, wherein the silicon oxide layer and the silicon nitride layer are used as hard mask layers for deep trench etching;
thirdly, coating photoresist on the silicon oxide layer, and forming a window area etched by the deep groove after developing;
fourthly, etching the hard mask layer under the definition of the photoresist until the semiconductor substrate is exposed, and transferring the pattern of the photoresist to the hard mask;
fifthly, removing the photoresist, taking the hard mask layer as a barrier layer, etching the semiconductor substrate, and forming a deep groove in the semiconductor substrate;
sixthly, etching to remove the silicon oxide layer on the upper layer in the hard mask layer;
seventhly, carrying out epitaxial filling in the deep groove to enable the deep groove formed by etching to be filled with the epitaxial filling, and covering a layer on the surface of the silicon nitride layer;
eighthly, removing the epitaxial layer on the silicon nitride surface;
and ninthly, etching to remove the silicon nitride layer.
6. The process of deep trench etching as claimed in claim 5, wherein: in the first step, the semiconductor substrate either comprises an epitaxy; before forming the silicon nitride layer, the method also comprises the step of removing the oxide layer on the surface of the semiconductor substrate.
7. The process of deep trench etching as claimed in claim 6, wherein: the thickness of the formed silicon nitride layer is 200-1100A.
8. The process of deep trench etching as claimed in claim 5, wherein: the silicon oxide layer formed in the second step is used as a barrier layer during deep trench etching, the forming process of the silicon oxide layer comprises a wet oxygen oxidation process, and the thickness of the formed silicon oxide is 20000-24000A.
9. The process of deep trench etching as claimed in claim 5, wherein: in the third step, the thickness of the photoresist is determined according to the actual process requirement.
10. The process of deep trench etching as claimed in claim 5, wherein: and in the fourth step, etching the hard mask layer by adopting a dry etching process to finish the pattern transfer of the photoresist.
11. The process of deep trench etching as claimed in claim 5, wherein: and in the fifth step, etching the semiconductor substrate or the epitaxy by adopting a dry etching process to form the deep groove.
12. The process of deep trench etching as claimed in claim 5, wherein: and in the sixth step, a wet etching process is adopted to remove the thicker silicon nitride layer on the upper layer in the hard mask layer, and after the wet etching, the silicon nitride layer on the lower layer in the hard mask still remains.
13. The process of deep trench etching as claimed in claim 5, wherein: and in the seventh step, the epitaxial layer filled in the deep groove by epitaxy has the conductivity type opposite to that of the semiconductor substrate or epitaxy, and selective epitaxy is filled in the deep groove.
14. The process of deep trench etching as claimed in claim 5, wherein: and in the eighth step, the epitaxy on the surface of the silicon nitride is grinded and removed by adopting a chemical mechanical grinding process, and the grinding is ended on the surface of the silicon nitride layer.
15. The process of deep trench etching as claimed in claim 5, wherein: and in the ninth step, the silicon nitride layer is completely removed by adopting a wet etching process, wherein the wet etching process comprises hydrofluoric acid, hot phosphoric acid and BHF solution.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210806630.2A CN115241122A (en) | 2022-07-08 | 2022-07-08 | Hard mask structure for deep trench etching and process method |
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| CN202210806630.2A CN115241122A (en) | 2022-07-08 | 2022-07-08 | Hard mask structure for deep trench etching and process method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115513051A (en) * | 2022-11-04 | 2022-12-23 | 合肥晶合集成电路股份有限公司 | Hard mask layer reworking method and DMOS forming method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115513051A (en) * | 2022-11-04 | 2022-12-23 | 合肥晶合集成电路股份有限公司 | Hard mask layer reworking method and DMOS forming method |
| CN115513051B (en) * | 2022-11-04 | 2023-02-10 | 合肥晶合集成电路股份有限公司 | Hard mask layer reworking method and DMOS forming method |
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