CN115237037A - Synchronous acquisition and processing method and system for speed regulator on-line monitoring analog signals - Google Patents

Abstract

The system comprises an ARM controller and an FPGA chip, wherein the ARM controller comprises 2A 72 kernels and 4A 53 kernels, the 2A 72 kernels are connected with a second gigabit network port, and IEC61850 protocol transmission is realized while Linux system operation and task scheduling are completed; the 4A 53 kernels are connected with the first gigabit network port, and the external transmission of real-time processing data is realized while the acquired data is processed; the A53 kernel expands the DDR memory chip in a parallel bus communication mode, the parallel bus is simultaneously connected with the FPGA chip, the FPGA chip expands 5 ADC chips in a serial bus mode, and the first key phase signal and the second key phase signal are connected to the A53 kernel and the FPGA chip through special communication lines. The application greatly improves the capability of signal acquisition and processing, and has higher response speed, more flexibility and more safety.

Description

Synchronous acquisition and processing method and system for speed regulator on-line monitoring analog signals

Technical Field

The application relates to the field of analog signal acquisition, in particular to a synchronous acquisition and processing method and system for speed regulator on-line monitoring analog signals.

Background

A hydraulic turbine governor control system is a core device in a power plant secondary control system. The online monitoring control system of the hydraulic turbine governor is an intelligent development direction of the hydraulic turbine control system, is generally applied to a single-machine capacity 100MW-1200MW synchronous generator or a pumped storage unit, realizes real-time synchronous acquisition of analog signals of the synchronous generator set, high-density wave recording, calculation analysis and fault diagnosis, and improves the working efficiency of the hydraulic turbine governor.

With the gradual increase of the capacity of the synchronous generator, the requirements for large data processing such as monitoring, analysis and uploading of the field state quantity of the hydraulic turbine speed regulator are increasing day by day, and the data processing precision and the processing speed are directly related to the accuracy of background data analysis and processing results of an online monitoring system. At present, signal acquisition of most speed regulator online monitoring systems adopts a single MCU to perform ADC chip control and data processing, AD conversion, logic control, data processing, peripheral interaction and the like can only be executed strictly according to a task sequence, and the real-time performance of signal acquisition and the response speed of system data interaction are seriously influenced.

Disclosure of Invention

The embodiment of the application aims to provide a synchronous acquisition and processing method and system for the speed regulator on-line monitoring analog signals, and the synchronous sampling rate, the processing capacity and the system data interaction response speed of the multichannel analog quantity of the speed regulator application occasion are greatly improved.

In order to achieve the above purpose, the present application provides the following technical solutions:

in a first aspect, an embodiment of the present application provides a synchronous acquisition and processing system for speed regulator online monitoring analog signals, which includes an ARM controller and an FPGA chip, where the ARM controller includes 2a 72 cores and 4 a53 cores, and the 2a 72 cores are connected to a second gigabit network port, so as to implement IEC61850 protocol transmission while completing Linux system operation and task scheduling; the 4A 53 kernels are connected with the first gigabit network port, and the external transmission of real-time processing data is realized while the acquired data is processed; the A53 kernel expands the DDR memory chip in a parallel bus communication mode, the parallel bus is simultaneously connected with the FPGA chip, the FPGA chip expands 5 ADC chips in a serial bus mode, and the first key phase signal and the second key phase signal are connected to the A53 kernel and the FPGA chip through special communication lines.

The A72 core and the A53 core in the ARM controller realize the core function division and the data access sharing through a CCI500 bus integrated in the chip.

And the ARM controller is also connected with a static storage chip.

The ADC chip is an 8-channel AD7606 chip.

The first key phase signal and the second key phase signal are 24V pulse input signals or analog quantity voltage signals.

In a second aspect, an embodiment of the present application provides a synchronous acquisition and processing method for an online monitoring analog signal of a speed regulator, including the following specific steps:

s1, detecting a first key phase signal by an ARM controller A53 inner core and an FPGA chip, carrying out pulse counting or analog-to-digital conversion on the first key phase signal, acquiring the frequency or amplitude of the key phase signal, and determining the analog quantity sampling rate; after delaying one or more cycles, enabling all ADC chips simultaneously on the rising edge of the key phase signal;

s2, all ADC chips synchronously sample and convert analog input signals;

s3, the FPGA chip detects the completion marks of all the ADC chips, simultaneously reads the conversion results of all the ADC chips, performs Fourier transform and processing, and stores the data in a DDR memory through a parallel bus;

s4, the ARM controller A53 inner core reads data in the DDR memory in real time through the parallel bus, performs data processing, signal restoration, fault diagnosis or simulation analysis, and directly transmits the data to external equipment through a gigabit network port by using a custom protocol;

s5, running Linux by an ARM controller A72 inner core, mounting a speed regulator on-line monitoring application program, synchronously calling the processed and analyzed data in an ARM memory, and transmitting the data to an external system by using an IEC61850 universal protocol through a gigabit network port;

s6, enabling all the ADC chips by the FPGA chip at the same time on the next rising edge of the key phase signal, and continuing the next round of data acquisition;

and S7, the ARM controller A53 inner core and the FPGA chip detect a second path of key phase signal and stop synchronous sampling.

In step S2, sampling is synchronized at a sampling rate of 8K or 16K.

Compared with the prior art, the invention has the beneficial effects that: the method for realizing multi-task concurrency and independent kernel independent control of signal acquisition, data storage and reading, data processing and analysis, data calling and external transmission and the like by combining a multi-core ARM controller and an FPGA (field programmable gate array), a DDR (double data rate) double-rate synchronous dynamic random access memory is adopted for data caching and transferring inside, a high-speed parallel bus is adopted for data interaction between kernels and kernels, and between kernels and external equipment, so that the signal acquisition and processing capacity is greatly improved; in addition, the starting and stopping of the analog quantity synchronous sampling and the sampling rate are controlled by adopting an external key phase signal, and compared with a traditional control mode, the response speed is higher, more flexible and safer.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and that those skilled in the art can also obtain other related drawings based on the drawings without inventive efforts.

FIG. 1 is an overall hardware functional block diagram of the present invention;

FIG. 2 is a functional block diagram of the key phase signal start and stop 40-way analog signal input synchronous sampling hardware;

FIG. 3 is a schematic flow chart of the method of the present invention.

Detailed Description

The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.

The terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising one of 8230; \8230;" 8230; "does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises the element.

The terms "first," "second," and the like, are used solely to distinguish one entity or action from another entity or action without necessarily being construed as indicating or implying any actual such relationship or order between such entities or actions.

As shown in fig. 1, a synchronous acquisition and processing system for analog signals of speed regulator online monitoring comprises an ARM controller 1 and an FPGA chip 2, wherein the ARM controller 1 comprises 2a 72 kernels 10 and 4 a53 kernels 11, 2a 72 kernels 10 are connected with a second gigabit network port 9, and IEC61850 protocol transmission is realized while Linux system operation and task scheduling are completed; the 4A 53 kernels 11 are connected with the first gigabit network port 8, and the external transmission of real-time processing data is realized while the acquired data is processed; the A53 kernel 11 expands the DDR memory chip 3 in a parallel bus communication mode, the parallel bus is simultaneously connected with the FPGA chip 2, the FPGA chip 2 expands the 5 ADC chips 4 in a serial bus mode, and the first key phase signal 5 and the second key phase signal 6 are connected to the A53 kernel 11 and the FPGA chip 2 through special communication lines. The ARM controller 1 adopts a six-core ARM controller RK3399 with a 64-bit Rui core and a 2GHz main frequency, a 16GB static storage chip 7 is expanded outside the ARM controller 1, a 2GB dynamic storage DDR is arranged on the DDR storage chip 3, and an A53 core 11, an FPGA chip and the DDR storage chip 3 of the ARM controller 1 share the same parallel bus for transmission, so that 10 MByte/s can be achieved.

Based on memory data sharing realized by a special bus CCI500 integrated in the chip of the ARM controller 1, the A72 kernel 10 can synchronously acquire real-time data and complete system task scheduling, data display and transmission.

The FPGA chip 2 synchronously reads 5 ADC chips 4 through the IO port; the gigabit network port is connected with an external drive circuit in an RGMII interface form, and the self-adaptation of 10/100/1000Mbps is realized.

The 40-channel analog signal input synchronous sampling completes data per second at a sampling rate of 8K or 16K as follows:

8K sampling rate: 40ch 8 × 1024 × 2byte =680kbyte/sec.

16K sampling rate: 40ch 16 × 1024 × 2byte =1.25mbyte/sec.

The RAM capacity of the traditional 32-bit single-core MCU is generally smaller than 2MB, when the 32-bit single-core MCU is used for ADC chip control and data processing, the required dynamic RAM capacity per second is at least 680KB, meanwhile, the ARM controller also needs to execute logic operation, task scheduling, communication protocol forwarding and the like, and the traditional 32-bit single-core MCU cannot achieve that 40 paths of analog signals complete synchronous sampling data processing and data forwarding at 8K or 16K.

In order to realize synchronous sampling of 40 paths of analog signals at 8K or 16K, the acquisition and processing of the analog signals are completed by high-performance GW2A-LV55 series FPGA chips, and the analog signals are read by an ARM controller through a high-speed parallel port bus and a cache chip of a high-capacity 2GB dynamic memory DDR. An ARM controller A53 inner core with the main frequency of 2GHz acquires real-time data through a parallel port bus, completes comprehensive processing of the data, integrates the functions of fault diagnosis and simulation analysis of a speed regulator unit, and forwards the data to the outside through a gigabit network port. The ARM controller A72 inner core completes Linux system operation, task scheduling, data display, external protocol conversion and the like.

According to the speed regulator on-line monitoring analog signal synchronous acquisition and processing system provided by the embodiment of the application, the ARM controller and the FPGA chip simultaneously identify external key phase signals, trigger the start and stop of synchronous sampling of analog quantity signals, and determine the sampling rate of synchronous sampling by identifying the frequency or amplitude of the key phase signals. The external key phase signal is composed of 2 channels, the first channel is a synchronous sampling starting signal, and the second channel is a synchronous sampling stopping signal. The key phase signals are of two types, one is a 24V pulse input signal, and the other is an analog voltage input signal; the sampling rate of the analog signal is determined by the 24V pulse input frequency or the amplitude of the analog voltage input signal.

When the key phase signal is a 24V pulse input signal, after the key phase signal is converted into a TTL level after high-speed optical isolation and level conversion: the first channel is connected to a GPIO pin of an A53 core TIM2-1 of the ARM and a GPIO-1 of the FPGA, and the second channel is connected to a GPIO pin of an A53 core TIM2-2 of the ARM and a GPIO-2 pin of the FPGA.

When the key phase signal is input as an analog voltage signal, the key phase signal is transmitted to the FPGA in a serial bus mode after passing through the ADC chip: the first channel sends a start synchronous sampling signal to a GPIO pin of an A53 core TIM2-3 of the ARM through the GPIO-3 of the FPGA, and the second channel sends a stop synchronous sampling signal to a GPIO pin of an A53 core TIM2-4 of the ARM through the GPIO-4 of the FPGA.

As shown in fig. 2, in the speed regulator online monitoring signal acquisition and processing system provided by the present application, the ARM controller and the FPGA chip control 40 analog quantity synchronous sampling by recognizing 2 key phase signal states. The 1 st channel of the key phase signal is used for starting synchronous sampling, and the 2 nd channel of the key phase signal is used for stopping synchronous sampling; meanwhile, the sampling rate of synchronous sampling is controlled by identifying the amplitude or frequency of the key phase signal.

As shown in fig. 3, the present application further provides a synchronous collecting and processing method for the speed regulator online monitoring analog signal, which includes the following specific steps:

s1, detecting a first key phase signal by an ARM controller A53 inner core and an FPGA chip, carrying out pulse counting or analog-to-digital conversion on the first key phase signal, acquiring the frequency or amplitude of the key phase signal, and determining the analog quantity sampling rate; after delaying one or more cycles, enabling all ADC chips simultaneously on the rising edge of the key phase signal;

s2, all ADC chips synchronously sample and convert analog input signals;

s3, the FPGA chip detects the completion marks of all the ADC chips, simultaneously reads the conversion results of all the ADC chips, performs Fourier transform and processing, and stores the data in a DDR memory through a parallel bus;

s4, the ARM controller A53 inner core reads data in the DDR memory in real time through the parallel bus, performs data processing, signal restoration, fault diagnosis or simulation analysis, and directly transmits the data to external equipment through a gigabit network port by using a custom protocol;

s5, running Linux by an ARM controller A72 inner core, mounting a speed regulator on-line monitoring application program, synchronously calling the processed and analyzed data in an ARM memory, and transmitting the data to an external system by using an IEC61850 universal protocol through a gigabit network port;

s6, enabling all the ADC chips by the FPGA chip at the same time on the next rising edge of the key phase signal, and continuing the next round of data acquisition;

and S7, the ARM controller A53 inner core and the FPGA chip detect a second path of key phase signal and stop synchronous sampling.

In step S2, sampling is synchronized at a sampling rate of 8K or 16K.

According to the method, the FPGA chip starts and closes 40 paths of analog signal input to synchronously sample at 8K or 16K sampling rate by taking a 24V pulse input signal or an analog quantity voltage signal as a key phase signal, the collected signal is subjected to Fourier transform through the FPGA chip and is transferred and stored through a DDR memory, the collected signal is read and processed by an A53 inner core of an ARM controller and then is sent to external equipment and a system for display or analysis processing by using a general or custom protocol through a high-speed network port, and the multichannel analog quantity synchronous sampling rate, the processing capacity and the system data interaction response speed of a speed regulator application occasion are greatly improved.

The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims (7)

1. A synchronous acquisition and processing system for speed regulator on-line monitoring analog signals is characterized by comprising an ARM controller and an FPGA chip, wherein the ARM controller comprises 2A 72 kernels and 4A 53 kernels, the 2A 72 kernels are connected with a second gigabit net port, and IEC61850 protocol transmission is realized while Linux system operation and task scheduling are completed; the 4A 53 kernels are connected with the first kilomega network port, and the data is processed in real time and transmitted to the outside while the acquired data is processed; the A53 kernel expands the DDR memory chip in a parallel bus communication mode, the parallel bus is simultaneously connected with the FPGA chip, the FPGA chip expands 5 ADC chips in a serial bus mode, and the first key phase signal and the second key phase signal are connected to the A53 kernel and the FPGA chip through special communication lines.

2. The synchronous acquisition and processing system for the analog signals of the on-line monitoring of the speed regulator according to claim 1, wherein the A72 core and the A53 core in the ARM controller realize the core function division and the data access sharing through a CCI500 bus integrated in the chip.

3. The system for synchronously acquiring and processing the analog signals of the online monitoring of the speed regulator according to claim 1, wherein a static memory chip is further connected to the ARM controller.

4. The speed regulator on-line monitoring analog signal synchronous acquisition and processing system of claim 1, wherein the ADC chip is an 8-channel AD7606 chip.

5. The system for synchronously acquiring and processing the analog signals of the online monitoring of the speed regulator according to claim 1, wherein the first key phase signal and the second key phase signal are 24V pulse input signals or analog voltage signals.

6. A synchronous acquisition and processing method for speed regulator on-line monitoring analog signals is characterized by comprising the following specific steps:

s1, detecting a first key phase signal by an ARM controller A53 inner core and an FPGA chip, carrying out pulse counting or analog-to-digital conversion on the first key phase signal, acquiring the frequency or amplitude of the key phase signal, and determining the analog quantity sampling rate; after delaying one or more cycles, enabling all ADC chips simultaneously on the rising edge of the key phase signal;

s2, all the ADC chips synchronously sample and convert the analog input signals;

s3, the FPGA chip detects the completion marks of all the ADC chips, simultaneously reads the conversion results of all the ADC chips, performs Fourier transform and processing, and stores the data in a DDR memory through a parallel bus;

s4, the ARM controller A53 inner core reads data in the DDR memory in real time through the parallel bus, performs data processing, signal restoration, fault diagnosis or simulation analysis, and directly transmits the data to external equipment through a gigabit network port by using a custom protocol;

s5, running Linux by an ARM controller A72 inner core, mounting a speed regulator on-line monitoring application program, synchronously calling the processed and analyzed data in an ARM memory, and transmitting the data to an external system by using an IEC61850 universal protocol through a gigabit network port;

s6, enabling all the ADC chips by the FPGA chip at the same time on the next rising edge of the key phase signal, and continuing the next round of data acquisition;

and S7, the ARM controller A53 inner core and the FPGA chip detect a second path of key phase signal and stop synchronous sampling.

7. The synchronous acquisition and processing method for the analog signals of the online monitor of the speed regulator, according to claim 6, is characterized in that in the step S2, synchronous sampling is carried out at a sampling rate of 8K or 16K.

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