CN115224053A - Display panel, manufacturing method thereof and display device - Google Patents

Display panel, manufacturing method thereof and display device Download PDF

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Publication number
CN115224053A
CN115224053A CN202210922518.5A CN202210922518A CN115224053A CN 115224053 A CN115224053 A CN 115224053A CN 202210922518 A CN202210922518 A CN 202210922518A CN 115224053 A CN115224053 A CN 115224053A
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Prior art keywords
region
layer
sub
metal layer
substrate
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CN202210922518.5A
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Chinese (zh)
Inventor
刘方梅
其他发明人请求不公开姓名
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to CN202210922518.5A priority Critical patent/CN115224053A/en
Publication of CN115224053A publication Critical patent/CN115224053A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement

Abstract

The application provides a display panel and a manufacturing method thereof, and a display device, wherein the display panel comprises a thin film transistor layer arranged on a substrate, the thin film transistor layer comprises an active layer, a grid electrode insulating layer and a grid electrode, the active layer is arranged above the substrate, the active layer is made of metal oxide, the active layer comprises a channel region and a doped region connected with the channel region, and the orthographic projection of the grid electrode on the substrate covers the orthographic projection of the channel region on the substrate; the doping region comprises a plurality of oxygen vacancies and nitrogen ions at least partially filling the oxygen vacancies, and the channel region is arranged to comprise the nitrogen ions at least partially filling the oxygen vacancies, so that the oxygen vacancies in the active layer are reduced, and the transmission rate of carriers is improved.

Description

Display panel, manufacturing method thereof and display device
Technical Field
The application relates to the technical field of display, in particular to a display panel, a manufacturing method thereof and a display device.
Background
Now, please refer to fig. 1, which is a schematic structural diagram of a conventional display panel; the conventional display panel comprises a substrate 10, and a thin film transistor layer 20, a passivation layer 30, a bridging portion 40, a flat layer 50, a light emitting device layer 60, a pixel defining layer 70 and a packaging layer 80 stacked on the substrate 10, wherein the substrate 10 comprises a substrate 11, a light shielding layer 12 and a buffer layer 13 which are stacked in sequence, the thin film transistor layer 20 comprises an active layer 21, a gate insulating layer 22, a gate 23A, an interlayer insulating layer 24, a source 25A and a drain 25B which are stacked on the substrate 10 in sequence, the active layer 21 comprises a first doped region 211B, a second doped region 212B and a channel region 21A located between the first doped region 211B and the second doped region 212B, the source 25A is connected with the first doped region 211B of the active layer 21, and the drain 25B is connected with the second doped region 212B of the active layer 21.
It can be understood that, in the prior art, the Thin Film Transistor layer 20 includes a plurality of Thin Film transistors 20A (TFTs) arranged in a matrix, wherein, by virtue of their low process temperature, high mobility, transparency to visible light, capability of fabricating a large-area high-quality Thin Film at room temperature, compatibility with existing production line equipment, capability of fabricating on the flexible substrate 11, and the like, oxide-type TFTs are considered to be one of the most promising next-generation TFTs; when the oxide thin film transistor 20A is manufactured, when metals (i.e., the source electrode 25A and the drain electrode 25B) are in contact with the active layer 21, a potential barrier is formed at a mutual contact interface, and the existence of the potential barrier causes large interface resistance, so that on-state current of elements of the thin film transistor 20A is insufficient, and thus the quality of display of a display panel is affected, in order to ensure that the source electrode 25A and the drain electrode 25B in the thin film transistor 20A are in good contact with the active layer 21, it is necessary to reduce the overlap resistance between the metals and the active layer 21, and a method of conducting a conductor treatment on a position in the active layer 21 for contacting with the source electrode 25A and the drain electrode 25B is generally adopted, so as to reduce the overlap resistance of the source electrode 25A and the drain electrode 25B, and further improve the performance of the thin film transistor 20A. However, in the prior art, when the active layer is subjected to dry etching-conductor processing, the active layer is often subjected to conductor processing by using plasma gas at the positions for contacting with the source and the drain, but the plasma gas diffuses toward the channel region along the doped region in the lap joint region 21B1, so that the actual channel length of the thin film transistor is less uniformly distributed on the substrate, and even the semiconductor performance of the thin film transistor is lost, thereby affecting the display effect of the display panel.
Disclosure of Invention
The embodiment of the application provides a display panel, a manufacturing method thereof and a display device, which are used for relieving the defects in the related art.
In order to realize the above functions, the technical solutions provided in the embodiments of the present application are as follows:
an embodiment of the present application provides a display panel, including:
a substrate;
the thin film transistor layer is arranged on the substrate and comprises an active layer, a grid electrode insulating layer and a grid electrode, the active layer, the grid electrode insulating layer and the grid electrode are arranged above the substrate, the active layer is made of metal oxide, the active layer comprises a channel region and a doped region connected with the channel region, and the orthographic projection of the grid electrode on the substrate covers the orthographic projection of the channel region on the substrate;
wherein the doped region comprises a plurality of oxygen vacancies, and nitrogen ions that at least partially fill the oxygen vacancies.
In the display panel provided in the embodiment of the present application, the concentration of the nitrogen ions is smaller than the concentration of the oxygen vacancies.
In the display panel provided in the embodiment of the present application, the display panel further includes a first metal layer stacked on the active layer, and the doped region includes a landing region connected to the first metal layer and a doped sub-region located between the landing region and the channel region, where a concentration of nitrogen ions in the doped sub-region is less than a concentration of nitrogen ions in the landing region.
In the display panel provided in the embodiment of the present application, the first metal layer includes a source electrode and a drain electrode, the landing zone includes a first landing zone in contact with the source electrode and a second landing zone in contact with the drain electrode, and the channel region is located between the first landing zone and the second landing zone;
wherein a width of the channel region is less than or equal to 3 micrometers in a direction in which the first lap region points toward the second lap region.
In the display panel provided by the embodiment of the present application, the doped sub-region includes a first doped sub-region and a second doped sub-region, the first doped sub-region is located between the first overlapping region and the channel region, and the second doped sub-region is located between the second overlapping region and the channel region;
wherein the concentration of nitrogen ions in the first doped sub-region is less than that in the first overlapping region, and the concentration of nitrogen ions in the second doped sub-region is less than that in the second overlapping region.
In the display panel provided in the embodiment of the present application, the thin-film transistor layer further includes a second metal layer, and the second metal layer includes the gate;
the second metal layer comprises a first sub-metal layer and a second sub-metal layer which are arranged on the substrate in a laminated mode, wherein the material of the second sub-metal layer comprises an inert metal material, and the electric conductivity of the first sub-metal layer is larger than that of the second sub-metal layer.
In the display panel provided in the embodiment of the present application, the material of the second sub-metal layer includes at least one of molybdenum, titanium, and a molybdenum-titanium alloy, and the material of the first sub-metal layer includes at least one of copper, aluminum, and silver.
In the display panel provided in the embodiment of the present application, the second metal layer further includes a third sub-metal layer located between the first sub-metal layer and the gate insulating layer, and a material of the third sub-metal layer includes at least one of molybdenum, titanium, and a molybdenum-titanium alloy.
The embodiment of the application provides a manufacturing method of a display panel, which comprises the following steps:
providing a substrate, and sequentially forming an active layer, a gate insulating layer and a gate on the substrate;
conducting treatment on the active layer to form a channel region and a doped region connected with the channel region, wherein the orthographic projection of the grid electrode on the substrate covers the orthographic projection of the channel region on the substrate, and the doped region comprises a plurality of oxygen vacancies;
and carrying out plasma doping treatment on the doped region to enable the doped region to comprise nitrogen atoms, wherein the nitrogen atoms at least fill part of the oxygen vacancies.
A display device comprising the display panel of any of the above.
The beneficial effects of the embodiment of the application are as follows: the embodiment of the application provides a display panel, a manufacturing method thereof and a display device, wherein the display panel comprises a thin film transistor layer which is stacked on a substrate, the thin film transistor layer comprises an active layer, a grid electrode insulating layer and a grid electrode which are arranged above the substrate, the active layer is made of metal oxide, the active layer comprises a channel region and a doped region which is connected with the channel region, and the orthographic projection of the grid electrode on the substrate covers the orthographic projection of the channel region on the substrate; wherein the doped region comprises a plurality of oxygen vacancies, and nitrogen ions that at least fill a portion of the oxygen vacancies; by providing the channel region to include nitrogen ions that fill at least a portion of the oxygen vacancies, thereby reducing oxygen vacancies in the active layer, the carrier transport rate is increased.
Drawings
The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.
FIG. 1 is a schematic structural diagram of a conventional display panel;
fig. 2 is a schematic view of a first structure of a display panel according to an embodiment of the present disclosure;
fig. 3 is a second structural schematic diagram of a display panel according to an embodiment of the present disclosure
Fig. 4 is a flowchart of a method for manufacturing a display panel according to an embodiment of the present disclosure;
fig. 5A to 5G are process flow diagrams of the structure of the display panel shown in fig. 4.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application. Furthermore, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the present application, are given by way of illustration and explanation only, and are not intended to limit the present application. In the present application, unless indicated to the contrary, the use of the directional terms "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, and more particularly to the orientation of the figures of the drawings; while "inner" and "outer" are with respect to the outline of the device.
The embodiment of the application provides a display panel, a manufacturing method thereof and a display device. The following are detailed below. It should be noted that the following description of the embodiments is not intended to limit the preferred order of the embodiments.
Referring to fig. 2 to 5G, an embodiment of the present application provides a display panel, a manufacturing method thereof, and a display device, where the display panel includes:
a substrate 10;
the thin-film transistor layer 20 is disposed on the substrate 10, the thin-film transistor layer 20 includes an active layer 21, a gate insulating layer 22 and a gate 23A disposed above the substrate 10, the active layer 21 is made of metal oxide, the active layer 21 includes a channel region 21A and a doped region 21B connected to the channel region 21A, and an orthographic projection of the gate 23A on the substrate 10 covers an orthographic projection of the channel region 21A on the substrate 10;
wherein the doped region 21B includes a plurality of oxygen vacancies, and nitrogen ions that at least partially fill the oxygen vacancies.
It can be understood that the embodiment of the present application improves the carrier transport rate by arranging the doped region 21B to include nitrogen ions that fill at least part of the oxygen vacancies, thereby reducing the oxygen vacancies in the active layer 21.
The technical solution of the present application will now be described with reference to specific embodiments.
In an embodiment, please refer to fig. 2, which is a schematic diagram illustrating a first structure of a display panel according to an embodiment of the present disclosure.
The present embodiment provides a display panel, which includes but is not limited to one of a Light-emitting diode (LED) and an organic Light-emitting diode (OLED), and the present embodiment does not specifically limit the present invention; it should be noted that, in this embodiment, the technical solution of the present application is described by taking the display panel as an organic light emitting diode display panel as an example.
In this embodiment, the display panel includes a substrate 10 and a thin-film transistor layer 20 located on the substrate 10; wherein, the base 10 includes a substrate 11 and a buffer layer 13 disposed on the substrate 11, the substrate 11 may include one of a rigid substrate or a flexible substrate, and the material of the buffer layer 13 includes, but is not limited to, a single layer of silicon nitride (Si) 3 N 4 ) Single layer silicon dioxide (SiO) 2 ) Single layer of silicon oxynitride (SiON) x ) Or a double-layer structure of the above layers, which is not limited in this embodiment.
The thin film transistor layer 20 includes a plurality of thin film transistors 20A arranged in a matrix, the thin film transistors 20A include an active layer 21, a gate insulating layer 22, and a gate 23A disposed above the substrate 10, the active layer 21 is made of a metal Oxide, and the metal Oxide includes, but is not limited to, indium Gallium Zinc Oxide (IGZO), indium Tin Zinc Oxide (ITZO), or Indium Gallium Zinc Titanium Oxide (IGZTO).
In this embodiment, the display panel further includes a first metal layer 25 stacked on the active layer 21, the active layer 21 includes a channel region 21A and a doped region 21B connected to the channel region 21A, an orthographic projection of the gate 23A on the substrate 10 covers an orthographic projection of the channel region 21A on the substrate 10, and the first metal layer 25 is connected to the doped region 21B; wherein the doped region 21B comprises a plurality of oxygen vacancies, and nitrogen ions that at least partially fill the oxygen vacancies.
Further, in this embodiment, the first metal layer 25 includes a source 25A and a drain 25B of the thin film transistor 20A, the display panel further includes an interlayer insulating layer 24 located between the gate 23A and the first metal layer 25, a via hole exposing a portion of the doped region 21B is formed on the interlayer insulating layer 24, and the first metal layer 25 is connected to the doped region 21B through the first via hole.
It should be noted that, in the present embodiment, the technical solution of the present application is illustrated by taking an example that the active layer 21, the gate insulating layer 22, the gate 23A and the first metal layer 25 are sequentially stacked on the substrate 10, and the film structure of the thin film transistor 20A is not specifically limited in this embodiment.
Further, in the present embodiment, the doped region 21B includes a first doped region 211B connected to the source 25A and a second doped region 212B connected to the drain 25B, and the channel region 21A is located between the first doped region 211B and the second doped region 212B; the first doped region 211B includes a plurality of oxygen vacancies, the first doped region 211B includes nitrogen ions that fill at least a portion of the oxygen vacancies, the second doped region 212B includes a plurality of oxygen vacancies, and the second doped region 212B includes nitrogen ions that fill at least a portion of the oxygen vacancies.
It can be understood that, with reference to fig. 1, in order to ensure that the source electrode 25A and the drain electrode 25B in the thin film transistor 20A have good contact with the active layer 21, it is necessary to reduce the overlap resistance between the first metal layer 25 and the active layer 21, in the prior art, a method of performing a conductor treatment on the positions in the active layer 21 for contacting with the source electrode 25A and the drain electrode 25B is generally adopted to reduce the overlap resistance of the source electrode 25A and the drain electrode 25B, thereby improving the performance of the thin film transistor 20A; when the active layer 21 is subjected to dry etching-conductor treatment, a plasma gas is usually used to conduct conductor treatment on the positions of the active layer 21, which are used for contacting with the source electrode 25A and the drain electrode 25B, but the plasma gas diffuses from the doped region 21B to the channel region 21A, so that the actual channel length of the thin film transistor 20A is poor in distribution uniformity on the substrate, and even the semiconductor performance of the thin film transistor is lost, thereby affecting the display effect of the display panel.
It can be understood that, in the embodiment of the present application, the doped region 21B includes a first doped region 211B connected to the source electrode 25A and a second doped region 212B connected to the drain electrode 25B, the first doped region 211B includes nitrogen ions filling at least a portion of the oxygen vacancies, and the second doped region 212B includes nitrogen ions filling at least a portion of the oxygen vacancies, so that the oxygen vacancies in the active layer 21 are reduced, and the carrier transport rate is increased.
In this embodiment, the concentration of the nitrogen ions is smaller than that of the oxygen vacancies, so that the conductive characteristics of the doped region 21B can be maintained and the characteristic of the oxide semiconductor thin film transistor 20A with high electron mobility can be prevented from being damaged.
In this embodiment, the interlayer insulating layer 24 is formed with a first via hole (not labeled) exposing a portion of the first doped region 211B and a second via hole (not labeled) exposing a portion of the second doped region 212B, the source 25A is connected to the first doped region 211B through the first via hole, and the drain 25B is connected to the second doped region 212B through the second via hole.
In this embodiment, the thin-film transistor layer 20 further includes a second metal layer 23, where the second metal layer 23 includes the gate 23A of the thin-film transistor 20A; wherein the second metal layer 23 includes a first sub-metal layer 231A and a second sub-metal layer 231B stacked on the substrate 10, wherein a material of the second sub-metal layer 231B includes an inert metal material, and an electrical conductivity of the first sub-metal layer 231A is greater than an electrical conductivity of the second sub-metal layer 231B.
Specifically, in the present embodiment, the oxidation resistance of the second sub-metal layer 231B is greater than that of the first sub-metal layer 231A, the material of the second sub-metal layer 231B includes, but is not limited to, at least one of molybdenum (Mo), titanium (Ti), and molybdenum-titanium alloy (MoTi), and the material of the first sub-metal layer 231A includes, but is not limited to, at least one of copper (Cu), aluminum (Al), and silver (Ag).
It is understood that in the existing display panel, metal copper (Cu) is generally used as the material of the material, and in the present embodiment, when the doping region 21B is doped with nitrogen ions using plasma, if the plasma includes oxygen ions, for example, nitrous oxide (N) is used 2 O) performing a plasma doping process on the doped region 21B, the gate electrode 23A is at risk of being oxidized, and therefore, in this embodiment, the second metal layer 23 includes a first sub-metal layer 231A and a second sub-metal layer 231B stacked on the substrate 10, the second sub-metal layer 231B includes an inert metal material, and the first sub-metal layer 231A has a conductivity greater than that of the second sub-metal layer 231B, so as to form a protection for the first sub-metal layer 231A, prevent the first sub-metal layer 231A from being oxidized, and ensure stable operation of the thin film transistor 20A.
Further, in this embodiment, the second metal layer 23 further includes a third sub-metal layer 231C located between the first sub-metal layer 231A and the gate insulating layer 22, and a bonding force between the third sub-metal layer 231C and the gate insulating layer 22 is greater than a bonding force between the first sub-metal layer 231A and the gate insulating layer 22.
Specifically, the material of the third sub-metal layer 231C is the same as the material of the second sub-metal layer 231B, the material of the third sub-metal layer 231C includes an inert metal material, and the material of the third sub-metal layer 231C includes, but is not limited to, at least one of molybdenum (Mo), titanium (Ti), and molybdenum-titanium alloy (MoTi); it can be understood that, in the present embodiment, by providing that the second metal layer 23 further includes a third sub-metal layer 231C located between the first sub-metal layer 231A and the gate insulating layer 22, and a bonding force between the third sub-metal layer 231C and the gate insulating layer 22 is greater than a bonding force between the first sub-metal layer 231A and the gate insulating layer 22, adhesion between the gate electrode 23A and the gate insulating layer 22 is increased, and a peeling problem of the gate electrode 23A in a manufacturing process of the thin film transistor 20A is avoided.
In addition, the above-mentioned dinitrogen monoxide (N) is used 2 O) the method of performing the plasma doping treatment on the doping region 21B is only for illustration, and the kind of the plasma is not particularly limited in this embodiment.
Further, in this embodiment, the display panel further includes a passivation layer 30, a bridge portion 40, a flat layer 50, a light emitting device layer 60, and an encapsulation layer 80 located on a side of the thin-film transistor layer 20 away from the substrate 10, where it is to be noted that other functional film layers may also be disposed between the substrate 10 and the encapsulation layer 80, which is not limited in this embodiment.
In this embodiment, the light emitting device layer 60 includes an anode 61, a light emitting layer 62 and a cathode 63 stacked on the planarization layer 50, wherein the passivation layer 30 has a third via (not labeled) formed thereon to expose a portion of the source electrode 25A or the drain electrode 25B, the bridging portion 40 is connected to the source electrode 25A or the drain electrode 25B through the third via, the planarization layer 50 has a fourth via (not labeled) formed thereon to expose a portion of the bridging portion 40, and the anode 61 is connected to the bridging portion 40 through the fourth via, that is, the anode 61 is connected to the source electrode 25A or the drain electrode 25B through the bridging portion 40; preferably, in this embodiment, the passivation layer 30 is opened with the third via hole exposing a portion of the drain electrode 25B, the bridging portion 40 is connected to the drain electrode 25B through the third via hole, and the anode 61 is connected to the drain electrode 25B through the bridging portion 40.
It should be noted that, in this embodiment, the display panel further includes a pixel defining layer 70 located on a side of the anode 61 away from the planarization layer 50, an opening (not labeled in the figure) exposing the anode 61 is formed in the pixel defining layer 70, the light emitting layer 62 is located in the opening, the light emitting layer 62 is connected to the anode 61 through the opening, and the cathode 63 is connected to the light emitting layer 62 through the opening.
The substrate 10 further includes a light shielding layer 12 disposed between the substrate 11 and the buffer layer 13, an orthographic projection of the light shielding layer 12 on the substrate 10 covers an orthographic projection of the active layer 21 on the substrate 10, and the light shielding layer 12 can shield light incident on the active layer 21, so as to reduce an increase in leakage current caused by photo-generated carriers generated by the light irradiating the active layer 21, thereby maintaining stability of the display panel during operation.
In another embodiment, please refer to fig. 3, which is a second structural diagram of a display panel provided in the present application.
In this embodiment, the structure of the display panel is similar to that of the display panel provided in the above embodiments, and please refer to the description of the display panel in the above embodiments, which is not repeated herein, and the difference between the two embodiments is only:
in the present embodiment, the doped region 21B includes a landing zone 21B1 connected to the first metal layer 25 and a doped sub-region 21B2 located between the landing zone 21B1 and the channel region 21A, wherein the concentration of nitrogen ions in the doped sub-region 21B2 is less than the concentration of nitrogen ions in the landing zone 21B 1.
Specifically, the landing zone 21B1 includes a first landing zone 211B1 contacting the source 25A and a second landing zone 212B1 contacting the drain 25B, the channel region 21A is located between the first landing zone 211B1 and the second landing zone 212B1, and the doped sub-zone 21B2 includes a first doped sub-zone 211B2 located between the first landing zone 211B1 and the channel region 21A and a second doped sub-zone 212B2 located between the second landing zone 212B1 and the channel region 21A, wherein along a direction in which the first landing zone 211B1 points to the second landing zone 212B1, a width of the channel region 21A is less than or equal to 3 microns, a concentration of nitrogen ions in the first doped sub-zone 211B2 is less than a concentration of nitrogen ions in the first landing zone 211B1, and a concentration of nitrogen ions in the second doped sub-zone 212B2 is less than a concentration of nitrogen ions in the second landing zone 212B 1.
It can be understood that, in the present embodiment, by providing the doped region 21B including the landing region 21B1 connected to the first metal layer 25 and the doped sub-region 21B2 located between the landing region 21B1 and the channel region 21A, the concentration of nitrogen ions in the doped sub-region 21B2 is less than that in the landing region 21B1, and by reserving the distance of the diffusion region of the plasma gas, the plasma gas in the landing region 21B1 is prevented from diffusing toward the channel region 21A during the conductor forming process of the active layer 21, the channel region 21A is prevented from losing semiconductor characteristics during the conductor forming process of the active layer 21, and thus the effective channel length is ensured, which is beneficial for realizing the short-channel forming process of the thin film transistor 20A.
Please refer to fig. 2, fig. 4, and fig. 5A to fig. 5E; fig. 4 is a flowchart of a method for manufacturing a display panel according to an embodiment of the present disclosure; fig. 5A to 5G are process flow diagrams of the structure of the display panel shown in fig. 4.
The present embodiment provides a manufacturing method of a display panel, where the manufacturing method includes:
step S100: a substrate 10 is provided, and an active layer 21, a gate insulating layer 22 and a gate 23A are sequentially formed on the substrate 10.
Specifically, in this embodiment, the step S100 includes the following steps:
step S101: providing the base 10, including providing a substrate 11, and forming a light-shielding layer 12 and a buffer layer 13 on the substrate 11 in sequence; as shown in fig. 5A;
wherein when the substrate is a rigid substrate, the material can be metal or glass; when the substrate 11 is a flexible substrate, the material may include at least one of acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy-based resin, polyurethane-based resin, cellulose resin, silicone resin, polyimide-based resin, and polyamide-based resin.
The thickness of the light shielding layer 12 ranges from 1000 angstroms to 8000 angstroms, the material of the light shielding layer 12 includes but is not limited to a metal material, and the metal material includes but is not limited to one or more alloys of molybdenum (Mo), titanium (Ti), and nickel (Ni); the thickness of the buffer layer 13 ranges from 1000 to 5000 angstroms, and the material of the buffer layer 13 includes, but is not limited to, a single layer of silicon nitride (Si 3N 4), a single layer of silicon dioxide (SiO 2), a single layer of silicon oxynitride (sioxx), or a double-layer structure of the above layers.
Step S102: a metal oxide film is deposited on the buffer layer 13, and the active layer 21 is formed by patterning the metal oxide film, as shown in fig. 5B.
Specifically, the material of the Oxide thin film includes, but is not limited to, indium Gallium Zinc Oxide (IGZO), indium Tin Zinc Oxide (ITZO), or Indium Gallium Zinc Titanium Oxide (IGZTO), and preferably, the present embodiment exemplifies the technical solution of the present application by taking the material of the Oxide thin film including, but not limited to, indium Gallium Zinc Oxide.
In this embodiment, a metal oxide semiconductor layer is deposited on the buffer layer 13 by a Physical Vapor Deposition (PVD) method, and the oxide semiconductor layer is patterned by a yellow light process to form the active layer 21, wherein the thickness of the active layer 21 ranges from 400 to 1000 angstroms, and an orthographic projection of the light shielding layer 12 on the substrate covers an orthographic projection of the active layer 21 on the substrate.
Step S103: and sequentially forming a gate insulating layer 22 and a gate electrode 23A on the active layer 21, wherein an orthographic projection of the gate electrode 23A on the substrate 10 is overlapped with an orthographic projection of the gate insulating layer 22 on the substrate 10, and the orthographic projection of the gate insulating layer 22 on the substrate 10 is located in an orthographic projection range of the active layer 21 on the substrate 10.
Specifically, the step S103 includes the following steps:
step S1031: forming a gate insulating material layer on the active layer 21, the gate insulating material layer including, but not limited to, silicon oxide (SiO) X ) The thickness range of the gate insulating material layer is 1000-3000 angstroms.
Step S1032: a second metal layer 23 is formed on a side of the gate insulating material layer away from the active layer 21, a thickness of the second metal layer 23 ranges from 2000 to 8000 angstroms, the second metal layer 23 includes a third sub-metal layer 231C, a first sub-metal layer 231A and a second sub-metal layer 231B, which are stacked on the gate insulating material layer, wherein a material of the third sub-metal layer 231C and a material of the second sub-metal layer 231B include, but are not limited to, at least one of molybdenum (Mo), titanium (Ti) and molybdenum-titanium alloy (MoTi), and a material of the first sub-metal layer 231A includes, but is not limited to, at least one of copper (Cu), aluminum (Al) and silver (Ag).
Preferably, in this embodiment, the technical solution of the present application is illustrated by taking the material of the third sub-metal layer 231C as molybdenum-titanium alloy (MoTi), the material of the first sub-metal layer 231A as copper (Cu), and the material of the second sub-metal layer 231B as molybdenum-titanium alloy (MoTi).
It is understood that, in the embodiment, the third sub-metal layer 231C, the first sub-metal layer 231A and the second sub-metal layer 231B can be simultaneously fabricated through one photo-masking process, so that no additional photo-masking process is added, and the process is simpler.
Step S1033: patterning the second metal layer 23, forming a gate 23A on the gate insulating material layer, self-aligning the gate 23A with the gate insulating material layer, and etching the gate insulating material layer to form the gate insulating layer 22, as shown in fig. 5C.
Conducting treatment on the active layer 21 to form a channel region 21A and a doped region 21B connected with the channel region 21A, wherein the orthographic projection of the gate 23A on the substrate 10 covers the orthographic projection of the channel region 21A on the substrate 10, and the doped region 21B comprises a plurality of oxygen vacancies.
Further, in the present embodiment, the doped region 21B includes a first doped region 211B and a second doped region 212B, and the channel region 21A is located between the first doped region 211B and the second doped region 212B, as shown in fig. 5D.
Specifically, the step S200 includes: performing plasma doping treatment on the active layer 21 to form the channel region 21A and a doping region 21B connected to the channel region 21A in the active layer 21, where the plasma is one or more of helium, argon, hydrogen, and oxygen, which is not limited in this embodiment; it should be noted that the plasma doping process performed on the active layer 21 is only for illustration, and the method for making the active layer 21 conductive is not particularly limited in this embodiment.
It can be understood that, in the present embodiment, the active layer 21 is subjected to the plasma doping process, so as to reduce the overlap resistance at the contact position between the active layer 21 and the source electrode 25A and the drain electrode 25B formed in the subsequent manufacturing process, and further improve the performance of the thin film transistor 20A, but when the active layer 21 is subjected to the conductor process at the position for contacting the source electrode 25A and the drain electrode 25B by using the plasma gas, the plasma gas diffuses from the doped region 21B to the channel region 21A, and therefore, in the prior art, when the active layer 21 is subjected to the doping process by using the plasma, the channel region 21A may lose the semiconductor performance.
Step S300: the doped region 21B is subjected to a plasma doping process so that the doped region 21B includes nitrogen atoms, and the nitrogen atoms fill at least part of the oxygen vacancies, as shown in fig. 5E.
Specifically, in the step S300, the doping region 21B is subjected to plasma doping treatment, and the plasma includes one or more mixed gases of nitrogen and nitrous oxide; preferably, in this embodiment, the technical solution of the present application is illustrated by taking the plasma as nitrous oxide as an example.
It is understood that the present embodiment improves the carrier transport rate by providing the doped region 21B to include nitrogen ions that fill at least part of the oxygen vacancies, thereby reducing the oxygen vacancies in the active layer 21; meanwhile, when the active layer 21 is conducted with a conductor treatment by using a plasma gas, the plasma gas can be effectively prevented from diffusing to the channel region 21A, the channel region 21A is prevented from losing semiconductor characteristics in the conductor treatment process of the active layer 21, and the working stability of the display panel device is further maintained; in addition, the lattice structure in the active layer 21 material is not affected by the nitrogen ion doping, and the doping amount is controllable and the process is simple.
In this embodiment, the method for manufacturing the display panel further includes the following steps:
step S400: sequentially forming an interlayer insulating layer 24 and a first metal layer 25 on the gate electrode 23A;
specifically, the step S400 includes the steps of:
step S401: forming an interlayer insulating layer 24 on the side of the gate 23A far away from the gate insulating layer 22 by adopting a physical vapor deposition process, wherein the thickness of the interlayer insulating layer 24 ranges from 2000 to 10000 angstroms, the interlayer insulating layer 24 has strong water and oxygen barrier capability and insulating capability, and the material of the interlayer insulating layer includes but is not limited to silicon oxide (SiO) X ) Silicon nitride (SiN) X ) Silicon oxynitride (SiNO), or the like, or a stack thereof.
Step S402: patterning the interlayer insulating layer 24 to form a via hole exposing a portion of the doped region 21B; specifically, the interlayer insulating layer 24 is provided with a first via hole exposing a portion of the first doped region 211B and a second via hole exposing a portion of the second doped region 212B.
Step S403: the first metal layer 25 is formed on the interlayer insulating layer 24 by using a physical vapor deposition method, the thickness of the first metal layer 25 ranges from 2000 to 8000 angstrom, the material of the first metal layer 25 includes, but is not limited to, a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), and/or titanium (Ti), and may include a single layer or a plurality of layers including the above materials.
Step S404: patterning the first metal layer 25 to form a source 25A and a drain 25B arranged at an interval, where the source 25A contacts the first doped region 211B through the first via hole, and the drain 25B contacts the second doped region 212B through the second via hole, as shown in fig. 5F; the first metal layer 25 is preferably patterned by yellow light and wet etching.
Step S500: forming a passivation layer 30 on the side of the first metal layer 25 far away from the interlayer insulating layer 24, wherein the thickness of the passivation layer 30 ranges from 1000 angstroms to 5000 angstromsAnd the material of the passivation layer 30 includes, but is not limited to, silicon oxide (SiO) X ) Silicon nitride (SiN) X ) Etc., or a stack thereof, and a method of fabricating the passivation layer 30 includes, but is not limited to, a vapor deposition method.
Step S600: forming a bridging portion 40 on a side of the passivation layer 30 away from the first metal layer 25, as shown in fig. 5G; the material of the bridge portion 40 is a metal material including, but not limited to, at least one metal of molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), and tungsten (W).
Specifically, the step S500 includes patterning the passivation layer 30 to form a third via hole exposing a portion of the drain electrode 25B, and the bridging portion 40 is connected to the drain electrode 25B through the third via hole.
Step S700, forming a flat layer 50 on one side of the bridging part 40 far away from the first metal layer 25, and carrying out patterning treatment on the flat layer 50 to form a fourth through hole exposing a part of the bridging part 40; preferably, the thickness of the planarization layer 50 ranges from 10000 to 30000 angstroms, and the planarization layer 50 can be formed by Chemical Vapor Deposition (CVD).
Step S800, forming a pixel defining layer 70, a light-emitting device layer 60 and a packaging layer 80 in sequence on one side of the flat layer 50 far away from the bridging part 40, as shown in FIG. 2; the light-emitting device layer 60 includes an anode 61, a light-emitting layer 62 and a cathode 63 stacked on the planarization layer 50, wherein the anode 61 is a stacked structure of indium tin oxide/silver/indium tin oxide; the pixel defining layer 70, the light emitting layer 62, the cathode 63, and the encapsulating layer 80 are conventional film layers widely used in the prior art, and the description of this embodiment is omitted.
This embodiment provides a display device, which includes the display panel described in any of the above embodiments.
It is to be understood that the display panel has been described in detail in the above embodiments, and the description is not repeated here.
In specific application, the display device can be a display screen of a smart phone, a tablet computer, a notebook computer, an intelligent bracelet, an intelligent watch, intelligent glasses, an intelligent helmet, a desktop computer, an intelligent television or a digital camera, and even can be applied to an electronic device with a flexible display screen.
The application provides a display panel, a manufacturing method thereof and a display device, wherein the display panel comprises a thin film transistor layer which is arranged on a substrate in a stacking mode, the thin film transistor layer comprises an active layer, a grid electrode insulating layer and a grid electrode, the active layer is made of metal oxide, the active layer comprises a channel region and a doped region which is connected with the channel region, and the orthographic projection of the grid electrode on the substrate covers the orthographic projection of the channel region on the substrate; wherein the doped region comprises a plurality of oxygen vacancies, and nitrogen ions that at least fill a portion of the oxygen vacancies; by providing the channel region to include nitrogen ions that fill at least a portion of the oxygen vacancies, thereby reducing oxygen vacancies in the active layer, the carrier transport rate is increased.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
The display panel, the manufacturing method thereof, and the display device provided in the embodiments of the present application are described in detail above, and specific examples are applied in the description to explain the principle and the implementation of the present application, and the description of the embodiments above is only used to help understanding the technical solution and the core idea of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.

Claims (10)

1. A display panel, comprising:
a substrate;
the thin film transistor layer is arranged on the substrate and comprises an active layer, a grid electrode insulating layer and a grid electrode, wherein the active layer, the grid electrode insulating layer and the grid electrode are arranged above the substrate, the active layer is made of metal oxide, the active layer comprises a channel region and a doped region connected with the channel region, and the orthographic projection of the grid electrode on the substrate covers the orthographic projection of the channel region on the substrate;
wherein the doped region comprises a plurality of oxygen vacancies and at least a portion of the oxygen vacancies are filled with nitrogen ions.
2. The display panel according to claim 1, wherein a concentration of the nitrogen ions is smaller than a concentration of the oxygen vacancies.
3. The display panel of claim 1, further comprising a first metal layer stacked on the active layer, wherein the doped region comprises a landing region connected to the first metal layer and a doped sub-region located between the landing region and the channel region, and wherein a concentration of nitrogen ions in the doped sub-region is less than a concentration of nitrogen ions in the landing region.
4. The display panel according to claim 3, wherein the first metal layer comprises a source electrode and a drain electrode, the landing zone comprises a first landing zone in contact with the source electrode and a second landing zone in contact with the drain electrode, and the channel region is located between the first landing zone and the second landing zone;
wherein a width of the channel region is less than or equal to 3 micrometers in a direction in which the first lap region points toward the second lap region.
5. The display panel of claim 4, wherein the doped sub-regions comprise a first doped sub-region and a second doped sub-region, the first doped sub-region being located between the first landing region and the channel region, the second doped sub-region being located between the second landing region and the channel region;
wherein the concentration of nitrogen ions in the first doped sub-region is less than that in the first overlapping region, and the concentration of nitrogen ions in the second doped sub-region is less than that in the second overlapping region.
6. The display panel of claim 1, wherein the thin-film transistor layer further comprises a second metal layer, the second metal layer comprising the gate electrode;
the second metal layer comprises a first sub-metal layer and a second sub-metal layer which are arranged on the substrate in a laminated mode, wherein the material of the second sub-metal layer comprises an inert metal material, and the electric conductivity of the first sub-metal layer is larger than that of the second sub-metal layer.
7. The display panel according to claim 6, wherein the material of the second sub-metal layer comprises at least one of molybdenum, titanium, and a molybdenum-titanium alloy, and the material of the first sub-metal layer comprises at least one of copper, aluminum, and silver.
8. The display panel according to claim 7, wherein the second metal layer further comprises a third sub-metal layer located between the first sub-metal layer and the gate insulating layer, and a material of the third sub-metal layer comprises at least one of molybdenum, titanium, and a molybdenum-titanium alloy.
9. A manufacturing method of a display panel is characterized by comprising the following steps:
providing a substrate, and sequentially forming an active layer, a gate insulating layer and a gate on the substrate;
conducting treatment on the active layer to form a channel region and a doped region connected with the channel region, wherein the orthographic projection of the grid electrode on the substrate covers the orthographic projection of the channel region on the substrate, and the doped region comprises a plurality of oxygen vacancies;
and carrying out plasma doping treatment on the doped region to enable the doped region to comprise nitrogen atoms, wherein the nitrogen atoms at least fill part of the oxygen vacancies.
10. A display device characterized in that it comprises a display panel as claimed in claims 1-8.
CN202210922518.5A 2022-08-02 2022-08-02 Display panel, manufacturing method thereof and display device Pending CN115224053A (en)

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